Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins to define multi fin field effect transistors (FinFETs). Dielectric sidewalls on fins protect the sidewalls while the surface is damaged intentionally, e.g., with an implant that leaves source/drain junctions undisturbed. After removing the dielectric sidewalls semiconductor material is grown epitaxially on the sidewalls with the damage retarding growth on the surface. The epi-growth bridges between fins in the same FET. After the damage is repaired, chip processing continues normally.

Abstract: An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit.

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

Abstract: A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.

Abstract: In a liquid crystal display device it is desirable to test in the state of TFT substrates, without reducing the number of TFT substrates to be obtained from one mother TFT substrate, and without increasing the overall size of the TFT substrates. Test terminals are formed on the outside of terminals for driving the liquid crystal display device. The test terminals of the specific TFT substrate are formed in another TFT substrate just below the specific TFT substrate. The area in which the test lines are formed is a space in which a sealing material is formed, between the display area and an end of the lower TFT substrate. Thus, the size of the TFT substrates is not actually increased. A test line area is not separately formed and not discarded, so that the number of TFT substrates to be obtained from one mother TFT substrate is not reduced.

Abstract: A semiconductor device includes: a resin case that houses a semiconductor element; a parallel plate that is disposed inside the resin case while being connected with the semiconductor element, the parallel plate including two flat plates parallel to each other with an insulating material therebetween; and two electrodes that are each led out from an upper end of the parallel plate and are disposed on an upper surface of the resin case at a predetermined interval. Upper end portions of the two flat plates of the parallel plate between two electrode lead-out portions are bent toward the outside being a direction in which the upper end portions of the two flat plates become more distant from each other, the two electrodes being led out from the corresponding two electrode lead-out portions.

Abstract: A package substrate is disclosed. The package substrate includes a molding layer, a redistribution structure, and a build-up structure. The redistribution structure is embedded in the molding layer with a surface exposed by the molding layer. The build-up structure is formed on the bottom surface of the molding layer. An inner stress caused by a CTE difference between different materials in the package substrate is reduced by forming at least one groove which is arranged around the periphery of the redistribution structure onto the top surface of the molding layer, thereby improving the problem of the redistribution structure cracking in the prior art.

Abstract: The invention provides a package structure which includes a substrate, at least one chip module, and a housing. The at least one chip module is located on the substrate. The housing includes an upper cover, a surrounding wall, and at least one adhesion enhancement structure. The surrounding wall is connected to the upper cover and encompasses the at least one chip module. The surrounding wall and the adhesion enhancement structure are bonded to the substrate by an adhesive. The adhesion enhancement structure includes an encircled hole or a semi-encircled hole.

Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

Abstract: Package structures and methods of forming the same are disclosed. A package structure includes a die, a dielectric layer, an encapsulant and a plurality of supports. The die includes, over a first side thereof, a plurality of connectors. The dielectric layer is formed over the first side of the die aside the connectors. The encapsulant is aside the die. The supports penetrate through the dielectric layer. The grinding rate of the supports is substantially the same as that of the encapsulant but different from that of the dielectric layer.

Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.

Abstract: Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.

Abstract: A semiconductor device includes: a substrate; a semiconductor chip mounted over the substrate and having a solder bump coupled by soldering with an electrode over the substrate; and a heating unit for locally generating heat in a corner part within the horizontal plane of the semiconductor chip when an operating temperature of the semiconductor chip is equal to or less than a prescribed temperature.

Abstract: A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted.

Abstract: In a conventional semiconductor device, a pattern serving as a heat dissipating material is formed by applying a phase transition material. Provided is a semiconductor device that can reduce collapse of a pattern shape even if a shock is applied to the pattern formed with the phase transition material that is liquefied when the environmental temperature is not sufficiently controlled. The semiconductor device includes semiconductor elements mounted inside a semiconductor module (10); a heat radiating surface (13), formed in the semiconductor module (10), dissipating heat generated in the semiconductor elements to a heat radiator; a pattern (14) formed on the heat radiating surface and made from a phase transition material; and a film (15) serving as a first film that covers the pattern (14).

Abstract: A semiconductor device includes: a stacked unit including a semiconductor module and a plurality of coolers each having a flow passage through which a coolant flows, the semiconductor module being disposed between the coolers; a coolant supply-discharge pipe configured to supply the coolant to the coolers or discharge the coolant from the coolers, the coolant supply-discharge pipe being passed through the stacked unit in a stacking direction of the stacked unit; a displacement restricting member provided at a first end portion of the coolant supply-discharge pipe, the displacement restricting member being configured to restrict displacement of the stacked unit in the stacking direction of the stacked unit; and a pressurizing member provided at a second end portion of the coolant supply-discharge pipe, the pressurizing member being configured to apply force to the stacked unit in a direction toward the first end portion.

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.

Abstract: Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame.

Abstract: To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads.

Abstract: A semiconductor device (100) comprising a leadframe with a pad (101) and elongated leads (103) made of a base metal plated with a layer enabling metal-to-metal bonding; a semiconductor chip (110) attached to the pad, the chip having terminals. A metallic wire connection (130) from a terminal to a respective lead, the connection including a first ball bond by a first squashed ball (131) attached to the terminal, and a first stitch bond (132) attached to the lead. A second squashed ball (150) of the wire metal attached to the lead as a second ball bond adjacent to the first stitch bond (132). A package (170) of a polymeric compound encapsulating the chip, wire connection, second ball and at least a portion of the elongated lead, the compound adhering to the materials of the encapsulated entities.

Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Abstract: An integrated circuit arrangement includes a flange, a transistor die, and a first conducting element defining a lead. The flange includes a conducting material and the transistor die is disposed on a surface of the flange. The first conducting element is electrically connected to the transistor die via connecting elements to allow current flow from the transistor die. The flange defines return current paths allowing the current flow via the connecting elements and the lead to return to the transistor die. The flange includes one or more reduced thickness portions that are configured to limit the return current paths and control current flow passing through the flange to the transistor die.

Abstract: An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface.

Abstract: Provided is an etching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with a chip. The structure comprises a metal substrate frame, wherein a base island and pins are arranged in the metal substrate frame; a chip is inversely arranged on a front face of the base island and the pins; a conductive pillar is arranged on a front face of the pins; the region on the periphery of the base island, the region between the base island and the pins, the region between one pin and another, the region above the base island and the pins, the region below the base island and the pins, and the outside of the chip and the conductive pillar are all enveloped with a plastic packaging material.

Abstract: A method of producing a multiplicity of surface-mountable carrier devices includes: A) providing a carrier plate having a first main face and a second main face located opposite the first main face, B) applying an electrically conductive layer to the first main face, C) applying a solder resist mask to a side of the electrically conductive layer remote from the carrier plate, wherein a multiplicity of adjoining regions are formed on the electrically conductive layer by the solder resist mask, D) applying a solder material to the solder resist mask and the electrically conductive layer, wherein the solder resist mask and the electrically conductive layer are at least partially covered by the solder material, and E) singulating the carrier plate and the electrically conductive layer along and through the solder resist mask and the solder material, wherein the solder material remains at least partially on the solder resist mask.

Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.

Abstract: An apparatus includes a contact grid array disposed on a substrate in a non-orthogonal row-column format with connection elements arranged in a hexagonal configuration. The contact grid array has an orientation based, at least in part, on an area available for the contact grid array on the substrate. A method to determine the orientation of the contact grid array includes identifying the area available for a contact grid array on a substrate and determining the orientation for the contact grid array based, at least in part, on the area available for the contact grid array on the substrate.

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract: A wiring substrate includes a first wiring substrate, a first insulation layer covering the first wiring layer, a second insulation layer stacked on the first insulation layer, and a cavity extending through the second insulation layer and exposing a portion of the upper surface of the first insulation layer. The cavity includes an opening, which is defined by an upper portion of a stepped inner wall surface of the second insulation layer, and a recess, which is defined by a lower portion of the stepped inner wall surface that contacts the upper surface of the first insulation layer. The recess is wider than the opening. An electronic component is mounted on the upper surface of the first insulation layer. The opening and the recess are filled with a third insulation layer that covers the electronic component and the second insulation layer.

Abstract: A wiring substrate includes a first wiring substrate, a first insulation layer stacked on the first wiring layer, and second and third insulation layers sequentially stacked on the first insulation layer. An electronic component is mounted on the first insulation layer in a cavity extending through the second and third insulation layers. The cavity is filled with a fourth insulation layer that entirely covers an upper surface of the third insulation layer and covers the electronic component. A second wiring layer is incorporated in the second and third insulation layers and electrically connected to the first wiring layer. The second wiring layer is electrically connected to a third wiring layer, which is stacked on the fourth insulation layer, by a first via wiring extending through the second and third insulation layers.

Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.

Abstract: A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

Abstract: An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.

Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

Abstract: A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view.

Abstract: A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer.

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Abstract: In some embodiments, an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers.

Abstract: A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard mask layer on the barrier metal layer, patterning a resist on the hard mask layer, patterning the hard mask layer by dry-etching the hard mask layer with the patterned resist as a mask, cleaning a surface of the barrier metal layer with a cleaning solution after the patterning the hard mask layer, and dry-etching the multilayered film with the patterned hard mask layer as a mask after the cleaning the surface of the barrier metal layer. In the patterning the hard mask layer, dry etching is performed with a ratio of a flow rate of an oxidizing gas to a total flow rate of a process gas at less than 1% in a state in which the barrier metal layer is exposed to the process gas.

Abstract: Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A gate cap encapsulates the at least one gate electrode. The semiconductor device further includes at least one contact separated from the at least one gate electrode via a portion of the gate cap. The at least one contact includes a metal portion that directly contacts the gate cap.

Abstract: A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad.

Abstract: A method of processing a substrate that displays out-gassing when placed in a vacuum comprises placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T1 and removing gaseous contamination emitted from the substrate until the out-gassing rate is determined by the diffusion of the substrate's contamination and thus essentially a steady state has been established. Afterwards, the temperature is lowered to a temperature T2 at which the diffusion rate of the substrate's contamination is lower than at T1. The substrate is further processed at said temperature T2 until the substrate has been covered with a film comprising a metal.

Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.