Abstract: In one embodiment, an integrated circuit includes an array of active structures, an array of dummy structures and multiple well-tap structures. The array of dummy structures surrounds the array of active structures. The well-tap structures may be interposed between the array of active structures and the array of dummy structures. In one embodiment, each of the well-tap structures may include a well, a diffusion region and a gate-like structure. The well may be formed in a substrate and is of a first doping type. The diffusion region may be formed in the well and is also of the first doping type. The gate-like structure may be formed above the substrate and adjacent to the diffusion region.

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

Abstract: A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

Abstract: Methods and apparatus for training a multi-layer artificial neural network for use in speech recognition. The method comprises determining for a first speech pattern of the plurality of speech patterns, using a first processing pipeline, network activations for a plurality of nodes of the artificial neural network in response to providing the first speech pattern as input to the artificial neural network, determining based, at least in part, on the network activations and a selection criterion, whether the artificial neural network should be trained on the first speech pattern, and updating, using a second processing pipeline, network weights between nodes of the artificial neural network based, at least in part, on the network activations when it is determined that the artificial neural network should be trained on the first speech pattern.

Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region.

Abstract: A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion. First and second contact trenches extend continuously along the first gate structure portion for less than the axial length of the gate structure and are positioned above at least a portion of the active region on respective opposing first and second sides of the gate structure. An epi semiconductor material is positioned on the active region within each of the first and second contact trenches.

Abstract: A method is provided for forming an integrated circuit. A doped silicon layer is formed on a silicon substrate. A silicon-germanium layer is subsequently formed on the doped silicon layer. The silicon-germanium layer is pattered to form a silicon-germanium feature. A silicon shell is formed on the silicon-germanium feature. At least a portion of the dopes silicon layer is converted to a porous silicon layer. Following the last step, the silicon shell is tensily stressed, making it a good candidate for use as a channel feature in an n-type field effect transistor.

Abstract: Provided is a FinFET device including a substrate having at least one fin, first and second gate stacks, first and second strained layers, a shielding layer and first and second connectors. The first and second gate stacks are across the fin. The first and second strained layers are respectively aside the first and second gate stacks. The shielding layer is over the second gate stack, over a top surface and a sidewall of the first gate stack and discontinuous around a top corner of the first gate stack. The first connector is through the shielding layer and is electrically connected to the first stained layer. The second connector is through the shielding layer and is electrically connected to the second stained layer. Besides, the width of the second connector is greater than the width of the first connector.

Abstract: A fin field effect transistor (FinFET) with improved electrical performance and a method of manufacturing the same are disclosed. A FinFET includes a substrate having a top surface and an insulation. At least a recessed fin is extended upwardly from the top surface of the substrate, and at least a gate stack is formed above the substrate, wherein the gate stack is extended perpendicularly to an extending direction of the recessed fin, and the recessed fin is outside the gate stack. The insulation includes a lateral portion adjacent to the recessed fin, and a central portion contiguous to the lateral portion, wherein a top surface of the lateral portion is higher than a top surface of the central portion. A top surface of the recessed fin is lower than the top surface of the central portion of the insulation.

Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: The present disclosure provides a TFT, a method for manufacturing the same, an array substrate and a display device, so as to effectively reduce a TFT edge leakage current IOFF (edge). The TFT includes an active layer and a silicon oxide layer arranged at a lateral side of the active layer.

Abstract: A method of forming a semiconductor device is disclosed. At least one suspended first semiconductor nanowire and two first semiconductor blocks at two ends of the first semiconductor nanowire are formed in a first area, and at least one suspended second semiconductor nanowire and two second semiconductor blocks at two ends of the second semiconductor nanowire are formed in a second area. A transforming process is performed, so the first semiconductor nanowire is transformed into a nanowire with stress, and the second semiconductor blocks are simultaneously transformed into two blocks with stress. First and second gate dielectric layers are formed respectively on surfaces of the nanowire with stress and the second semiconductor nanowire. First and second gates are formed respectively across the nanowire with stress and the second semiconductor nanowire.

Abstract: Provided is a semiconductor device in which deterioration of electrical characteristics can be suppressed. The semiconductor device includes a first oxide semiconductor layer over an insulating surface, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer whose one surfaces are in contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer, a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a gate insulating film over the third oxide semiconductor layer, and a gate electrode layer over the gate insulating film. The second oxide semiconductor layer wholly overlaps with the first oxide semiconductor layer. Part of the third oxide semiconductor layer is in contact with the other surfaces of the source electrode layer and the drain electrode layer.

Abstract: An oxide thin film transistor, an array substrate, methods of manufacturing the same and a display device are disclosed. The oxide thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an oxide active layer, drain/source electrodes sequentially disposed on the base substrate. The oxide TFT transistor further includes an ultraviolet barrier layer disposed on the oxide active layer, the ultraviolet barrier layer is made of a resin material contains an ultraviolet absorbent. The stability of the oxide TFT is enhanced by disposing the ultraviolet barrier layer over the oxide active layer of the oxide TFT, since the ultraviolet barrier layer blocks the impact of UV light on the oxide TFT.

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

Abstract: A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

Abstract: The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.

Abstract: A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.

Abstract: A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H—SiC body.

Abstract: A solar cell module includes: two solar cells, each including: a first main face and a second main face; a first electrode on the first main face, comprising a bus-bar electrode having at least one of an opening portion, notch portion, and gap portion; and a second electrode on the first or second main face having a polarity opposite to that of the first electrode; a wiring member that electrically connects the first electrode of one solar cell to the second electrode of another solar cell; and an electrically conductive connection layer that contacts the wiring member and the first main face.

Abstract: An electronics module docking system includes docking member removably coupled to a photovoltaic module. The docking system includes a first connector port electrically coupled to one or more photovoltaic cells of the photovoltaic module. The photovoltaic module is selectively coupleable to the docking member. The docking system includes a housing to enclose an electronics module. The housing may include second connector port that is selectively engageable to the power electronics module. The power electronics module and the photovoltaic cells are electrically coupled to one another upon selective engagement of the connector ports. The inverter housing is receivable by and removably coupleable to the docking member allowing the inverter housing to be removably coupleable to the photovoltaic module.

Abstract: The present invention relates to a composition for preparing solar cell electrodes including: a silver (Ag) powder; a glass frit containing about 0.1 mole % to about 50 mole % of elemental silver; and an organic vehicle, the composition introduces a glass frit including a silver cyanate or a silver nitrate to enhance contact efficiency between an electrode and a wafer, and solar cell electrodes prepared from the composition have minimized contact resistance (Rc) and serial resistance (Rs), thereby exhibiting excellent conversion efficiency.

Abstract: The solar cell (1) of the present invention is provided with an n-side electrode (14), a p-side electrode (15), and a photoelectric conversion unit (20) having a first main surface (20a) and a second main surface (20b). The first main surface (20a) includes an n-type surface (20an) and a p-type surface (20ap). The photoelectric conversion unit (20) has a semiconductor substrate (10) and a semiconductor layer (12n). The semiconductor substrate (10) has first and second main surfaces (10b, 10a). The semiconductor layer (12n) is arranged on a portion of the first main surface (10b). The semiconductor layer (12n) constitutes either the n-type surface (20an) or the p-type surface (20ap). The semiconductor layer (12n) includes a relatively thick portion (12n1) and a relative thin portion (12n2). The n-side electrode (14) or the p-side electrode (15) is arranged on at least the relatively thin portion (12n2) of the semiconductor layer (12n).

Abstract: Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask.

Abstract: An optical assembly includes an image sensor, a lens module disposed over the image sensor in a first direction, a transparent glue layer, and a transparent dry adhesive layer formed of a different material than the transparent glue layer. Each of the transparent glue layer and the transparent dry adhesive layer are disposed between the image sensor and the lens module in the first direction. Each of the transparent glue layer and the transparent dry adhesive layer are optically coupled in series with the image sensor and the lens module. A method for forming an optical assembly includes joining an image sensor and a lens module using a transparent glue layer and a transparent dry adhesive layer formed of a different material than the transparent glue layer.

Abstract: A radiographic image detector includes a phosphor layer, a heat shield layer, and a photoelectric converter in this order, wherein the heat shield layer has a thickness T (?m) and a thermal conductivity C (W/m·K) satisfying that C/T is from 0.004 to 5.

Abstract: A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate.

Abstract: In various embodiments of the present disclosure, there is provided a method of manufacturing a monolayer graphene photodetector, the method including forming a graphene quantum dot array in a graphene monolayer, and forming an electron trapping center in the graphene quantum dot array. Accordingly, a monolayer graphene photodetector is also provided.

Abstract: The present invention discloses a photo-detector comprising: an n-type photon absorbing layer of a first energy bandgap; a middle barrier layer, an intermediate layer is a semiconductor structure; and a contact layer of a third energy bandgap, wherein the layer materials are selected such that the first energy bandgap of the photon absorbing layer is narrower than that of said middle barrier layer; wherein the material composition and thickness of said intermediate layer are selected such that the valence band of the intermediate layer lies above the valence band in the barrier layer to create an efficient trapping and transfer of minority carriers from the barrier layer to the contact layer such that a tunnel current through the barrier layer from the contact layer to the photon absorbing layer is less than a dark current in the photo-detector and the dark current from the photon-absorbing layer to said middle barrier layer is essentially diffusion limited and is due to the unimpeded flow of minority carrier

Abstract: An optoelectronic device comprising: a first conductive layer, a second conductive layer, an active layer between the first conductive layer and the second conductive layer, wherein the active layer comprises a submicrometer size structure of hexagonal type crystals of an element or alloy of elements selected from the carbon group.

Abstract: A photovoltaic solar cell assembly includes a bypass diode, a first and a second planar solar cell. Each of the first and the second solar cell includes a front facing side and a rear facing side, each rear facing side including a respective conductive surface, each front facing side including a respective current collector bar, and corresponding grid of metallic lines conductively coupled with the current collector bar. A first terminal of the bypass diode is electrically coupled with the conductive surface of the first solar cell. A second terminal of the bypass diode is electrically coupled with the current collector bar of the second solar cell. Electrical coupling of the bypass diode with the first solar cell and the second solar cell excludes any external wiring or busbar.

Abstract: Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A conductive contact structure is disposed above the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal seed material regions providing a metal seed material region disposed on each of the alternating N-type and P-type semiconductor regions. A metal foil is disposed on the plurality of metal seed material regions, the metal foil having anodized portions isolating metal regions of the metal foil corresponding to the alternating N-type and P-type semiconductor regions.

Abstract: Disclosed is a method for manufacturing a solar cell module (10), said method being provided with: a first step for a first step for manufacturing a laminated body by sequentially stacking and thermocompression-bonding a solar cell (11), sealing material (14), first protection member (12) and second protection member (13); and a second step, which is a step of heating the solar cell (11) of the laminated body, and in which the sealing material (14) is indirectly heated due to a temperature increase of the solar cell (11).

Abstract: Disclosed is a photovoltaic device comprising a substrate composed of an oriented polycrystalline zinc oxide sintered body in a plate shape, a photovoltaic layer provided on the substrate, and an electrode provided on the photovoltaic layer. According to the present invention, a photovoltaic device having high photoelectric conversion efficiency can be inexpensively provided.

Abstract: The present disclosure includes devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays. In some aspects, the detectors and arrays include a virtual beveled edge mesa structure surrounded by resistive material damaged by ion implantation and having side wall profiles that taper inwardly towards the top of the mesa structures, or towards the direction from which the ion implantation occurred. Other aspects are directed to masking and multiple implantation and/or annealing steps. Furthermore, methods for fabricating and using such devices, circuits and arrays are disclosed.

Abstract: A display substrate includes a pixel switching element, a pixel electrode, a reference line, a control switching element, a bias line, a light sensing element, a sensing capacitor and a light blocking filter pattern. The pixel switching element is connected to a data line and a gate line, includes a first semiconductor pattern. The pixel electrode is connected to the pixel switching element. The reference line is in parallel with the data line. The control switching element is connected to the reference line and the gate line, includes a second semiconductor pattern. The bias line is in parallel with the gate line. The light sensing element is connected to the bias line and the control switching element, includes a third semiconductor pattern. The sensing capacitor is connected to the light sensing element and a storage line. The light blocking filter pattern transmits a first light, and blocks a second light.

Abstract: An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface.

Abstract: A light receiving and emitting element module includes a substrate; a light emitting element and a light receiving element on an upper surface of the substrate; a frame-shaped outer wall that on the upper surface of the substrate; and a light shielding wall that is positioned inside the outer wall and partitions an internal space of the outer wall into spaces respectively corresponding to the light emitting element and the light receiving element. The light shielding wall includes a light emitting element-side shading surface on the light emitting element side, a light receiving element-side shading surface on the light receiving element side, and a lower surface that is connected to each of the light emitting element-side shading surface and the light receiving element-side shading surface, and that faces the substrate. The lower surface has an inclined surface inclined with respect to the upper surface of the substrate.

Abstract: An optical sensor is described that includes a light emitter and a photodetector assembly directly attached to a transparent substrate. In one or more implementations, the optical sensor comprises at least one light emitter and a photodetector assembly (e.g., photodiodes, phototransistors, etc.). The light emitter(s) and the photodetector assembly are directly mounted (e.g., attached) to a transparent substrate.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: Monolithic tandem chalcopyrite-perovskite photovoltaic devices and techniques for formation thereof are provided. In one aspect, a tandem photovoltaic device is provided. The tandem photovoltaic device includes a substrate; a bottom solar cell on the substrate, the bottom solar cell having a first absorber layer that includes a chalcopyrite material; and a top solar cell monolithically integrated with the bottom solar cell, the top solar cell having a second absorber layer that includes a perovskite material. A monolithic tandem photovoltaic device and method of formation thereof are also provided.

Abstract: A method of applying a fluorescent material to a surface includes providing a substrate, providing a semiconductor light-emitting stack on the substrate, bonding the substrate to the semiconductor light-emitting stack, and overlaying top and side surfaces of the semiconductor light-emitting stack with the fluorescent material, wherein the fluorescent material contains no binding material.

Abstract: The present invention relates to an epitaxial wafer for a light-emitting diode wherein the peak emission wavelength is 655 nm or more, and it is possible to improve reliability. The epitaxial wafer for light-emitting diodes includes a GaAs substrate (1) and a pn-junction type light-emitting unit (2) provided on the GaAs substrate (1), wherein light-emitting unit (2) is formed as a multilayer structure in which a strained light-emitting layer and a barrier layer are alternately stacked, and the composition formula of the barrier layer is (AlXGa1-X)YIn1-YP (0.3?X?0.7, 0.51?Y?0.54).

Abstract: An LED device capable of emitting electromagnetic radiation ranging from about 200 nm to 365 nm, the device. The device includes a substrate member, the substrate member being selected from sapphire, silicon, quartz, gallium nitride, gallium aluminum nitride, or others. The device has an active region overlying the substrate region, the active region comprising a light emitting spatial region comprising a p-n junction and characterized by a current crowding feature of electrical current provided in the active region. The light emitting spatial region is characterized by about 1 to 10 microns. The device includes an optical structure spatially disposed separate and apart the light emitting spatial region and is configured to facilitate light extraction from the active region.