Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Abstract: FinFET devices and methods of forming the same are disclosed. One FinFET device includes a substrate with first and second fins in a first region and third and fourth fins in a second region, and first to fourth gates respectively across the first to fourth fins. The first end sidewall of the first gate is faced to the second end sidewall of the second gate, and a first opening is formed between the first and second end sidewalls. The third end sidewall of the third gate is faced to the fourth end sidewall of the fourth gate, and a second opening is formed between the third and fourth end sidewalls. The first and second regions have different pattern densities, and the included angle between the sidewall of the first opening and the substrate is different from the included angle between the sidewall of the second opening and the substrate.

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Abstract: Techniques for effectively confining n-well dopants during fabrication of relaxed SiGe on SRB devices are provided. In one aspect, a method for forming a semiconductor device includes the steps of: forming a SiGe stress relief buffer layer on a substrate; growing a bottom confinement layer on the stress relief buffer layer; growing a SiGe layer on the bottom confinement layer; growing a top confinement layer on the SiGe layer; forming STI regions extending through the top confinement layer, through the SiGe layer, and at least down to the bottom confinement layer, wherein the STI regions define at least one active area in the SiGe layer; and implanting at least one well dopant into the at least one active area which is confined to the at least one active area by the top confinement layer, the bottom confinement layer, and the STI regions. A semiconductor device is also provided.

Abstract: Embodiments of the present disclosure provide a structure including: a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a gate and source drain region adjacent to the sidewall spacers, a distance between the pFET source drain region and the pFET gate is substantially equal to a distance between the nFET source drain region and the nFET gate.

Abstract: A semiconductor device includes a first MOS transistor and a second MOS transistor of a second conductivity type. The first MOS transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential. The second MOS transistor includes a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential. The control electrodes of the first and second MOS transistors are connected in common. The first and second MOS transistors are formed on a common wide bandgap semiconductor substrate. In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide bandgap semiconductor substrate. In the second MOS transistor, a main current flows in a direction parallel to the main surface of the wide bandgap semiconductor substrate.

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

Abstract: A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

Abstract: A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines.

Abstract: The memory system has an overwrite operation and an operation control method thereof. A nonvolatile memory device has a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate. When data of memory cells connected to a word line of a selected memory block is read, the need of reclaim is determined based on an error bit level of the read data. In the case that memory cells having an erase state among the memory cells connected to the word line become a soft program state, the read data is overwritten in the memory cells connected to the word line of the selected memory block.

Abstract: Methods to utilize efficient processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing mandrels separated from each other across two adjacent bit-cells on an upper surface of a dielectric layer on an upper surface of a silicon (Si) layer; forming first spacers on opposite sides of each mandrel; forming second spacers on exposed sides of the first spacers; removing the mandrels; removing exposed sections of the dielectric layer; removing the first and second spacers; forming fin-spacers on opposite sides of remaining sections of the dielectric layer; removing the remaining sections of the dielectric layer; removing exposed sections of the Si layer; and removing the fin-spacers to reveal Si fins.

Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Abstract: The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.

Abstract: A NAND flash memory has word lines in a memory array area and contact pads and lead lines in a word line hookup area, each of the word lines connected to a corresponding contact pad by a lead line. The word lines in the memory array area have a first height and low-profile areas of lead lines in the word line hookup area have a second height that is less than the first height.

Abstract: A nonvolatile memory cell includes an active region extending in a first direction, a selection gate electrode layer intersecting the active region and extending in a second direction, a floating gate electrode layer intersecting the active region, extending in the second direction, wherein the floating gate electrode layer extends in parallel to the selection gate electrode layer and is separated from the selection gate electrode layer, and a dielectric layer disposed between the selection gate electrode layer and the floating gate electrode layer. The selection gate electrode layer, the dielectric layer, and the floating gate electrode layer are located substantially at the same level and, in combination, form a lateral coupling capacitor, and a first end portion of the floating gate electrode layer overlaps the active region.

Abstract: A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

Abstract: A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.

Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.

Abstract: A semiconductor memory device according to an embodiment, includes a stacked body, a semiconductor member, a charge storage layer, a charge block layer and an electrode antioxidant layer. The stacked body includes a plurality of electrode layers stacked separated from each other and an inter-electrode insulating layer between the electrode layers. The semiconductor member extends in a stacking direction of the stacked body and penetrates the stacked body. The tunnel insulating layer is provided on a side surface of the semiconductor member. The charge storage layer is provided on a side surface of the tunnel insulating layer. The charge block layer is provided on a side surface of the charge storage layer and contains oxygen. The electrode antioxidant layer is provided between the charge block layer and the electrode layer and has a composition different from that of the electrode layer.

Abstract: A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes exposing the first sacrificial film on the bottom by removing the second sacrificial film on the bottom. The method includes making a gap between the second sacrificial film and a side surface of the lower portion of the hole by causing etching of the first sacrificial film to progress along the side surface of the lower portion of the hole from the exposed portion on the bottom. The method includes causing an end of at least one portion of the lower layer portion of the etching layer to recede in a diametrical direction of the hole by causing side etching to progress from an end of the lower layer portion of the etching layer exposed in the gap.

Abstract: A semiconductor device may include a multi-layered source layer, conductive patterns, interlayer insulating layers, and a channel pillar. The multi-layered source layer may include a lower source layer, an interlayer source layer, and an upper source layer. The conductive patterns and interlayer insulating layers may be alternately disposed on the multi-layered source layer. The channel pillar may penetrate the conductive patterns. The interlayer insulating layers, the upper source layer, and the interlayer source layer, the channel pillar may extend into the lower source layer. The channel pillar may be in contact with the interlayer source layer. Doped regions having various structures can be formed at a lower portion of the channel pillar, thereby improving the operational reliability of the semiconductor device.

Abstract: A memory cell includes: a polarizable member including an electret to store a plurality of bits; a thermal electrode to heat the polarizable member; and a program electrode opposing the thermal electrode to program the polarizable member in a bit comprising a polarized state or a non-polarized state, the polarizable member being interposed between the thermal electrode and the program electrode. A random access memory includes: a plurality of addressable memory cells, the memory cell including: a thermal electrode; a program electrode opposing the thermal electrode; a polarizable member interposed between the thermal electrode and the program electrode, the polarizable member including an electret to store a plurality of bits.

Abstract: A semiconductor device includes a 2-input NOR decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.

Abstract: A library of a DFM-improved standard logic cells (including D flip-flop cells) that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

Abstract: Three-dimensional (3D) transistors and methods of manufacturing thereof include a first semiconductor fin extending over a substrate. The first semiconductor fin has a vertical recess extending from a first sidewall of the first semiconductor fin toward a second sidewall of the first semiconductor fin opposite the first sidewall. A distance between two opposing sidewalls of the vertical recess decreases as the vertical recess extends toward the second sidewall of the first semiconductor fin. The device further includes a vertically recessed channel region between the second sidewall of the first semiconductor fin and a bottom of the vertical recess, source/drain (S/D) regions at opposite ends of the vertically recessed channel region, and a gate stack over the vertically recessed channel region.

Abstract: The invention provides a high-precision display device having a reliable top- and single-gate TFT causing less current leakage. Part of a gate line 10 that crosses a semiconductor layer 103 acts as a gate electrode to form a TFT. The semiconductor layer 103 is connected to a data line 20 via a through-hole 140 on one side of the TFT and also connected to a contact electrode 107 via a through-hole 120 on the other side of the TFT. A floating electrode 30 is formed between the TFT and the through-hole 140 or between the TFT and the through-hole 120. The floating electrode 30 is formed on a layer above the semiconductor layer 103 with the use of the same material and at the same time as the gate electrode.

Abstract: The semiconductor device includes a transistor including an oxide semiconductor film, a first gate electrode overlapping with the oxide semiconductor film, a gate insulating film between the oxide semiconductor film and the first gate electrode, a first insulating film over the oxide semiconductor film, a pair of electrodes that are over the first insulating film and electrically connected to the oxide semiconductor film, a second insulating film over the first insulating film and the pair of electrodes, and a second gate electrode that is over the second insulating film and overlaps with the oxide semiconductor film. The first insulating film includes a region having a thickness of 1 nm or more and 50 nm or less, and the pair of electrodes includes a region in which a distance between the electrodes is 1 ?m or more and 6 ?m or less.

Abstract: The present invention provides a metallic oxide thin film transistor and its manufacturing method, an array substrate and its manufacturing method, as well as a display device, which is belong to the field of thin film transistor manufacturing technology. The method for manufacturing the metallic oxide thin film transistor comprises a step of forming patterns of an oxide active layer and an etch stopping layer through a one-time patterning process.

Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.

Abstract: An array substrate is disclosed. The array substrate includes gate lines and data lines, and first and second signal lines. A first data line is between first and second pixel units, respectively including first and second film transistors. A first gate line is electrically connected to the gate electrodes of the first and second film transistors. The second electrode of the second film transistor is electrically connected to the first data line, and the second electrode of the first film transistor is electrically connected to the first signal line. The array substrate also includes a common electrode layer partially located between a third pixel unit and the first pixel unit, which is electrically insulated. In addition, a portion of the common electrode layer between the first pixel unit and the second pixel unit overlaps the first data line.

Abstract: A method of manufacturing a display apparatus includes: preparing a substrate including a pixel circuit region and a driving circuit region; forming a first active layer at the pixel circuit region; forming a second active layer at the driving circuit region; forming gate electrodes that overlap the first active layer and the second active layer, respectively, with a gate insulating layer disposed therebetween; forming a first insulating layer covering the first and second active layers; forming a first contact hole that passes through the first insulating layer until a portion of the first active layer is exposed; heat-treating the substrate where the first insulating layer, in which the first contact hole is formed, is formed; and forming a second contact hole that passes through the first insulating layer disposed on the heat-treated substrate until a portion of the second active layer is exposed.

Abstract: Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor. A gate of the first transistor is electrically connected to a source or drain electrode of the second transistor. The second transistor has a semiconductor layer including the oxide semiconductor over the source and drain electrodes and a gate electrode over the semiconductor layer with an insulating layer therebetween.

Abstract: A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel unlike the related art and thus thickness and manufacturing cost are reduced.

Abstract: A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to yield the resultant electronic device.

Abstract: An array substrate and manufacturing method thereof and a display device. The display device includes a pixel electrode (8), including a first portion (b) in a non-display region and a second portion (a) in a display region; a first electrode (6) formed on the first portion (b) of the pixel electrode (8); a passivation layer (9) formed on the pixel electrode (8) and the first electrode (6), the passivation layer (9) includes a via hole (11) located over the first electrode (6); an active layer (4) and a second electrode (7) that are formed on the passivation layer (9), the active layer (4) being connected to the first electrode (6) through the via hole (11) of the passivation layer (9). With the array substrate and the manufacturing method thereof, the manufacturing cost is reduced, materials of the electrodes are less subjected to corrosion, and quality of the array substrate is enhanced.

Abstract: There is provided a photodetector, comprising a semiconductor heterostructure having in sequence: a first collection layer having substantially uniform doping of a first doping type; a radiation-absorbing layer having substantially uniform doping of the first doping type and having a band gap less than or equal to that of the first collection layer; and a barrier layer having a band gap greater than that of the radiation-absorbing layer, the top of the valence band of the barrier layer being substantially equal in energy to that of the radiation-absorbing layer where the first doping type is n-type or the bottom of the conduction band of the barrier layer being substantially equal in energy to that of the radiation-absorbing layer where the first doping type is p-type; wherein a first portion of the barrier layer is of the first doping type and a second portion of the barrier layer is of a second doping type, the first portion of the barrier layer being adjacent to the radiation-absorbing layer, forming a het

Abstract: Provided is a solid-state image pickup apparatus, including: a pixel region, in which a plurality of pixels each including an amplifier transistor are arranged two-dimensionally in rows and columns, and which includes an n-row signal mixing region in which outputs of n amplifier transistors are mixed, where n is a natural number of 1 or more, and an m-row signal mixing region in which outputs of m amplifier transistors are mixed, where m>n; a column signal line to which a voltage from the amplifier transistor is output; and a clipping circuit, which is configured to clip a voltage in the column signal line, and is arranged at a position that is closer to the n-row signal mixing region than to the m-row signal mixing region.

Abstract: Ambient light sensing and proximity sensing is accomplished using pairs of stacked photodiodes. Each pair includes a shallow diode with a shallow junction depth that is more sensitive to light having a shorter wavelength and a deeper diode with a deeper junction depth more sensitive to light with longer wavelengths. Photodiodes receiving light passed through cyan, yellow, and magenta filters and light passed without a color filter are used to generate red, green, and blue information through a subtractive approach. The shallow diodes are used to generate lux values for ambient light and the deeper diodes are used for proximity sensing. One or more of the deep diodes may be used in correction to lux determinations of ambient light.

Abstract: A photoelectric conversion device has a pixel area including an effective pixel row and a reference pixel row, the reference pixel row containing a plurality of reference pixel pairs, each pair composed of a first reference pixel and a second reference pixel arranged adjacent to each other. The first and second reference pixels output reference signals having different signal levels and independent of the quantity of incident light.

Abstract: Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate. The semiconductor substrate has a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a reflective layer positioned on an inner wall of the trench, wherein the reflective layer has a light reflectivity ranging from about 70% to about 100%.