Abstract: The present invention provides a solid-state image sensor in which degradation in image quality can be reduced. The solid-state image sensor includes an optical isolation layer between a pupil dividing unit and a plurality of photoelectric conversion units. The optical isolation layer includes a plurality of high-refractive-index areas and a low-refractive-index area having a lower refractive index than that of the high-refractive-index areas. The high-refractive-index areas are disposed above the photoelectric conversion units, and the low-refractive-index area is disposed between the high-refractive-index areas. The refractive index changes stepwise at the boundaries between the high-refractive-index areas and the low-refractive-index area. The refractive index difference of the stepwise changing portion is 0.15 or more. A value obtained by multiplying the physical thickness of the optical isolation layer by the refractive index of the high-refractive-index areas is 2.

Abstract: An image sensor includes a first semiconductor chip, a second semiconductor chip and connecting portions configured to connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip includes a photoelectric conversion portion, a capacitor, a reset transistor, and an amplification transistor. The second semiconductor chip includes a transfer transistor, and a row selecting transistor. The connecting portions connect the photoelectric conversion portion to the transfer transistor, the transfer transistor to the capacitor, and the amplification transistor to the row selecting transistor respectively.

Abstract: A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.

Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.

Abstract: A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line.

Abstract: A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.

Abstract: A method of manufacturing a junction field effect transistor having a channel region disposed in a semiconductor substrate, deeper than one of a source region and a drain region, the method includes a first step of forming a first mask having a first opening portion over the semiconductor substrate in which a first semiconductor region of a first conductivity type is disposed, a second step of forming a second semiconductor region of a second conductivity type defined as the channel region, in the first semiconductor region by implantation of ions of second conductivity type opposite to the first conductivity type using the first mask, and a third step of forming a third semiconductor region of the second conductivity type defined as the one of the source region and the drain region, by implantation of ions of the second conductivity type, using the first mask.

Abstract: A device for color imaging including an optical sensor having light sensitive pixels with a metal film disposed over the light sensitive pixels. The metal film has a group of nano-holes arranged over the pixels according to a periodic lattice formation and is configured to pass light of a preselected first range of wavelengths. The group of nano-holes arranged over an adjoining group of pixels is configured to pass light having ranges of wavelengths different from the first range of wavelengths.

Abstract: A light emitting device includes a substrate and a plurality of light emitting cells disposed on the substrate. Each light emitting cell includes a first semiconductor layer and a second semiconductor layer, an active layer between the first and the second semiconductors, a conductive material on the second semiconductor layer, an inclined surface, a first insulation layer overlaps each light emitting cell, an electrically conductive material overlaps the first insulation layer to couple two of the plurality of light emitting cells, and a second insulation layer overlaps the electrically conductive material. A light-transmitting material is used in both the first insulation layer and the second insulation layer. The inclined surface is continuous and has a slope of approximately 20° to approximately 80° from a horizontal plane based on the substrate.

Abstract: A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies.

Abstract: Embodiments are related generally to display fabrication, and more particularly to a fluidic assembly process for the placement of light emitting diodes on a transparent display substrate.

Abstract: The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.

Abstract: A ZnO based display pixel structure that includes system-on-glass (SOG) substrates with embedded non-volatile resistive random access memory iNV-RRAM) is provided. Such pixels feature high frame rates and low power consumption. The entire SOG is based on ZnO devices. Different devices including TFT, TCO, RRAM, inverters, and shift registers are obtained through doping of different elements into selected ZnO active regions. This reduces the cost to package control circuitry onto a backplane of a display system, resulting in a low cost, light weight and uUra-thin display.

Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.

Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Abstract: Providing for three-dimensional memory cells having enhanced electric field characteristics is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

Abstract: A method of manufacturing a fine metal mask is provided. The method of manufacturing a fine metal mask includes: forming a first recessed portion in a first surface of a base member; forming an edge portion of the first recessed portion in a uniform depth; forming a second recessed portion in a second surface of the base member, the second surface being opposite to the first surface; and communicating the first recessed portion and the second recessed portion of the base member. A fine metal mask produced by the inventive method is also described and may be used to fabricate OLEDs having better resolution and an increased aperture ratio in comparison with OLEDs prepared using the fine metal masks of the conventional art.

Abstract: Various embodiments relate to an optoelectronic component including: an electronic circuit structure including an electronic circuit and a metallization structure disposed over the electronic circuit, the metallization structure including one or more contact pads electrically connected to the electronic circuit; and an optoelectronic structure disposed over the metallization structure, the optoelectronic structure including at least one electrode structure being in direct contact with the one or more contact pads, wherein the electrode structure includes an electroless plated electrically conductive material.

Abstract: A display device includes a substrate and subpixel groups disposed on the substrate. Each subpixel group includes four first subpixels for emitting four first color lights, four second subpixels for emitting four second color lights, and eight third subpixels for emitting eight third color lights. The first subpixels, the second subpixels, and the third subpixels are respectively arranged adjacent to each other along a first axis and a second axis intersecting the first axis, in which each of the first subpixels is located adjacent to another one of the first subpixels along the first axis or the second axis, each of the second subpixels is located adjacent to another one of the second subpixels along the first axis or the second axis, and each of the third subpixels is located adjacent to another one of the third subpixels along at least one of the first axis and the second axis.

Abstract: The invention discloses an active matrix organic light emitting diode panel and a method for manufacturing the same. The active matrix organic light emitting diode panel includes a substrate, an organic film formed on the substrate, and a plurality of red, green and blue organic light emitting diodes formed on the organic film. A recess or protrusion is formed in the organic film in a region corresponding to the blue organic light emitting diode. The blue organic light emitting diode is formed on the recess or protrusion, and the surface area of the recess or protrusion is larger than the area of the surface where the red or green organic light emitting diodes contacts the organic film.

Abstract: The present invention provides an OLED panel. The OLED panel includes a substrate and a plurality of walls formed on the substrate. The substrate and the walls define a plurality of containing areas. Each of the containing areas is corresponding to each of a plurality of sub-pixels. The sub-pixels are separated from each other by the walls. Each of the sub-pixels includes one of emitting materials formed in one of the containing areas. At least one of the containing areas corresponding to the sub-pixel includes a first partition. The height of the first partition is lower than the walls.

Abstract: A pixel arrangement structure for an organic light-emitting diode display includes at least one first sub-pixel line having alternately disposed first and second sub-pixel units in a first direction. Each first sub-pixel unit includes four diagonally disposed red sub-pixels. Each second sub-pixel unit includes four diagonally disposed green sub-pixels. At least two second sub-pixel lines are respectively located on two sides of the first sub-pixel line. Each second sub-pixel line includes third sub-pixel units arranged in the first direction. Each third sub-pixel unit is located between one of the first sub-pixel units and one of the second sub-pixel units in a second direction perpendicular to the first direction and includes two blue sub-pixels arranged in the second direction. A red sub-pixel, a green sub-pixel, and a blue sub-pixel, which are adjacent to each other and which are respectively of the first sub-pixel line and the second sub-pixel line, form a pixel.

Abstract: An organic light emitting display device includes a plurality of first sub-pixels arranged adjacent to each other along a first direction, each of the first sub-pixels includes a first emission region configured to emit light of a first color and a first transmission region configured to transmit external light, the first emission regions of at least two of the first sub-pixels are adjacent to each other; and a plurality of second sub-pixels arranged adjacent to each other along the first direction and adjacent to corresponding ones of the plurality of first sub-pixels along a second direction crossing the first direction, each of the plurality of second sub-pixels includes a second emission region configured to emit light of a second color and a second transmission region configured to transmit external light, the second emission regions of at least two of the sub-pixels are adjacent to each other.

Abstract: A pixel structure includes a plurality of pixel cells each including two sub-pixel cells. Each of the two sub-pixel cell includes: a first sub-pixel; and at least two second sub-pixels parallelly adjacent to each other. Herein, organic material parts of the at least two second sub-pixels are interconnected and the first sub-pixel is arranged staggered with any of the at least two second sub-pixels in both a first direction and a second direction, and the first direction is perpendicular to the second direction.

Abstract: An organic light emitting display apparatus wherein a shift of white light caused by a viewing angle is reduced by adjusting an offset distance between one end of a corresponding emission region and one end of the black matrix adjacent to the one end of the corresponding emission region, thereby preventing a white color shift phenomenon at various viewing angles. Accordingly, a certain image is produced regardless of a use environment of a user's viewing angle.

Abstract: A display unit includes a plurality of light emitting devices, each of the light emitting devices including a function layer including at least an organic layer is sandwiched between a first electrode and a second electrode, and which have a resonator structure for resonating light by using a space between the first electrode and the second electrode as a resonant section and extracting the light through the second electrode are arranged on a substrate, wherein in the respective light emitting devices, the organic layer is made of an identical layer, and a distance of the resonant section between the first electrode and the second electrode is set to a plurality of different values.

Abstract: Provided are an organic light emitting display device, the display device including: a substrate defined into a display area and a non-display area; sub-pixels formed on the display area of the substrate; and dummy sub-pixels formed on the non-display area of the substrate, the dummy sub-pixels have a different shape for each position of the non-display area.

Abstract: It is provided a touch display driving circuit, a method thereof and a display apparatus, wherein the touch display driving circuit includes a driving transistor, a touch sensing unit, and a compensation driving unit; wherein the driving transistor drives a pixel display element to perform the displaying of the pixel; the touch sensing unit receives a touch control signal, and to control the compensation driving unit to drive the driving transistor according to the received touch control signal; the compensation driving unit drives the driving transistor, and to adjust the gate-source voltage of the driving transistor as driving the driving transistor, so that a compensation amount of the gate-source voltage and a threshold voltage are counteracted. The technical solutions of the embodiments of the disclosure are capable of achieving an integration of the touch control with the driven displaying, which reduces a thickness of the display screen.

Abstract: An organic light-emitting display apparatus includes: a display substrate; at least one thin film transistor (TFT) on the display substrate; an organic light-emitting diode (OLED) electrically connected to the TFT, the OLED including: a first electrode on each sub-pixel on the display substrate; an intermediate layer on the first electrode; and a second electrode on the intermediate layer; an encapsulation substrate covering the OLED; a filler filling a space between the display substrate and the encapsulation substrate, the filler including scatterers having optical anisotropy; and a color filter between the encapsulation substrate and the filler, the color filter including a color filter electrode at a surface of the color filter.

Abstract: An organic light emitting display device includes a spacer on a pixel defining layer. The pixel defining layer includes openings corresponding to pixels. The device further includes first pixels to third pixels emitting light having different colors. The first pixels and the second pixels are alternately disposed in a row direction, and the third pixels are continuously disposed in a row direction. The row in which the first pixels and the second pixels are alternately disposed and the row in which the third pixels are continuously disposed are adjacent to each other in a column direction The spacer is disposed between two of the third pixels.

Abstract: An organic light-emitting display panel and a method of fabricating the same, the panel including a base substrate; a first electrode layer including a plurality of first electrodes arranged on the base substrate; a pixel-defining layer including partition walls that extend from the base substrate and that define a plurality of pixels; an organic light-emitting layer including a plurality of organic light-emitting patterns in the pixels, respectively; and a second electrode layer on the organic light-emitting layer, wherein the organic light-emitting layer includes a plurality of primer patterns, the plurality of primer patterns being respectively formed in the pixels, being separate from one another, and respectively overlapping the first electrodes, at least one of the primer patterns has an area different area from an area of the other primer patterns, and the primer patterns have an affinity for liquid that is higher than an affinity for liquid of the pixel-defining layer.

Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes, an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Abstract: The present disclosure provides an array substrate, its manufacturing method and a display device. The array substrate includes a thin film transistor. A source electrode and a drain electrode are located above a pattern of an active layer, and the source electrode and the drain electrode are in electrical contact with the pattern of the active layer through a first via-hole penetrating an insulating structure. Before the formation of the source electrode and the drain electrode, the pattern of the active layer is subjected to ion injection through the first via-hole, so as to form an ion injection region.

Abstract: Disclosed herein is an OLED (Organic Light Emitting Display) device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel. A second pixel is adjacent to the first pixel in the direction in which data lines are extended. A switching thin-film transistor configured to be an LTPS (Low Temperature Poly-Silicon) thin-film transistor is disposed in the second pixel. The switching thin-film transistor of the first pixel and the switching thin-film transistor of the second pixel are connected to the same gate line. A pixel and another pixel adjacent to the pixel connected to a gate line in common, so that it is possible to provide an OLED device with high aperture ratio and high resolution.

Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.

Abstract: An organic display device includes a pixel driving circuit having a TFT connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the TFT. The first electrode is connected to the TFT through a contact hole in the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner wall having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over pixels.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and an active pattern formed over the substrate and including first to fourth regions. A gate insulation layer is formed over the active pattern and the substrate, and a first gate electrode is formed over the gate insulation layer and partially overlapping the active pattern. The first gate electrode, the first region and the second region define a first transistor. A second gate electrode is formed on the same layer as the first gate electrode. The second gate electrode, the third region and the fourth region define a second transistor, and the second gate electrode, the second region and the fourth region define a third transistor. A first insulating interlayer is formed over the first gate electrode, the second gate electrode, and the gate insulation layer.

Abstract: A display panel is disclosed, which comprises: a first substrate; a first metal line disposed on the first substrate and having a first surface and a first side connecting to the first surface, wherein the first side has a concave shape; and a sealant unit covering the first surface and the first side.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: Provided is a capacitor structure including a substrate, a dielectric layer, a first conductive layer, and a cup-shaped capacitor. The dielectric layer is located on the substrate. The first conductive layer is located in the dielectric layer. The cup-shaped capacitor penetrates through the first conductive layer and is located in the dielectric layer. The cup-shaped capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Two sidewalls of the bottom electrode are electrically connected to the first conductive layer. The capacitor dielectric layer covers a surface of the bottom electrode. The top electrode covers a surface of the capacitor dielectric layer. The capacitor dielectric layer is located between the top electrode and the bottom electrode. A top surface of the bottom electrode is lower than a top surface of the top electrode. Also the invention provides a method of manufacturing the capacitor structure.

Abstract: A doped mold film is formed with a dopant concentration gradient in the doped mold film that continuously varies in a thickness direction and a portion of the doped mold film is etched in the thickness direction to form a hole so that an electrode can be formed along an inner wall of the hole. The electrode thus formed includes a first outer wall surface, a second outer wall surface, and a third outer wall surface wherein the first outer wall surface is in contact with a sidewall of an insulating pattern formed on a substrate within a through hole formed in the insulating pattern; the second outer wall surface is in contact with a top surface of the insulating pattern and extends in a lateral direction; the third outer wall surface is spaced apart from the first outer wall surface with the second outer wall surface therebetween; and the third outer wall surface extends on the insulating pattern in a direction away from the substrate.

Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1<Pn (n?2).

Abstract: A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer.

Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device comprises: a semiconductor substrate with an active area defined by a plurality of isolation features; a gate stack extending across the active area onto portions of the isolation features, wherein the gate stack comprising a gate dielectric layer on the active area and the portions of the isolation features, and a gate electrode on the gate dielectric layer; and a protective seal comprising a vertical portion lining sidewalls of the gate stack and a horizontal portion extending onto a top surface of the isolation features, wherein the horizontal portion surrounding portions of the gate stack outside the active area in a top view.

Abstract: A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer.

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow.