Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

Abstract: A TSV interposer having a reinforced edge and methods for fabricating an IC package utilizing the same are provided. In one embodiment, a chip package includes an interposer having a wiring layer and a die disposed on a surface of the interposer. The die is electrically connected to the wiring layer of the interposer. A die underfill material is disposed between the interposer and the die. The die underfill material at least partially covers a side of the die that extends away from the surface of the interposer. Stiffening material is disposed in contact with the interposer and the die underfill material.

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

Abstract: A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

Abstract: An integrated circuit structure with seal ring structure is provided. The seal ring structure includes a low k dielectric layer, a first seal ring and a second seal ring. The first seal ring and the second seal ring are spaced from each other. Each of the first seal ring and the second seal ring comprises a metal layer. The metal layer is embedded in the low k dielectric layer, and the metal layer includes a body pattern having a plurality of openings. The area ratio of the body pattern to the metal layer of the first seal ring and the second seal ring is greater than or equal to 50% and less than 100%.

Abstract: An integrated circuit has a set of circuit components. The set of circuit components enables the circuit to execute an action. The integrated circuit has a structural weakness. In response to undergoing a mechanical force, the structural weakness will cause the integrated circuit to undergo a structural failure. A human is able to provide the mechanical force without the use of tools. The structural failure will alter one or more circuit components of the set of circuit components. The alteration will result in the set of circuit components no longer enabling the integrated circuit to execute the action.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.

Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.

Abstract: A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip outputs a first signal by a first bus width and includes a first via which transfers the first signal. The second semiconductor chip receives, by the first bus width, the first signal transferred through the first via.

Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.

Abstract: Plating pre-processing is carried out before carrying out a plating process on the surface of a conducting section provided on a semiconductor wafer. A first metal film is formed on the surface of the conducting section by NiP alloy plating process. A second metal film is formed on the surface of the first metal film by immersion Ag plating process. The semiconductor wafer is diced and cut into semiconductor chips. A conductive composition containing Ag particles is applied to the surface of the second metal film which is on the front surface of the semiconductor chip. A bonding layer containing Ag particles is formed by sintering the conductive composition through heating. A metal plate is then bonded to the surface of the second metal film via the bonding layer containing Ag particles. The electronic component has high bonding strength, excellent thermal resistance and heat radiation properties.

Abstract: A power semiconductor module and an arrangement including it. The module includes a housing, a switching device having a substrate connected to the housing, a connecting device, load connection devices and a pressure device movable relative to the housing. The substrate has a first central passage and conductor tracks which are electrically insulated from one another. A power semiconductor component sits on a conductor track. The connecting device has two main surfaces and an electrically conductive film. The pressure device has a pressure body with a second passage, in alignment with the first passage and a first recess. A pressure element projects out of the recess, and presses onto a section of the second main surface. This section is within the surface of the component projects normal to the substrate. The first and second passages receive a fastener which force-fittingly fastens the module to the cooling device.

Abstract: The semiconductor device of the present invention includes an insulating layer, a copper wiring for wire connection formed on the insulating layer, a shock absorbing layer formed on an upper surface of the copper wiring, the shock absorbing layer being made of a metallic material with a hardness higher than copper, a bonding layer formed on the shock absorbing layer, the bonding layer having a connection surface for a wire, and a side protecting layer covering a side surface of the copper wiring, wherein the side protecting layer has a thickness thinner than a distance from the upper surface of the copper wiring to the connection surface of the bonding layer.

Abstract: A semiconductor-mounted product includes a semiconductor package, a circuit board, a solder bonding part, and a resin reinforcing part. Wiring is formed on the surface of the circuit board, and the semiconductor package is mounted on the circuit board. The solder bonding part electrically connects the semiconductor package with the wiring. The resin reinforcing part is formed on a side surface of the solder bonding part such that the solder bonding part is partially exposed. The bonding part has a first solder region formed closer to the semiconductor package than the circuit board, and a second solder region formed closer to the circuit board than the semiconductor package.

Abstract: An embodiment is a structure comprising a package, a substrate, and external electrical connectors mechanically and electrically coupling the package to the substrate. The package contains a die. The external electrical connectors are between the package and the substrate. An underfill material is around a periphery region of the package and between the periphery region and the substrate. A gap is between a central region of the package and the substrate, and does not contain the underfill material. The underfill material may seal the gap. The gap may be an air gap. In some embodiments, the underfill material may fill greater than or equal to 10 percent and no more than 70 percent of a volume between the package and the substrate.

Abstract: A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.

Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.

Abstract: A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes: (a) disposing, on a substrate (insulating substrate), a bonding material having a sheet shape and having sinterability; (b) disposing a semiconductor element on the bonding material after the (a); and (c) sintering the bonding material while applying pressure to the bonding material between the substrate and the semiconductor element. The bonding material includes particles of Ag or Cu, and the particles are coated with an organic film.

Abstract: A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device includes: patterning a metal sheet to include a plurality of openings; bonding at least one two terminal device to the metal sheet, wherein a first opening corresponds to a distance between a first contact and a second contact of the at least one two terminal device; and cutting the metal sheet around each of the least one two terminal device, wherein the metal sheet forms a first electrode to the first contact and a second electrode to the second contact.

Abstract: Devices and methods for processing singulated radio-frequency (RF) units. In some embodiments, a device for processing singulated RF packages can include a plate having a plurality of apertures. Each aperture can be dimensioned to receive and position a singulated RF package to thereby facilitate processing of the singulated RF packages positioned in their respective apertures. In some embodiments, such a device can be utilized to batch process high volume of RF packages as if the RF packages are still in a panel format.

Abstract: Methods for a semiconductor device package formed in a chip-on-wafer last process using thin film adhesives are disclosed and may include bonding a first carrier to a first surface of an interposer in wafer form, forming conductive bumps on a second surface of the interposer, bonding a second carrier to the conductive bumps utilizing a film adhesive, removing the first carrier from the interposer, bonding a semiconductor die to the first surface of the interposer, and encapsulating the die and the first surface of the interposer in an encapsulant material. The second carrier and the film adhesive may be removed from the conductive bumps utilizing a slide-off process. The interposer and encapsulant may be diced into a plurality of interposer and die structures. One of the die and interposer structures may be bonded to a substrate. The die may be bonded to the interposer utilizing a mass reflow process.

Abstract: A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad.

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.

Abstract: A semiconductor module includes a first semiconductor switch, a second semiconductor switch, a circuit carrier arrangement and a non-ceramic dielectric isolation layer. The first semiconductor switch and the second semiconductor switch have a first load terminal and a second load termina. The current path of the first semiconductor switch and the current path of the second semiconductor switch are electrically connected in series between a first circuit node and a second circuit node. A circuit carrier arrangement includes a dielectric first isolation carrier section, a dielectric second isolation carrier section, a first upper metallization layer, a second upper metallization layer and a third upper metallization layer, a first lower metallization layer, and a second lower metallization layer.

Abstract: A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: Multiple configuration light emitting diode (LED) devices and methods are disclosed wherein LEDs within the device can be selectively configured for use in higher voltage, or variable voltage, applications. Variable arrangements of LEDs can be configured. Arrangements can include one or more LEDs connected in series, parallel, and/or a combination thereof. A surface over which one or more LEDs may be mounted can comprise one or more electrically and/or thermally isolated portions.

Abstract: An illumination device includes a light-emitting device and a diffusion member. The light-emitting device has a plurality of light-emitting elements that emit light having a peak wavelength in a wavelength region of 380 to 420 nm, a first phosphor that emits visible light having a peak wavelength in a wavelength region of 560 to 600 nm, a second phosphor that is excited by ultraviolet ray or short-wavelength visible light and emits visible light in complementary color relationship with the visible light emitted by the first phosphor, and a light-transmitting member that covers the plurality of light-emitting elements and contains the first phosphor and the second phosphor dispersed therein. The diffusion member diffuses at least a part of the light emitting from the light-emitting device.

Abstract: A display device including a wiring substrate having a wiring electrode; a plurality of semiconductor light emitting devices which form pixels; and a conductive adhesive layer configured to electrically connect the wiring electrode with the plurality of semiconductor light emitting devices. Further, the conductive adhesive layer includes a body provided with a resin having an adhesive property; and a metallic aggregation part disposed in the body, and formed as metallic atoms precipitated from a metal-organic compound and aggregated with each other.

Abstract: Disclosed is a combined light emitting diode lamp that utilizes a multicolored light emitting diode that is capable of creating a full spectrum of colors. Attached to the multicolored lamp is a white light emitting diode lamp that provides a bright white signal that is consistent from one combined LED lamp to another.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: A microelectronic semiconductor package includes first and second microelectronic elements and a substrate positioned between them. Each of the microelectronic elements has active and passive surfaces, first edges bounding the surfaces in a first lateral direction and second edges bounding the surfaces in a second lateral direction transverse to the first lateral direction. The first microelectronic overlies the second microelectronic element and the active surface of the first microelectronic element faces toward the passive surface of the second microelectronic element. Each of the first edges of the first microelectronic element are disposed beyond each of the adjacent first edges of the second microelectronic element. Each of the second edges of the second microelectronic element are disposed beyond each of adjacent second edges of the first microelectronic element.

Abstract: Memory devices with controllers under stacks of memory packages and associated systems and methods are disclosed herein. In one embodiment, a memory device is configured to couple to a host and can include a substrate, a stack of memory packages, and a controller positioned between the stack and the substrate. The controller can manage data stored by the memory packages based on commands from the host.

Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one AA-short-related failure mode.

Abstract: An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The device includes a first bipolar transistor having a collector and an emitter located in a first n-type region. The emitter of the first transistor is connected to the first node. The device also includes a second bipolar transistor having a collector and an emitter located in a second n-type region. The emitter of the second transistor is connected to the collector of the first bipolar transistor. The device further includes a pn junction diode including a p-type region located in a third n-type region. The p-type region of the diode is connected to the collector of the second bipolar transistor and the third n-type region is connected to the second node.

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Abstract: In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.

Abstract: A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.