Abstract: A memory subsystem enables satisfying refresh needs for a memory device with hidden refreshes performed by the memory device in response to Activate commands, and external refreshes to make up a difference between the number of hidden refreshes and a minimum number of total refreshes needed during a refresh window. With a hidden refresh the memory device executes the Activate command in one memory portion as indicated by the identified memory location of the command, and executes a refresh in a different portion, such as a different sub-bank. By combining external refreshes with hidden refreshes, the memory subsystem can enable hidden refreshes without the hidden refreshes causing a back-off or retry condition from the memory device to the memory controller.

Abstract: Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on value of the stored bit, and such that: the gate of the MOS transistor is connected to the memory point, and the gate of the TFET transistor is able to receive a read command signal; a first electrode of the MOS transistor is connected to the power supply terminal; a second electrode of the MOS transistor is connected to a first electrode of the TFET transistor; a second electrode of the TFET transistor is connected to the read bit line.

Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.

Abstract: An SRAM cell includes first and second inverters which are cross-coupled to one another to establish first and second data storage nodes, which are complementary. A first access transistor includes a first source/drain region coupled to the first data storage node, a first drain/source region coupled to a first bitline, and a first gate region coupled to a wordline. A second access transistor includes a second source/drain region coupled to the second complementary data storage node, a second drain/source region coupled to a second bitline, and a second gate region coupled to the wordline. A first dummy transistor has a first dummy source/drain region coupled to the first source/drain region of the first access transistor. A second dummy transistor has a second dummy source/drain region coupled to the second source/drain region of the second access transistor.

Abstract: A memory write tracking device is applied to a data write operation to at least a memory cell row. The memory write tracking device includes a dummy cell row, a variation sensor, a judging device and a word-line pulse generator. The dummy cell row includes a plurality of dummy memory cells for simulating the data write operation to the memory cell row. The variation sensor senses a set of circuit parameters for write ability of the memory cell row. The judging device determines a threshold number according to a change of the set of circuit parameters and sends an enabling signal when a threshold number of the dummy memory cells have been successfully written with the data. The word-line pulse generator determines a write cycle of the data write operation in response to the enabling signal. An associated memory write tracking method is also provided.

Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.

Abstract: Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.

Abstract: One example provides a device including a first transistor having a source-drain path electrically coupled between a first node and a second node. The device includes an operational amplifier having an output electrically coupled to a gate of the first transistor. The operational amplifier controls the first transistor to maintain a predetermined voltage on the first node. A first current source adds a current at the first node and a second current source subtracts the current at the second node.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.

Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell. The sense amplifier connects to the bit line. The register holds write data, and a write voltage. The controller outputs a busy signal. The controller causes the register to hold the write data and the write voltage upon receiving the first command, and resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command.

Abstract: A memory device, and method of operation, includes an array of non-volatile memory cells and a controller. The controller is configured to perform an operation (e.g. erase, program, etc.) on a first plurality of the non-volatile memory cells using operational voltages with a first energy margin, and perform the same operation on a second plurality of the non-volatile memory cells using operational voltages with a second energy margin that is greater than the first energy margin. The operations of varying energy margins are based on the required storage longevity of the data being stored (lower energy margins for data being stored for shorter periods of time) to save energy and wear.

Abstract: A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Abstract: A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

Abstract: A method and apparatus for testing a device memory. The method begins with a generated data and address width from an automatic testing system. The generated data width and the generated address width is compared with the required data width and address width of a device under test and used to set a user bit. If the generated data width and address width match the required data and address width, the user bit is set to zero. If the generated data width and address width do not match the required data width and address width, the user bit is set to 1. The user bit provides address control and data control during testing. The apparatus includes a wireless test access protocol that is electrically connected to a glue logic module. A wireless test access port is electrically connected to the glue logic module as is the device under test.

Abstract: Disclosed is an integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.

Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.

Abstract: Provided is a device for transferring spent fuel between spent fuel storage pools. The device includes a transfer container extending in a direction, disposed in a vertical direction, and containing spent fuel therein; a guide frame configured to guide the transfer container while maintaining a vertical orientation of the transfer container; and a transfer unit configured to transfer the transfer container along the guide frame.

Abstract: In one embodiment, a system and method for dry storage comprises removing spent fuel rods from their fuel rod assemblies and placing the freed fuel rods in a storage cell of a dry storage canister with a high packing density and without a neutron absorber material present.

Abstract: A dry storage systems for radioactive nuclear waste materials in one embodiment includes a canister having a tubular shell defining an internal cavity for storing nuclear waste material, a lid sealably welded to one end the shell, and an end closure attached to a second end of the shell. The end closure includes a base plate having an upturned peripheral annular closure flange. In one embodiment, a circumferentially-extending butt joint is formed between the closure flange and the shell second end which is hermetically seals by a full through-wall thickness butt weld. Various embodiments may further include secondary pressure retention barriers enclosing the canister or select portions thereof most susceptible to failure under certain conditions.

Abstract: A method to produce a high-purity Zr-89 on a solid target through physical irradiation and measurement by selecting a target Barn value of the cross-sectional area of nuclear reaction, drawing a horizontal line to intersect at two points on the function diagram curve and drawing a vertical line downward from each of the two points intersecting at X-axis to obtain incident energy values at the two intersecting points on the X-axis, and followed by plotting an attenuation function diagram curve of penetration depth versus incident energy of Y-89(p,n)Zr-89, selecting an attenuation function diagram curve and a minimum attenuation position of the selected attenuation function diagram curve in correspondence to the incident energy in the interval of incident energy absorption range to obtain an optimal plating thickness value on the solid target.

Abstract: A support structure having multiple highly aligned curved x-ray optics, the support structure having multiple internal partially or fully concentric surfaces upon which said optics are mounted, thereby aligning said optics along a central optical axis thereof and therefore to a source, sample, and/or detector in combination with which the support structure is useable. The surfaces may be nested around the central optical axis; and the support structure may divided longitudinally into sections around the central optical axis by walls. At least one of the x-ray optics comprises a curved diffracting optic, for receiving a diverging x-ray beam and focusing the beam to a focal area, in one embodiment a focusing monochromating optic. In an improved embodiment, an optic comprises a single layer, plastically deformed, LiF optic.

Abstract: An electrical conductor includes: a first conductive layer including a plurality of ruthenium oxide nanosheets, wherein at least one ruthenium oxide nanosheet of the plurality of ruthenium oxide nanosheets includes a halogen, a chalcogen, a Group 15 element, or a combination thereof on a surface of the ruthenium oxide nanosheet.

Abstract: A system having preclinical emergency care modules which produce a complex condition-dependent control system that is as integral as possible in combination with a human emergency worker. At the system level, an intelligent decision-making system is provided which leads to measures that are optimized for the situation with and without the emergency worker. The modules exhibit a different behavior depending on the situation and interaction. In the process, the emergency worker can be utilized as an additional sensor/actuator module. Based on all obtained sensor data, which is weighted differently, decision-making support is proposed to the emergency worker, or the system. makes decisions automatically. The protected communication of the modules is of particular importance for this purpose.

Abstract: A reflective conductive film includes (i) a reflective polymeric substrate having a polymeric base layer and a polymeric binding layer, wherein the polymeric material of the base layer has a softening temperature TS-B, and the polymeric material of the binding layer has a softening temperature TS-HS; and (ii) a conductive layer that includes a plurality of nanowires, wherein the nanowires are bound by the polymeric matrix of the binding layer such that the nanowires are dispersed at least partially in the polymeric matrix of the binding layer, wherein the polymeric substrate is a biaxially oriented substrate, and wherein the polymeric binding layer is a copolyester.

Abstract: In a splice connection member, a core wire holder is integrally formed on an interior of each of a plurality of depressions into which coated wires can be guided. A plurality of pressure blades are provided opposite each other on a wire introduction opening side of the depressions, the pair of pressure blades separated by a distance smaller than an inlet diameter of the wire introduction opening. Each of the pressure blades includes a plurality of blade tips separated by a distance in an axis direction of the coated wires smaller than a thickness of the coating, and the core wire holder includes a plurality of pressure portions. A communicating groove is formed in each of the depressions so as to be open on two ends, passing between the plurality of pairs of blade tips, the communicating groove extending in a circumference direction of each of the coated wires.

Abstract: A first electric wire is fastened, in a first frame, by a plurality of first wire hooking ribs provided on upper side edges of an upper thin plate, and by a plurality of second wire hooking ribs provided at lower thin plates, thereby being routed three-dimensionally. A second electric wire is fastened, in a second frame, by a plurality of third wire hooking ribs provided staggered along the upper side edges of the second frame, thereby being routed in a serpentine shape. With the electric wires routed and the second frame accommodated at a predetermined location in a housing space of the first frame, the first electric wire passes below the second electric wire at openings in the structure and passes above the second electric wire at connecting portions in the structure while passing on the connecting portions.

Abstract: A wire harness includes a plurality of coated electric wires; a connector terminal including a connection portion, a first barrel portion, and a second barrel portion; a connector configured to lock and store the connection portion; a rubber seal including a small-diameter tubular portion, a middle tubular portion having a spiral contour, and a large-diameter tubular portion, where the small-diameter tubular portion is secured by the second barrel portion along with an end portion of the insulation coating material. The middle tubular portion and the large-diameter tubular portion are force-fitted into a terminal insertion hole, and a rear holder is secured to the connector with the rubber seal pressed toward the terminal insertion hole, compressing the middle tubular portion axially. A waterproofing agent is applied to an outer surface of the middle tubular portion and is cured filling gaps between the middle tubular portion and the terminal insertion hole.

Abstract: Provided are reinforcing tape for a flat cable, which can maintain sufficient adhesive force for a long time in a high-temperature, high-humidity environment, and a flat cable that uses this reinforcing tape for a flat cable. The present invention provides a reinforcing tape for a flat cable, the reinforcing tape including a base layer containing a resin as a main component, and an adhesive layer stacked on one side of the base layer, in which the adhesive layer contains a thermoplastic resin and a polycarbodiimide compound, and the polycarbodiimide compound contains an isocyanate group. The content of the polycarbodiimide compound relative to 100 parts by mass of the thermoplastic resin is preferably 0.5 parts by mass or more and 10 parts by mass or less. The polycarbodiimide compound preferably further contains an alicyclic structure.

Abstract: A power cable bundle is provided herein. The power cable bundle includes a spool having an axle, and a power cable wound there around. The power cable comprises a plurality of conductor wires, and a non-conductive, high-strength, synthetic material around the plurality of conductor wires substantially along its length. The power cable has a tensile strength of at least 2,000 MPa, and a weight that is less than 0.1 lb./ft. in air. Preferably, the power cable is at least 2,000 feet in length. A method of pumping fluids from a wellbore using an electrical submersible pump that receives electrical power through the power cable is also provided herein.

Abstract: A cable (100) includes a plurality of wires (10) and a jacket (20) enclosing the wires. The wires includes a plurality of differential signal wires (11) for transmitting high speed signal, a detection signal wire (12), at least one auxiliary signal wire (13), and a plurality of lower speed signal wires (14). All of the differential signal wires, the detection signal wire and the at least one auxiliary signal wire are arranged at an outer peripheral of and enclosing the lower signal wires. Each two adjacent differential signal wire pairs are separated by one of the detection signal wire and the at least one auxiliary signal wire.

Abstract: A wire cable assembly capable of transmitting signals at speeds of 5 Gigabits per second over a single pair or conductors. The cable has a characteristic impedance of 95 Ohms and can support transmission data according to either USB 3.0 or HDMI 1.3 performance specifications. The wire cable includes a pair of conductors, a shield surrounding the conductors, and a dielectric structure configured to maintain a first predetermined spacing between the conductors and a second predetermined spacing between said the conductors said shield. The shield includes an inner shield conductor enclosing the dielectric structure, a ground conductor external to the inner shield conductor, extending generally parallel to the pair of conductors, an outer shield conductor enclosing the inner shield conductor and the ground conductor.

Abstract: A USB Type-C cable includes: a number of first wires and second wires, the first wires including a power wire for transmitting a power signal and plural coaxial wires for transmitting high speed signal, the second wires including at least one detective wire for transmitting detective signal, at least one power return wire for grounding, at least one twisted pair of wires for transmitting USB 2.0 signal, and at least one subsidiary wire for transmitting subsidiary signal; a jacket made of insulative material and receiving the first wires and the second wires; and a metal shield layer coating around the twisted pair of wires; wherein the first wires are arranged along an inner wall of the jacket in a circle and forms a cavity without a metal shield layer to receive the second wires, and the detective wire and the subsidiary wire are separated by the power return wire.

Abstract: A cable fixator includes: a first member formed in a cylindrical shape with a through hole inside; a protrusion formed on one side of the first member and inserted in the through tube after the first screw thread provided; a first fastener formed in a ring shape and combined with the protrusion by the combining grooves; a second screw thread formed on the inner side of the first member; a second member formed in a cylindrical shape and inserted into the inside of the first member; a second fastener formed on one side of the second member; a third screw thread formed on the outside of the second member and combined with the second screw thread; a sealing member consisting of a soft material; a sealing groove formed on the outer surface of the sealing member and provided with grooves toward the inside of the sealing member.

Abstract: An Al2O3 carrier has a thin-film structure of platinum or a platinum alloy arranged thereon. The carrier and/or the thin-film structure are adapted to reduce mechanical stresses owing to different thermal expansion coefficients. The carrier and/or the thin-film structure include a surface of the carrier in the region of the thin-film structure is smoothed at least in sections to reduce the adhesion and/or a surface of the carrier has an intermediate layer on which the thin-film structure is arranged. The thermal expansion coefficient of the intermediate layer is from 8*10?6/K to 16*10?6/K, in particular from 8.5*10?6/K to 14*10?6/K, and/or the thin-film structure has at least one conductor path that is undular at least in sections, said conductor path extends laterally along the surface of the carrier.

Abstract: The invention relates to a surge protection device, comprising at least one surge arrester and one short-circuit switching device which is connected in parallel with the surge arrester, can be thermally tripped and is spring-pretensioned, wherein the abovementioned means form one physical unit. The thermal tripping means is arranged in the region where heating of the surge arrester is expected when it is overloaded, and operating or surge current does not flow through said thermal tripping means. The thermal tripping means is in the form of a stop part which releases an unlocking slide of the switching device in the event of thermal overload. The switching device has two opposite contact pieces, wherein at least one of the contacts is of moveable design and is under spring pretension in the closing direction of the switching device. The opening state of the switching device is ensured by the unlocking slide and is released by the thermal tripping means for closing the switching device.

Abstract: Provided is a compressed powder core that can suppress a decrease in the inductance even when a high magnetic field (of greater than or equal to 40 kA/m) is applied to the compressed powder core while suppressing an iron loss and a decrease in the strength of the compressed powder core. The compressed powder core 1A has soft magnetic particles 11A and aluminum nitride layers 12A formed on the surface layers of the respective soft magnetic particles 11A. The compressed powder core 1A has a ratio of the first differential relative permeability ??L to the second differential relative permeability ??H satisfying a relationship of ??L/??H?6, and has a magnetic flux density of greater than or equal to 1.4 T when a magnetic field of 60 kA/m is applied. The soft magnetic particles of the compressed powder core 1A contain Si in the range of 1.0 to 3.