Patents Issued in April 20, 2017
  • Publication number: 20170110378
    Abstract: This method for estimating the depth of latent scratches in SiC substrates includes an etching step, a measurement step, and an estimation step. In the etching step, a SiC substrate in which at least the surface is formed from single crystal SiC, and which has been subjected to machining, is subjected to heat treatment under Si atmosphere to etch the surface of the SiC substrate. In the measurement step, the surface roughness or the residual stress of the SiC substrate which has been subjected to the etching step is measured. In the estimation step, the depth of latent scratches or the presence or absence of latent scratches in the SiC substrate before the etching step are estimated on the basis of the results obtained in the measurement step.
    Type: Application
    Filed: October 3, 2015
    Publication date: April 20, 2017
    Applicant: Toyo Tanso Co., Ltd.
    Inventors: Satoshi Torimi, Norihito Yabuki, Satoru Nogami
  • Publication number: 20170110379
    Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.
    Type: Application
    Filed: March 28, 2016
    Publication date: April 20, 2017
    Inventors: Jia-Ming LIN, Wei-Ken LIN, Shiu-Ko JANGJIAN, Chun-Che LIN
  • Publication number: 20170110380
    Abstract: A monitoring method that can detect a sign of disconnection of a heat generation source is provided. Further, a highly reliable semiconductor device is provided. The monitoring method uses a first control device that samples outputs of a plurality of thermometers at a first frequency (100 Hz sampling in S10) and controls a plurality of heat generation sources based on temperature information obtained by sampling, and a second control device that forms information based on temperature information obtained by sampling at the first frequency (100 Hz sampling in S20) and pieces of heat-generation-source information obtained by sampling of outputs of the respective heat-generation sources at the first frequency (100 Hz sampling in S20). Based on the temperature information obtained by sampling at the first frequency (100 Hz sampling in S20) and the pieces of heat-generation-source information obtained by sampling at the first frequency (100 Hz sampling in S20), states of the heat generation sources are monitored.
    Type: Application
    Filed: August 31, 2016
    Publication date: April 20, 2017
    Inventors: Masahide NAKAKUKI, Mikio SHIMIZU, Ryoichi SHINOHARA, Toshihiro NAKAJIMA
  • Publication number: 20170110381
    Abstract: Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Michael Tan, Cheng P. Pour
  • Publication number: 20170110382
    Abstract: A semiconductor package, a semiconductor module, a method of fabricating a semiconductor package are disclosed. The semiconductor package may include a substrate, a semiconductor chip, a connection terminal, a mold layer, and a protection layer. The protection layer may be provided to cover the substrate, the connection terminal, and the mold layer. The protection layer may be removed from a lower portion of the connection terminal, and thus, the lower portion of the connection terminal may be exposed. The connection terminal may be coupled to a module substrate through the lower portion, and a result, the semiconductor module may be fabricated. The connection terminal, the substrate, and the mold layer may be prevented from being exposed to outer air or moisture, owing to the presence of the protection layer.
    Type: Application
    Filed: August 24, 2016
    Publication date: April 20, 2017
    Inventor: SOONBUM KIM
  • Publication number: 20170110383
    Abstract: A semiconductor device is disclosed including material for absorbing EMI and/or RFI. The device includes a substrate, one or more semiconductor die, and molding compound around the one or more semiconductor die. The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer on the substrate, or within a dielectric core of the substrate. The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Applicant: SanDisk Information Technology (Shanghai) Co. Ltd.
    Inventors: Dacheng Huang, Ye Bai, Kaiyou Qian, Chin-Tien Chiu
  • Publication number: 20170110384
    Abstract: In embodiments described herein, an integrated circuit (IC) package is provided. The IC package may include a substrate, an IC die, and a heat spreader. The IC die may have opposing first and second surfaces, where the first surface of the IC die is coupled to a surface of the substrate. The heat spreader may have a surface coupled to the second surface of the IC die by a thermal interface (TI) material. The surface of the heat spreader may have a micro-recess which may include a micro-channel or a micro-dent to direct a flow of TI material towards or away from a predetermined area of the second surface of the IC die based on temperatures of the substrate, the IC die, and/or the heat spreader.
    Type: Application
    Filed: October 30, 2015
    Publication date: April 20, 2017
    Applicant: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Publication number: 20170110385
    Abstract: A heat-conductive sheet includes a laminated sheet and first and insulating sheets bonded to first and second main surfaces of the laminated sheet. The laminated sheet includes graphite sheets and one or more adhesive layers disposed alternately on the graphite sheets to bonds the graphite sheets to each other. The first insulating sheet is bonded to the second insulating sheet outside an outer circumferential edge of the laminated sheet to seal the laminated sheet between the first and second insulating sheets. The laminated sheet includes an outer circumferential portion connected to the outer circumferential edge and an inner portion apart from the outer circumferential edge. The outer circumferential portion of the laminated sheet has a thickness smaller than a thickness of the inner portion. The heat-conductive sheet has high reliability of sealing the insulating sheet.
    Type: Application
    Filed: March 18, 2015
    Publication date: April 20, 2017
    Inventors: KEIJI KAWAJIRI, KAZUHIRO MIURA, MASAFUMI NAKAYAMA, HIROSHI EBINA, HIROFUMI YAMADA
  • Publication number: 20170110386
    Abstract: A heat dissipating component including a main body formed from a first material, and a heat dissipating sheet that is formed from a second material having higher thermal conductivity than the first material, that covers the main body, and that includes a fin, and a connecting portion that is thermally connected to the fin at a position other than an apex of the fin and is also thermally connected to an electronic component.
    Type: Application
    Filed: December 27, 2016
    Publication date: April 20, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Suzuki, Kanae Nakagawa
  • Publication number: 20170110387
    Abstract: A semiconductor device includes a semiconductor package and a mark. The semiconductor package includes a semiconductor chip including a hot spot from which heat is generated, and a mold layer encapsulating the semiconductor chip. The mark is disposed on the semiconductor package. The mark is formed in a region of the semiconductor package that corresponds to a position of the hot spot.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventor: YOUNG-DEUK KIM
  • Publication number: 20170110388
    Abstract: A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.
    Type: Application
    Filed: October 11, 2016
    Publication date: April 20, 2017
    Inventors: Sang Cheon PARK, Won Il LEE, Chajea JO, Taeje CHO
  • Publication number: 20170110389
    Abstract: A semiconductor device includes a lead frame; a semiconductor chip mounted on the lead frame; and an encapsulation resin, wherein a convexo-concave portion including a plurality of concave portions is provided at a covered portion of the lead frame that is covered by the encapsulation resin, wherein the planer shape of each of the concave portions is a circle, the diameter of which is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, or a polygon, the diameter of whose circumcircle is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, and wherein a ratio S/S0 is greater than or equal to 1.7 where ā€œSā€ is a surface area of the convexo-concave portion that is formed at a flat surface whose surface area is ā€œS0ā€.
    Type: Application
    Filed: September 1, 2016
    Publication date: April 20, 2017
    Inventor: Shintaro HAYASHI
  • Publication number: 20170110390
    Abstract: The invention relates to a support and/or clip for at least one semiconductor element with at least one functional surface (10) for connecting to the semiconductor element. The invention is further characterized by at least one solder resist cavity (12) with at least one flank wall (13), in particular a straight flank wall (13), and a delimiting edge (14) which adjoins the flank wall (13) and delimits the functional surface (10) at least on one side. The delimiting edge (14) forms a protrusion (15) which protrudes past the functional surface (10) in order to retain solder, and/or the flank wall (13) forms an undercut (16) for retaining solder at the delimiting edge (14).
    Type: Application
    Filed: March 26, 2015
    Publication date: April 20, 2017
    Applicant: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Andreas HINRICH, Reinhard DITZEL, Andreas KLEIN
  • Publication number: 20170110391
    Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen ST. GERMAIN, Roger M. ARBUTHNOT, Jay A. YODER, Dennis Lee CONNER
  • Publication number: 20170110392
    Abstract: A semiconductor package structure includes a first semiconductor substrate, a second semiconductor substrate, a semiconductor die electrically connected to the first semiconductor substrate, an interconnection element and an encapsulant. The first semiconductor substrate includes a first top pad, and the second semiconductor substrate includes a second bottom pad. The interconnection element connects the second bottom pad and the first top pad. The interconnection element includes a first cupped portion and a second arcuate portion, where the first portion is connected to the first top pad and the second portion is connected to the second bottom pad. The first portion and the second portion together define the interconnection element as a monolithic component. The encapsulant is disposed between the first semiconductor substrate and the second semiconductor substrate, and covers the semiconductor die and the interconnection element.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: Chun-Hung LIN, Yi-Ting CHEN, Shih-Ming HUANG, Ching-Rong LIN
  • Publication number: 20170110393
    Abstract: A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Kai-Ming Yang, Wang-Hsiang Tsai, Tzyy-Jang Tseng
  • Publication number: 20170110394
    Abstract: A wiring substrate includes an insulating layer, at least one via hole formed in the insulating layer, a first wiring layer formed on one surface of the insulating layer and having a droop portion at an end-side of the via hole, a second wiring layer formed on the other surface of the insulating layer, and a metal-plated layer formed in the via hole and configured to connect the second wiring layer and the droop portion of the first wiring layer. One surface of the insulating layer around the via hole is formed as a convex curved surface and the droop portion of the first wiring layer is arranged on the convex curved surface.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventor: Tatsuaki Denda
  • Publication number: 20170110395
    Abstract: A semiconductor device, in which a plurality of control terminals that correspond to a main terminal and the same semiconductor chip protrude from a surface of an encapsulating part, and a plurality of signal paths that include the plurality of control terminals are positioned so as to be aligned with the main terminal in a first direction. Provided in each of the plurality of signal paths are pairs of relay members having identical functions, and a first relay grouping that includes one relay member of the pair of relay and a second relay grouping that includes the other relay member of the pair are positioned neighboring each other aligned in the first direction, with the ordering of the first relay grouping being mirror-inverted relative to the second relay grouping.
    Type: Application
    Filed: March 5, 2015
    Publication date: April 20, 2017
    Applicant: DENSO CORPORATION
    Inventors: Akira IWABUCHI, Atsushi KANAMORI, Kenji ONODA, Syoichirou OOMAE
  • Publication number: 20170110396
    Abstract: According to an example aspect of the present invention, there is provided an apparatus comprising a silicon layer comprising security circuitry and a first part of a first sensor, an insulator layer attached on the silicon layer, comprising integrated therein a second part of the first sensor, and a conducting pathway coupling the security circuitry to the first sensor, comprising a portion extending on the insulator layer and portions extending at least partly through the insulator layer.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventor: John Cronin
  • Publication number: 20170110397
    Abstract: A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao
  • Publication number: 20170110398
    Abstract: An interconnection structure includes a non-insulator structure, a dielectric structure, and a conductive structure. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The trench opening has a bottom surface and at least one recess in the bottom surface. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The conductive structure is at least separated from the bottom of the recess.
    Type: Application
    Filed: December 29, 2015
    Publication date: April 20, 2017
    Inventors: Che-Cheng CHANG, Chih-Han LIN
  • Publication number: 20170110399
    Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Tatsuya Usami, Yukio Miura, Hideaki Tsuchiya
  • Publication number: 20170110400
    Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.
    Type: Application
    Filed: March 10, 2016
    Publication date: April 20, 2017
    Inventors: Shu-Hsiao TSAI, Rong-Hao SYU, Yi-Ling LIU, Cheng-Kuo LIN
  • Publication number: 20170110401
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kio-Chio Liu
  • Publication number: 20170110402
    Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Michael A. Smith, Eric H. Freeman
  • Publication number: 20170110403
    Abstract: A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: CHIEN LING HWANG, HSIN-HUNG LIAO, YU-TING CHIU
  • Publication number: 20170110404
    Abstract: Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, and at least two gate trenches formed in the semiconductor substrate. Each of the trenches comprises a gate electrode. The semiconductor device also includes a body contact trench formed in the semiconductor substrate between the gate trenches. The body contact trench has a lower width at the bottom of the body contact trench and an ohmic body contact implant beneath the body contact trench. The horizontal extent of the ohmic body contact implant is at least the lower width of the body contact trench.
    Type: Application
    Filed: September 13, 2016
    Publication date: April 20, 2017
    Inventors: Lingpeng GUAN, Kyle TERRILL, Seokjin JO
  • Publication number: 20170110405
    Abstract: The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues.
    Type: Application
    Filed: July 19, 2016
    Publication date: April 20, 2017
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Yung-Sung Yen
  • Publication number: 20170110406
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Wei-Che HUANG, Yu-Hua HUANG, Tzu-Hung LIN, Kuei-Ti CHAN, Ruey-Beei WU, Kai-Bin WU
  • Publication number: 20170110407
    Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Applicant: XILINX, INC.
    Inventors: Raghunandan Chaware, Amitava Majumdar, Glenn O'Rourke, Inderjit Singh
  • Publication number: 20170110408
    Abstract: An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.
    Type: Application
    Filed: October 19, 2015
    Publication date: April 20, 2017
    Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Sueann Lim Wei Fen
  • Publication number: 20170110409
    Abstract: A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: Fu-Chiang KUO, Ying-Hsun CHEN, Shih-Chi KUO, Tsung-Hsien LEE
  • Publication number: 20170110410
    Abstract: A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is formed by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Applicant: NIKON CORPORATION
    Inventor: Tomoharu FUJIWARA
  • Publication number: 20170110411
    Abstract: A heat sink of a metallic shielding structure is provided in this disclosure, which includes a heating module and a cooling module. The heating module includes a heat generating component, a substrate, and a shield housing. The heat generating component is electrically connected to one side surface of the substrate and forms an opening corresponding the substrate. The cooling module includes a body and a working fluid is disposed in the body.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventors: George A. Meyer IV, Hsin-Hua WEN, Ming-Kuei HSIEH, Chieh-Ping CHEN
  • Publication number: 20170110412
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Application
    Filed: October 19, 2015
    Publication date: April 20, 2017
    Inventors: CHUEI-TANG WANG, VINCENT CHEN, TZU-CHUN TANG, CHEN-HUA YU, CHING-FENG YANG, MING-KAI LIU, YEN-PING WANG, KAI-CHIANG WU, SHOU ZEN CHANG, WEI-TING LIN, CHUN-LIN LU
  • Publication number: 20170110413
    Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang, Tien-Chung Yang
  • Publication number: 20170110414
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 20, 2017
    Applicant: COORSTEK KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Noriko OMORI, Hiroshi OISHI, Jun KOMIYAMA
  • Publication number: 20170110415
    Abstract: A method for manufacturing a semiconductor apparatus, including an encapsulating step of collectively encapsulating a device mounting surface of a substrate having semiconductor devices mounted thereon with a base-attached encapsulant having a base and a thermosetting resin layer formed on one surface of the base, the semiconductor devices being mounted by flip chip bonding, the encapsulating step including a unifying stage of unifying the substrate having the semiconductor devices mounted thereon and the base-attached encapsulant under a reduced pressure condition with a vacuum of 10 kPa or less, and a pressing stage of pressing the unified substrate with a pressure of 0.2 MPa or more.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 20, 2017
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tomoaki NAKAMURA, Hideki AKIBA, Toshio SHIOBARA
  • Publication number: 20170110416
    Abstract: Disclose is a chip package having an adhesive protection piece compliantly attached on the chip sensing surface, comprising a substrate, a main chip disposed on the substrate, an adhesive protection piece covering the main chip and an encapsulant encapsulating the main chip. The main chip has a chip sensing surface facing to a direction away from the substrate and a connection terminal electrically connected to the substrate. The adhesive protection piece essentially consists of a pick-and-place sheet and a die-bonding layer. The encapsulant completely encapsulates the die-bonding layer without covering the external surface of the pick-and-place sheet. The adhesive protection piece is compliantly attached to the chip sensing surface by pick-and-place processes so that the die-bonding layer is attached to the chip sensing surface with a constant adhesive gap.
    Type: Application
    Filed: May 20, 2016
    Publication date: April 20, 2017
    Inventors: Hong-Yan MIAO, Yi HUA, Zhi-Ling LIU, Ruo-Xu JIN
  • Publication number: 20170110417
    Abstract: In embodiments, the present invention may attach at least two isolated electronic components to an elastomeric substrate, and arrange an electrical interconnection between the components in a boustrophedonic pattern interconnecting the two isolated electronic components with the electrical interconnection. The elastomeric substrate may then be stretched such that the components separate relative to one another, where the electrical interconnection maintains substantially identical electrical performance characteristics during stretching, and where the stretching may extend the separation distance between the electrical components to many times that of the unstretched distance.
    Type: Application
    Filed: October 28, 2016
    Publication date: April 20, 2017
    Inventors: William J. Arora, Roozbeh Ghaffari
  • Publication number: 20170110418
    Abstract: According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified RS master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an RS latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified RS master latch in response to an RS latch forbidden input transition has a predetermined defined logic state, forming an RS slave latch having a set input and a reset input and connecting the set input or the reset input of the RS-slave latch to the output of the modified RS master latch.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Thomas Kuenemund, Berndt Gammel
  • Publication number: 20170110419
    Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: Shing-Yih Shih, Hsu Chiang
  • Publication number: 20170110420
    Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.
    Type: Application
    Filed: February 23, 2016
    Publication date: April 20, 2017
    Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
  • Publication number: 20170110421
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: June 1, 2016
    Publication date: April 20, 2017
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20170110422
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Applicant: INTEL CORPORATION
    Inventors: Srinivas V. Pietambaram, Kyu-Oh Lee
  • Publication number: 20170110423
    Abstract: According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 20, 2017
    Inventors: Johann Gatterbauer, Bernhard Weidgans, Dietrich Bonart, Thomas Gross, Martina Debie
  • Publication number: 20170110424
    Abstract: A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20170110425
    Abstract: An embodiment method includes providing a carrier having a recess and attaching a die to the carrier, wherein the die is at least partially disposed in the recess. The method further includes forming a molding compound over the carrier and around at least a portion of the die, forming fan-out redistribution layers over the molding compound and electrically connected to the die, and removing the carrier.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Chang-Pin Huang, Chen-Hua Yu, Ching-Jung Yang, Chung-Shi Liu, Hsien-Ming Tu, Hung-Yi Kuo, Hao-Yi Tsai, Shih-Wei Liang, Yu-Chia Lai
  • Publication number: 20170110426
    Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Han Chen, Hsun-Wei Chan, Mei-Yi Wu
  • Publication number: 20170110427
    Abstract: A chip package can include a chip, a plurality of metal posts, an encapsulating body and a redistribution layer. The plurality of metal posts surrounds the chip. The encapsulating body surrounds the chip and the plurality of metal posts. The redistribution layer is coupled to the encapsulating body and electrically coupled to the chip and the plurality of metal posts. A method for manufacturing the chip package is also provided.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 20, 2017
    Inventor: WEI-SHUO SU