Abstract: A polymer, an organic layer composition, and a method of forming patterns, the polymer including a structural unit represented by Chemical Formula 1:

Abstract: A local thinning process is employed on the backside of a semiconductor substrate such as a wafer in order to improve the thermal performance of the electronic device built on or in the front side of the wafer.

Abstract: A method is provided for manufacturing an etched surface. The method includes the steps of assembling a plurality of particles on the surface of a substrate and etching the plurality of particles to vary the size and spacing of the particles on the surface of the substrate. The method further includes depositing a mask material on the substrate including the etched particles, removing the etched particles from the substrate, thereby exposing the substrate beneath the plurality of particles, and selectively etching the substrate exposed after removal of the plurality of particles.

Abstract: A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate. A second layer of the layer stack is less etched or non-etched compared to the selective etching of the first layer of the layer stack, such that the first layer of the layer stack is laterally etched back between the semiconductor substrate and the second layer of the layer stack. The method further includes growing semiconductor material on regions of the surface of the semiconductor substrate exposed after the selective etching process.

Abstract: A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas.

Abstract: A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.

Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.

Abstract: A method for selectively etching a silicon nitride layer on a substrate includes arranging a substrate on a substrate support of a substrate processing chamber. The substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device. The gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region. The method includes supplying an etch gas mixture to the upper chamber region and striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil. The etch gas mixture etches silicon nitride, promotes silicon dioxide passivation and promotes polysilicon passivation, The method includes selectively etching the silicon nitride layer on the substrate and extinguishing the inductively coupled plasma after a predetermined period.

Abstract: Methods for minimizing sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: A semiconductor device including an oxide conductor with high conductivity and high transmittance is provided. A manufacturing method for a semiconductor device includes the steps of: forming an oxide semiconductor over a first insulator; forming a second insulator over the first insulator and the oxide semiconductor; forming a first conductor over the second insulator; forming an etching mask over the first conductor; forming a second conductor including a region overlapping with the oxide semiconductor by etching the first conductor with use of the etching mask as a mask; removing the etching mask; and performing heat treatment after forming a hydrogen-containing layer over the second insulator and the second conductor.

Abstract: Two-dimensional (2D) transition-metal dichalcogenides have emerged as a promising material system for optoelectronic applications, but their primary figure-of-merit, the room-temperature photoluminescence quantum yield (QY) is extremely poor. The prototypical 2D material, MoS2 is reported to have a maximum QY of 0.6% which indicates a considerable defect density. We report on an air-stable solution-based chemical treatment by an organic superacid which uniformly enhances the photoluminescence and minority carrier lifetime of MoS2 monolayers by over two orders of magnitude. The treatment eliminates defect-mediated non-radiative recombination, thus resulting in a final QY of over 95% with a longest observed lifetime of 10.8±0.6 nanoseconds. Obtaining perfect optoelectronic monolayers opens the door for highly efficient light emitting diodes, lasers, and solar cells based on 2D materials.

Abstract: A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.

Abstract: A pressing unit including a pressing pin is attached to a mold, a semiconductor chip, first and second heat sinks, and solders are disposed in a cavity of the mold, a mold closing state is made, and a reflow is carried out in a state where the first and second heat sinks are pressed against first and second wall surfaces by the pressing pin to form a laminated body. After the laminated body is formed, the pressing pin is pulled out from the cavity, and a resin molded body is formed by injecting a resin.

Abstract: A die mounting system in which die supply device is set on component mounter and dies supplied from die supply device are mounted on circuit board by mounting head of component mounter, determines the next die transfer position is determined such that the longer of time required for die transfer preparation operation (die imaging and image processing, die pickup operation, and movement and vertical inverting operation of a supply head) of die supply device and time required for die mounting operation (movement and vertical motion at the mounting position of mounting head) of component mounter is made shorter, and the difference (which corresponds to the waiting time at the die transfer position) between the two times decreased, such that the cycle time is shortened.

Abstract: For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.

Abstract: The present invention provides a wet etching apparatus. The wet etching apparatus comprises: an etching chamber, comprising an etching chamber inlet at a front end and an etching chamber outlet at a rear end, wherein in the etching chamber, a film to be etched on a substrate is subject to etching with an etching liquid; and a decrystallization device, which washes residual etching liquid or etching liquid crystal formed by the etching liquid at the etching chamber inlet and/or etching chamber outlet with a washing liquid. By means of the decrystallization device, residual etching liquid or etching liquid crystal formed by the etching liquid at the etching chamber inlet and the etching chamber outlet can be effectively removed, thus improving operation ratio and cleanness of the apparatus as well as quality of products.

Abstract: Provided is a nozzle system for dispensing a dispense chemical onto a substrate, the system comprising: a nozzle comprising a nozzle body and a nozzle tip; a shielding device coupled to the nozzle tip, the shielding device configured to create a mini-environment for a dispense chemical such that a partial pressure of the dispense chemical is maintained in the shielding device; wherein the nozzle system is configured to meet selected dispense objectives.

Abstract: In certain embodiments the metal liftoff tool comprises an immersion tank for receiving a wafer cassette with wafers therein, the immersion tank including an inner weir, a lifting and lowering mechanism capable of raising and lowering the wafer cassette while submerged in fluid in the immersion tank, low pressure high velocity primary spray jets for stripping the metal, the primary spray jets positioned at opposing sides of the immersion tank parallel to the wafer surfaces planes, and secondary spray jets for pressure equalization force, positioned at the bottom of the immersion tank. A wafer lift insert is positioned at the bottom of the immersion tank to receive and periodically lift the wafers within the cassette.

Abstract: Disclosed are a substrate supporting unit, a substrate processing apparatus, and a method of manufacturing the substrate supporting unit. The substrate supporting unit includes a susceptor provided with heaters to heat a substrate placed on the susceptor, and including a first temperature region and a second temperature region having a higher temperature than that of the first temperature region; and a heat dissipating member including a contact surface being in thermal contact with the second temperature region. The heat dissipating member further includes an opening corresponding to the first temperature region. The heat dissipating member formed in a ring shape, in which the opening is surrounded with the contact surface, and the contact surface of the heat dissipating member makes thermal contact with the lower surface of the susceptor.

Abstract: A decapsulation apparatus has an etch plate, an off-center etch head having an opening, a cover sealing to the etch plate forming an etching chamber, a gasket surrounding the opening, a ram sealed through the cover, a pressure-controlled source of Nitrogen or inert gas continuously purging the etching chamber at a low gas pressure, a f toggle mechanism mounted to a metal plate t, an etchant supply subsystem comprising sources of etchant solutions, an etchant solution pump, supply passages and controls to select etchants and etchant ratios, and a heat exchanger heating or cooling the etchant solution, etchant waste passages f conducting used etchant away. Etchants are mixed in the passages to the reaction region, and turbulence in the reaction region is promoted by impinging etchant solution on the encapsulated device.

Abstract: A substrate processing system for performing a process with respect to a plurality of substrates includes an annular process chamber configured to accommodate the plurality of substrates and to perform a predetermined process on the plurality of substrates, a cassette mounting part configured to mount a cassette which accommodates the plurality of substrates, and a substrate transfer mechanism configured to transfer the plurality of substrates between the annular process chamber and the cassette mounting part. The plurality of substrates is concentrically disposed within the annular process chamber in a plane view.

Abstract: A system for processing substrates is provided, comprising: a wafer transport assembly that is configured to transport wafers to and from one or more process modules, the wafer transport assembly having at least one wafer transport module, wherein lateral sides of the at least one wafer transport module are configured to couple to the one or more process modules; a service floor defined below the wafer transport assembly, the service floor being defined at a height that is less than a height of a fabrication facility floor in which the system is disposed.

Abstract: A load lock assembly includes a first load lock connected between an equipment front end module (EFEM) and a wafer transport module, the EFEM being at a lab ambient condition, the wafer transport module being at a vacuum condition, the wafer transport module being part of a wafer transport assembly that is configured to transport wafers to and from one or more process modules that are connected to the wafer transport assembly; a second load lock disposed over the first load lock, the second load lock connected between the EFEM and the wafer transport module; a post-processing module disposed over the second load lock, the post-processing module configured for performing a post-processing operation on a processed wafer that has been processed in at least one of the process modules that are connected to the wafer transport assembly, the post-processing module being configured for connection to the wafer transport module.

Abstract: Embodiments described herein relate to a substrate carrier system. The substrate carrier system includes a carrier for transferring a substrate within a multi-chamber processing system. The carrier may be placed in a load lock chamber for receiving the substrate, and the substrate is transferred to a processing chamber on the carrier. In the processing chamber, the carrier, with substrate, is disposed on a susceptor. The carrier can also enhance thermal control of the edge of the substrate in the processing chamber. The substrate carrier system further includes positioning features for repeatable positioning of the substrate in the processing chamber and repeatable positioning of the carrier in the load lock chamber and the processing chamber.

Abstract: A wafer boat includes a base, a plurality of support rods and a plurality of cantilever arms. The support rods are carried by the base. The support rods are disposed around a space above the base. The cantilever arms are carried by the support rods. At least two of the cantilever arms carried by at least one of the support rods are vertically spaced apart to define at least one slot for a wafer.

Abstract: A wafer transport assembly includes first and second wafer transport modules, and a buffer module coupled between the first and second wafer transport modules. The first and second wafer transport modules and the buffer module are aligned in a single directional axis. The buffer module includes a first buffer stack positioned at a first lateral end of the buffer module, and a second buffer stack positioned at a second lateral end of the buffer module. The first lateral end of the buffer module defines a first side protrusion nested between the first and second wafer transport modules and first and second process modules. The second lateral end of the buffer module defines a second side protrusion that is nested between the first and second wafer transport modules and third and fourth process modules. The first and second wafer transport modules and the buffer module define a continuous controlled environment.

Abstract: The present invention provides a substrate cleaning apparatus for a substrate related to a photomask, including a holder for holding only an end face of the substrate, a rotation mechanism for rotating the holder, and a nozzle for supplying liquid at least to the front surface of the substrate rotating with the holder by the rotation mechanism; wherein at least one of the holder has a conductive surface and is earthed. The present invention also provides a method for cleaning a substrate related to a photomask. These inventions can prevent adhesion of contaminants to the substrate when performing a cleaning treatment.

Abstract: An Electrostatic Chuck (ESC) in a chamber of a semiconductor manufacturing apparatus is presented for eliminating cooling-gas light-up. One wafer support includes a baseplate connected to a radiofrequency power source, a dielectric block, gas supply channels for cooling the wafer bottom, and first and second electrodes. The dielectric block is situated above the baseplate and supports the wafer when present. The first electrode is embedded in the top half of the dielectric block, where the top surface of the first electrode is substantially parallel to a top surface of the dielectric block, and the first electrode is connected to a DC power source. Further, the second electrode is embedded in a bottom half of the dielectric block, the second electrode being electrically connected to the first electrode, where the bottom surface of the second electrode is substantially parallel to a top surface of the baseplate.

Abstract: A heating member includes a ceramic substrate having a structure in which a plurality of ceramic layers are laminated together; a resistance heat-generating element embedded in the ceramic substrate; an electricity supply element disposed on a surface of the ceramic substrate; and an electricity supply path embedded in the ceramic substrate and electrically connecting the resistance heat-generating element and the electricity supply element. The electricity supply path includes a plurality of conductive layers disposed along the planar direction of the ceramic layers at different positions in the thickness direction of the ceramic substrate, and a plurality of vias disposed along the thickness direction of the ceramic substrate. When the plurality of conductive layers are viewed from the thickness direction, their outer edges are positionally offset from one another.

Abstract: Implementations described herein provide a chucking circuit for a pixilated electrostatic chuck which enables both lateral and azimuthal tuning of the RF coupling between an electrostatic chuck and a substrate placed thereon. In one embodiment, a chucking circuit for an electrostatic chuck (ESC) has one or more chucking electrodes disposed in a dielectric body of the ESC, a plurality of pixel electrodes disposed in the dielectric body, and a chucking circuit having the one or more chucking electrodes and the plurality of pixel electrodes, the chucking circuit operable to electrostatically chuck a substrate to a workpiece support surface of the ESC, the chucking circuit having a plurality of secondary circuits, wherein each secondary circuit includes at least one capacitor of a plurality of capacitors, each secondary circuit is configured to independently control an impedance between one of the pixel electrodes and a ground.

Abstract: Method for a controlled spalling utilizing vaporizable release layers. For example, a method comprises providing a base substrate, depositing a stressor layer and a vaporizable release layer on the base substrate, forming a flexible support layer on at least one of the stressor layer and the vaporizable release layer, spalling an upper portion of the base substrate, securing the spalled upper portion of the base substrate to a handle substrate, and vaporizing the vaporizable release layer.

Abstract: A wafer processing laminate including support, temporary adhesive material layer formed on support, and wafer stacked on temporary adhesive material layer, wafer having front surface on which circuit is formed and back surface to be processed, wherein temporary adhesive material layer includes a three-layered complex temporary adhesive material layer that includes first temporary adhesive layer composed of thermoplastic organopolysiloxane polymer layer (A) having thickness of less than 100 nm and releasably laminated to front surface of wafer, second temporary adhesive layer composed of thermosetting siloxane-modified polymer layer (B) releasably laminated to first temporary adhesive layer, and third temporary adhesive layer composed of thermoplastic organopolysiloxane polymer layer (A?) having thickness of less than 100 nm, releasably laminated to second temporary adhesive layer, and releasably laminated to support.

Abstract: Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.

Abstract: Present embodiments provide for A SOI substrate and fabricating method thereof are provided. The fabricating method of SOI substrate comprises: providing a first substrate, wherein a first dielectric layer is formed on the first substrate; implanting deuterium ions into the first substrate, wherein a deuterium-impurity layer is formed in the first substrate at predetermined depth; providing a second substrate, wherein a second dielectric layer is formed on the second substrate and bounded with the first dielectric layer; performing an annealing process, wherein microbubbles are formed in the deuterium-impurity layer; and cutting the first substrate from the deuterium-impurity layer to obtain the SOI substrate.

Abstract: [Problem] To provide a liquid cleaning composition for removing a titanium nitride hard mask while suppressing damage to copper, a copper alloy, cobalt or a cobalt alloy upon fabricating a semiconductor device, a cleaning method using the same, and a method for fabricating a semiconductor device. [Solution] A liquid cleaning composition of the present invention used for fabricating a semiconductor device comprises hydrogen peroxide at 1-30% by mass, potassium hydroxide at 0.01-1% by mass, aminopolymethylene phosphoric acid at 0.0001-0.01% by mass, a zinc salt at 0.0001-0.1% by mass and water.

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

Abstract: A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.

Abstract: The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern.

Abstract: A method includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The method includes an adhesion layer formed in the dielectric layer and over the first metal layer, and the adhesion layer is a discontinuous layer. The method includes a second metal layer formed in the dielectric layer, and the adhesion layer is formed between the second metal layer and the dielectric layer. The second metal layer includes a via portion and a trench portion over the via portion, and the trench portion is wider than the via portion.

Abstract: A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.

Abstract: An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher elastic modulus than Cu; a second insulating film on the first insulating film; and a via plug composed of Cu and arranged in the second insulating film, the via plug being in contact with the metal film.

Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.

Abstract: A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a N-type field-effect transistor positioned in the semiconductor substrate, and a P-type field-effect transistor positioned in the semiconductor substrate and spaced apart the N-type field-effect transistor. N-type field-effect transistor includes a first germanium nanowire, a first III-V compound layer surrounding around the first germanium nanowire, a first potential barrier layer mounted on the first III-V compound layer, a first gate dielectric layer, a first gate, a first source region and a first drain region mounted on two sides of the first gate.

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.

Abstract: A method for equalizing the thickness variation of a substrate stack comprised of a product substrate and a carrier substrate and which is connected in particular by means of an interconnect layer, by local application of local thickness peaks by means of an application apparatus which has at least one application unit. Furthermore this invention relates to a corresponding device.