Abstract: According to one embodiment, a magnetic disk device includes a disk including a tracks including a servo region, a light irradiator configured to irradiate the disk with light and heat the disk with the light, a head including a write head configured to write data in a range irradiated and heated with the light, and a read head configured to read data from the tracks, a controller configured to write first data to be used for offset detection in a first region of the tracks, read the first data from the first region with reference to servo data in the servo region, detect an offset of the read head based on an amplitude of a first signal of the first data, and control a position of the read head based on the offset.

Abstract: Disclosed herein is a hard disk drive slider having an extended three-dimensional air-bearing surface (ABS). The slider has an ABS and a back surface opposite the ABS, where at least a portion of the back surface defines a plane (i.e., if the back surface is substantially flat, the back surface itself defines the plane). Defined herein is an ABS function, which describes the characteristics of a portion of the ABS in a two-dimensional plane made by taking a cross-section of the slider perpendicular to the plane defined by the at least a portion of the back surface. The cross-section of the slider taken perpendicular to the plane has an ABS function that is a multi-valued function, which is defined herein as a relation for which, for at least one possible input value along the selected axis in the plane, the relation evaluates to two or more distinct nonzero values.

Abstract: Disclosed herein are hard disk drive sliders having one or more tunnels between the leading-edge surface of the slider and the air-bearing surface (ABS) that may be used to control the pitch and/or fly height of the slider. A slider comprises a leading-edge surface, an ABS, and a tunnel having an entry area at the leading-edge surface and an exit area at the ABS, the tunnel for directing gas impinging on the entry area through the slider and out the exit area toward a surface of a hard disk. The tunnel may be a convergent tunnel. The tunnel may include two or more branches.

Abstract: The optical information recording device includes a light source configured to emit a laser beam, an optical element configured to divide the laser beam into the reference beam and the signal beam, an angle control unit configured to control an angle of incidence of the reference beam on the optical information recording medium, and a phase control unit configured to control a phase of at least one of the signal beam and the reference beam in a recording period, wherein the angle control unit controls an angle interval so that a position of a 1st null of an adjacent page of the signal beam is fixed, and wherein the phase control unit controls the phase of the signal beam or the reference beam so that a phase difference between the adjacent pages is a predetermined value.

Abstract: Recorded in a recording medium are a video stream of standard-luminance range, and a video stream of high-luminance range that is a broader luminance range than the standard-luminance range, which are used selectively in accordance with a playback environment, a subtitle stream of the standard-luminance range, and a subtitle stream of the high-luminance range, which are used selectively in accordance with the playback environment, and a playlist file storing playback control information of content, playlist file including a management region where the playback control information relating to a main stream is stored, and an extended region. The management region stores first playback control information specifying playing of a video stream of the high-luminance range and a subtitle stream of the high-luminance range in combination.

Abstract: An aspect includes gathering audio feeds captured from sources at a function. Each of the audio feeds is annotated with metadata identifying a time of capture and geo-coordinates of a location of the source. An aspect also includes mapping the audio feeds to a video feed captured by a first device at the function. The video feed is annotated with metadata identifying a time of capture and geo-coordinates of locations corresponding to images in the video feed. An aspect further includes identifying geo-coordinates of a location corresponding to an image in a focal point of view of a second device, searching the database for audio feeds in which the geo-coordinates of the sources are within a defined range of the geo-coordinates of the location corresponding to the image in the focal point of view, and transmitting, to the second device, a listing of user-selectable audio feeds resulting from the searching.

Abstract: The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.

Abstract: Data including a digital stream obtained by encoding video information is recorded in a recording medium. A recording region of the recording medium has a first recording region where reading is performed at a first read rate, and a second recording region where reading is performed at a second read rate that is faster than the first read rate. The data includes a digital stream having real-time attributes and a data file having non-real-time attributes. The data file to be read in during playback of the digital stream is recorded in, of the first recording region and the second recording region, the same recording region as the recording region where the digital stream is recorded.

Abstract: Implementations described and claimed herein includes a storage device comprising a plurality of readers, including a first subset of readers configured to read a first subset of tracks and a second subset of readers configured to read a second subset of tracks, the first subset of tracks being wider than the second subset of tracks. In another implementation, the readers in the first subset of readers are wider than the readers in the second subset of readers. The wider readers may be configured to recover servo information and the narrow readers may be configured to recover data information. The storage devices may include two-dimensional magnetic recording, conventional perpendicular magnetic recording, shingled magnetic recording, multi-sensor magnetic recording, and interlaced magnetic recording.

Abstract: Implementations disclosed herein provide a method comprising comparing high-latency data sectors of a storage band, the high-latency data sectors having latency above a predetermined threshold, with target sectors for storing new data to determine one or more of the high-latency data sectors that may be skipped during retrieval of at-rest data from the storage band.

Abstract: According to one embodiment, a magnetic disk device includes a disk including a first recording area, a head includes a write head configured to write data to the disk, and a read head configured to read data from the disk, and a controller configured to set particular areas in same circumferential positions on tracks of the first recording area, and to write, to the respective particular areas, parity data based on data read from areas other than the particular areas.

Abstract: Features described herein relate to providing the capability to playback audiovisual content in a comprehensible manner at a rate adjustable by the viewer. For example, if a viewer wishes to watch a one hour news program, but the viewer only has thirty minutes to view the program, playback of the program at twice the rate, but in a comprehensible manner is provided. To provide the playback of the video at the adjustable rate, substitute audio is generated by adding or removing audio content without changing the playback rate of the audio. The video at the adjusted playback rate and the substitute audio at the normal playback rate may have the same duration and in some embodiments, may be presented synchronously.

Abstract: Disclosed herein are an electronic device and a method of managing a playback rate of a plurality of images using an electronic device. The electronic device may include a display, an image capturing unit configured to obtain a plurality of images, a motion detecting unit configured to detect motion data of at least one region of interest (ROI) in the plurality of images, and a controller configured to determine at least one playback rate for the plurality of images based on the detected motion data and control the display to display the plurality of images based on the at least one playback rate.

Abstract: Implementations are directed to providing a digital media editing environment for editing at least a portion of a digital video using a mobile device, establishing communication between the mobile device and a data source, receiving, from the data source, a first portion of the digital video, the first portion including a first set of frames including less than all frames of the digital video, applying an edit to the first portion of the digital video, while less than all frames of the first digital video are stored on the mobile device, subsequent to applying the at least one edit, receiving, from the data source, a second portion of the digital video, the second portion including a second set of frames, and storing an edited digital video including at least one frame of the first set of frames, at least one frame of the second set of frames, and the edit.

Abstract: The systems and methods discussed herein relate to technology for enhancing media recordings of a live event based on a media feed corresponding to the live event. The media recordings may be media items that include audio and image data captured by a user device. The user device may be associated with a member of an audience that is experiencing the live event. The user device may generate the media item using one or more sensory input devices and may receive additional media data via a media feed. The media feed may include media data that corresponds to the live event and includes content that is similar to the media item recorded by the user device but may have been derived from a higher quality recording or include supplemental data. The media data may then be used to enhance the media item.

Abstract: A first method utilizes placeholder tags to facilitate a user's adding a tag to a video scene during a production process of a video. The tag is associated with an item depicted in the video and characterized by size, shape, temporal duration, and spatial location properties with respect to the video scene. A second method facilitates a user's customizing a video scene during a production process of a video, wherein computer-generated graphic content (logo or brand name for the tagged item) is overlaid on the item depicted in the video and associated with the tag. A third method facilitates a user to add a tag to a video scene during a production process of a video, where the video scene is related to another video scene associated with the video, and the method stores data associated with said another video scene to note the tag.

Abstract: Electronic delivery techniques for distribution of audiovisual and associated data files via communication networks. The techniques including conversion of data files to generate modified versions thereof and provision of access to the files and the modified files by designated recipients for limited time periods.

Abstract: Recorded in a recording medium is a video stream, map information, and bitrate information of the video stream. The map information includes size information indicating data size of a section where a picture is recorded in the video stream, based on a predetermined stipulated data size. The stipulated data size differs in accordance with the bitrate information.

Abstract: A data transferring device and a data transfer method. The data transferring device for transferring an audio-visual stream stored in a first medium to a second medium, includes: a reader comprising reading circuitry configured to read the audio-visual stream from the first medium; and a controller configured to: extract an audio packet and a video packet from the audio-visual stream; write the audio packet and video packet to the second medium; and store, in a memory, first location information indicating locations at which the audio packet and the video packet are written in the second medium, and second location information indicating locations at which the audio packet and the video packet are read from the first medium.

Abstract: Various embodiments of a magnetic stack are disclosed. In one or more embodiments, the magnetic stack includes first and second shield layers, and a magnetically responsive lamination disposed between the first and second shield layers. The magnetically responsive lamination can be configured to receive a sense current IS therethrough. The magnetic stack also includes a cooling element disposed between the first and second shield layers and thermally coupled to the magnetically responsive lamination. The cooling element can be configured to receive a bias current IB therethrough. And the cooling element can be configured to cool the magnetically responsive lamination during a read function.

Abstract: Provided herein are a voltage regulator, a memory system having the same and an operation method thereof. The memory system includes a memory device configured to store data, a controller configured to control the memory device, and a voltage regulator configured to supply a pump-out voltage to the memory device or the controller so that the memory device or the controller is operated in the following manner: until a level of the pump-out voltage is increased to a second reference voltage lower than a first reference voltage, the pump-out voltage is output using a clock having a first frequency; when the pump-out voltage exceeds the second reference voltage and does not exceed the first reference voltage, the pump-out voltage is output using a clock having a second frequency lower than the first frequency; and when the pump-out voltage exceeds the first reference voltage, the pump-out voltage is output using the clock having the first frequency.

Abstract: A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a first data strobe signal and a second data strobe signal to generate a buffer output signal and an inverted buffer output signal. The strobe signal division circuit may divide the buffer output signal and the inverted buffer output signal to generate internal strobe signals which are used in capturing data when receiving data. The drive control circuit may drive the buffer output signal to a predetermined logic level during an initial section of time from a point of time when a write operation is performed.

Abstract: In one embodiment, a SO-STT device has a non-symmetric device geometry. The device may be fabricated to have a non-symmetric magnetic pattern by tilting a shaped magnetic pattern (e.g., an ellipse, diamond, rectangle, etc. shaped magnetic pattern) such that the pattern's main (long and short) axes are tilted with respected to an in-plane current direction. Alternatively, the non-symmetric device geometry may be produced by locating the magnetic pattern away from the center of a current injection line. The non-symmetric may permit switching absent application of an external magnetic field. A SO-STT device with non-symmetric device geometry, or another type of SO-STT device, may further integrate an additional semiconductor, insulator or metal layer into the device's multilayer stack. By integrating the additional semiconductor, insulator or metal layer, a significant reduction of SO-STT switching current density may be achieved.

Abstract: Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.

Abstract: A memory array comprises a plurality of memory cells arranged in columns and rows. The memory array also comprises a plurality of first-type strap cells arranged in a row, wherein each first-type strap cell comprises a first-type well strap structure. The memory array further comprises a plurality of second-type strap cells arranged in a row. Each second-type strap cell comprises a second-type well strap structure. Each column of memory cells is bracketed by at least one first-type strap cell of the plurality of first-type strap cells or at least one second-type strap cell of the plurality of second-type strap cells.

Abstract: Systems, methods and/or devices are used to adjust a read property for a memory portion of non-volatile memory. In one aspect, in response to receiving a program request, the device: detects a first temperature of the memory portion; and stores first temperature data corresponding to the detected first temperature. In response to receiving a read request, the device performs an adjustment determination, including: detecting a second temperature of the memory portion of the non-volatile memory, retrieving the stored first temperature data, and determining, in accordance with the detected second temperature and the retrieved first temperature data, whether to perform the read using an adjusted read property. In accordance with a determination to perform the read using the adjusted read property, the device performs a read on the memory portion using the adjusted read property.

Abstract: A system for asymmetrically selecting a memory element is described. The system includes a number of memory cells in a crossbar array. Each memory cell includes a memory element to store information. The memory element is defined as an intersection between a column electrode and a row electrode of the crossbar array. Each memory cell also includes a selector to select a target memory element by relaying a first selecting voltage to a column electrode that corresponds to the target memory element and relaying a second selecting voltage to a row electrode that corresponds to the target memory element. The system also includes a controller to pass a first standing voltage to column electrodes of the crossbar array and to pass a second standing voltage to row electrodes of the crossbar array. The first standing voltage is different than the second standing voltage.

Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

Abstract: According to an example, an apparatus may include an input line, an output line, and a memory cell connected between the input line and the output line. The memory cell may include a memristor connected in series with a selector. The apparatus may also include a shunt device connected to the input line, in which the shunt device is to divert a portion of current away from the memory cell in response to a voltage at the input line being greater than a threshold voltage.

Abstract: A method of increasing a read margin in a memory cell may include sensing an input current created from the application of a read voltage across a memristive device, squaring the input current, and comparing the squared input current to a reference current. A memristive device may include a memristor and a sense amplifier communicatively coupled to the memristor wherein a sensed input current created from the application of a reference voltage across a memristor is squared and wherein the sense amplifier compares the squared input current to a reference current.

Abstract: The present invention relates to apparatuses and methods for limiting current in threshold switching memories. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits.

Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller.

Abstract: A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.

Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.

Abstract: A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, an address decoder configured to be connected to the memory cells through a plurality of word lines and to provide select or unselect read voltages to the word lines, and a control logic configured to control the address decoder to perform a plurality of read sequences in a continuous read mode and to adjust a word line setup start point in at least one of the read sequences to be different than a word line setup start point in at least one of the other read sequences, wherein the word line setup start point is a time at which the select or unselect read voltages begin to be provided to the word lines.

Abstract: A storage apparatus includes a flash memory that includes multiple blocks; and a control portion that reads data written in the block and writes the data into the block. The flash memory includes one block set having n pieces of the blocks including BR1 to BRn. A write data and a write flag are capable of being written into each of blocks BRi, the write data being written in accordance with a request, the write flag indicating that the write data has been written into a target block BRj. In accordance with a write request, the control portion performs an erasure process, a first write process, and a second write process. The erasure process erases the data including the write data and the write flag. The first write process writes the new write data into the block BRl. The second write process writes the write flag into a block BRm.

Abstract: Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include: drain select transistor coupled to a bit line; a source select transistor coupled to a source line; a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; and a peripheral circuit configured to successively apply a discharge control voltage to memory cells in sequence from a memory cell adjacent to the source select transistor to a memory cell adjacent to the drain select transistor.

Abstract: A method for controlling a nonvolatile memory device includes requesting a plurality of first sampling values from the nonvolatile memory device, each of the first sampling values representing the number of memory cells having a threshold voltage between a first sampling read voltage and a second sampling read voltage. The first sampling values are processed through a non-linear filtering operation to estimate the number of memory cells having the threshold voltage between the first sampling read voltage and the second sampling read voltage.

Abstract: A method for operating a non-volatile memory device initially includes supplying an erase voltage to the memory cells. The memory cells are in cell strings in a three-dimensional structure. The method further includes performing a first read operation of the memory cells, performing a second read operation of the memory cells, and then performing a first erase verify operation based on results of the first and second read operations. The first erase verify operation may include performing a first exclusive-or (XOR) operation on the first and second read operation results.

Abstract: A memory system includes a plurality of first signal lines to connect a plurality of memory devices to one another. The memory devices include a first memory device and at least one second memory device. The first memory device has at least one fuse cell and outputs fuse information set based on whether each of the at least one fuse cell is programmed. The at least one second memory device receives the fuse information and selectively activates the first signal lines based on the fuse information. The at least one second memory device simultaneously operates based on the fuse information received from the first memory device.

Abstract: A method and system are used to generate random values for Physical Unclonable Function (PUF) for use in cryptographic applications. A PUF value generation apparatus comprises two dielectric breakdown based anti-fuses and at least one current limiting circuit connected between anti-fuses and power rails. Two anti-fuses are connected in parallel for value generation in programming by applying high voltage to both anti-fuses at the same time. Time for dielectric breakdown under high voltage stress is of random nature and therefore unique for each anti-fuse cell. Therefore the random time to breakdown causes one cell to break before another, causing high breakdown current through the broken cell. Once high breakdown current through one broken or programmed cell is established, a voltage drop across a current limiting circuit leads to decreased voltage across both cells, thereby slowing the time dependent breakdown process in the second cell and preventing it from breakage under programming conditions.

Abstract: A template of instructions may be copied from a non-volatile memory (NVM) to a plurality of cache lines of an instruction cache of a processor. The instructions of the templates copied to the instruction cache may be executed. The templates may include a conditional branch instruction to determine if to proceed to a next template of the plurality of copied templates.