Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

Abstract: A manufacturing method for a memory device includes forming a stack structure over a substrate, forming a mask pattern over the stack structure, forming a first vertical hole by patterning the stack structure using the mask pattern, implanting a dopant into a sidewall of the first vertical hole to form a first region, wherein the first region is exposed by the mask pattern; and removing the first region to form a second vertical hole.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate. The dielectric layer has a first recess. The method includes forming a first conductive material layer over an inner wall and a bottom of the first recess. The first conductive material layer is partially filled in the first recess. The method includes performing a reflow process to convert the first conductive material layer into a first conductive layer. The first conductive layer has a second recess in the first recess. The method includes performing an electroplating process or an electroless plating process to form a second conductive layer over the first conductive layer so as to fill the second recess.

Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).

Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.

Abstract: Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the substrate a solution or colloidal dispersion of an alumina polymer, said solution or dispersion being obtained by hydrolysis and condensation of monomers of at least one aluminium oxide precursor in a solvent or a solvent mixture in the presence of water and a catalyst. The invention can be used for making a hard mask in a TSV process to form a high aspect ratio via a structure on a semiconductor substrate.

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area of a substrate, forming a first mask pattern on a cell array area of the substrate, the first mask pattern including a pair of first portions extending in parallel and a second portion covering a portion of a sidewall of the etch stop pattern and a portion of a sidewall of the first insulation pattern, forming a second insulation layer covering the etch stop pattern and the first mask pattern, partially etching the etch stop pattern and the second insulation layer to expose the second portion of the first mask pattern, and removing the second portion of the first mask pattern to divide the pair of first portions of the first mask pattern.

Abstract: One embodiment of the present invention relates to a polishing liquid for CMP containing cerium oxide particles and water, wherein the half-value width of the main peak appearing within a range from 2?=27.000 to 29.980° in a powder X-ray diffraction chart of the cerium oxide particles is from 0.26 to 0.36°, the average particle size of the cerium oxide particles is at least 130 nm but less than 175 nm, and the number of cerium oxide particles having a particle size of 1.15 ?m or greater is 5000×103/mL or less.

Abstract: There is provided a substrate processing method which includes: treating a substrate using a fluorine-containing gas; and exposing the substrate to a moisture-containing atmosphere.

Abstract: A liquid removal composition and process for removing anti-reflective coating (ARC) material and/or post-etch residue from a substrate having same thereon. The composition achieves at least partial removal of ARC material and/or post-etch residue in the manufacture of integrated circuitry with minimal etching of metal species on the substrate, such as aluminum, copper and cobalt alloys, and without damage to low-k dielectric and nitride-containing materials employed in the semiconductor architecture.

Abstract: A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

Abstract: The present invention relates to a vacuum evacuation system used to evacuate a processing gas from one or more process chambers for use in, for example, a semiconductor-device manufacturing apparatus. The vacuum evacuation system is a vacuum apparatus for evacuating a gas from a plurality of process chambers (1). The vacuum evacuation system includes a plurality of first vacuum pumps (5) coupled to the plurality of process chambers (1) respectively, a collecting pipe (7) coupled to the plurality of first vacuum pumps (5), and a second vacuum pump (8) coupled to the collecting pipe (7).

Abstract: A cleaning apparatus 1 is provided with a heating unit 5 that heats a cleaning surface of a substrate W, a cleaning unit 6 that supplies ozone water to the cleaning surface of the substrate W and cleans the cleaning surface and a control unit 7 that controls the heating of the cleaning surface and the supply of the cleaning liquid so as to clean the cleaning surface after heating the cleaning surface of the substrate W.

Abstract: Disclosed is a substrate processing apparatus including: a holding unit configured to hold a substrate; a processing liquid supply unit configured to supply a first processing liquid and a second processing liquid to the substrate; a first cup configured to recover the first processing liquid; a second cup disposed adjacent to the first cup and configured to recover the second processing liquid; a recovery portion defined by a peripheral wall portion that is erected on a bottom portion of the first cup; and a cleaning liquid supply unit configured to supply a cleaning liquid to the recovery portion. The peripheral wall portion is cleaned by causing the cleaning liquid supplied by the cleaning liquid supply unit to overflow from the peripheral wall portion to the second cup side.

Abstract: The interference between overhead travelling vehicles and a local vehicle is prevented, in a situation where an overhead travelling vehicle has trouble, and the overhead travelling vehicles and the controller cannot communicate. Carriers are temporarily stored between the overhead travelling vehicles and the load port. The local vehicle travels along a travelling rail for the local vehicle located below a travelling rail for the overhead travelling vehicles and over a load port, and plural buffers are provided. The overhead travelling vehicles and the local vehicle communicate with a controller via a terminal, and a sensor is provided at a height without interference with the local vehicle and detects an element of a hoist of the overhead travelling vehicles or a carrier raised/lowered. The local vehicle is restricted from travelling when the sensor detects an element of hoist or the carrier.

Abstract: Without a lateral transfer mechanism in a local vehicle, the buffering capacity of a temporary storage apparatus is increased. The temporary storage apparatus stores carriers temporarily between overhead travelling vehicles and load ports. A travelling rail for the local vehicle is provided to allow the local vehicle to run below the travelling rail for the overhead vehicles and over the load ports. A slidable buffer slidable between a position under the travelling rail for the local vehicle and a position shifted laterally and a controller for controlling the local vehicle and the slidable buffer are provided, and the local vehicle waits at a position separated from an area over the load ports.

Abstract: A system for zapping a wafer, the system includes a pulse generator; a sensor; a first conductive interface; a second conductive interface; a controller; wherein the pulse generator is configured to generate zapping pulses; wherein the first conductive interface is configured to provide the zapping pulses to a first location of a backside insulating layer of a wafer; wherein the sensor is configured to monitor a coupling between the first conductive interface and the second conductive interface to provide a monitoring result; wherein the monitoring occurs while the second conductive interface contacts a second location of the backside insulating layer; and wherein the controller is configured to control a generation of the zapping pulses in response to the monitoring result.

Abstract: A temporary adhesive is good peelability, heat resistance and cleaning removability after polishing of the rear surface of the wafer. A layered body for processing a rear surface of a wafer opposite to a circuit surface of the wafer, the layered body being a temporary adhesive loaded between a support and circuit surface of the wafer and including an adhesive layer (A) that includes a polyorganosiloxane to be cured by a hydrosilylation reaction and is releasably bonded, and a separation layer (B) includes a polyorganosiloxane and is releasably bonded, in which the polyorganosiloxane forming the separation layer (B) is a polyorganosiloxane containing a siloxane unit of RRSiO2/2 (provided that each R is bonded to a silicon atom as a Si—C bond), and at least one R is an aralkyl group, epoxy group, or phenyl group. Methods for producing and separating these layered bodies and composition for forming the separation layer.

Abstract: An adhesive sheet is provided that is capable of inhibiting scraping up of an adhesive in the dicing step, does not cause chip detachment during dicing processing, facilitates picking up, and does not readily develop adhesive transfer. According to the present invention, an adhesive sheet is provided that comprises a substrate film and an adhesive layer laminated on the film, wherein the adhesive layer contains 100 parts by mass of a (meth)acrylate copolymer, from 5 to 250 parts by mass of a photopolymerizable compound, from 20 to 160 parts by mass of a softener, from 0.1 to 30 parts by mass of a curing agent, and from 0.1 to 20 parts by mass of a photopolymerization initiator, and the photopolymerizable compound has a weight average molecular weight from 40,000 to 220,000.

Abstract: A sample transfer system includes a sample-mounting member mounting a sample thereonto; and a sample-moving device lifting the sample to move the sample between the sample-mounting member and another location, wherein the sample-mounting member comprises: a first predetermined sample-mounting region mounting the sample; and a recessed part on or around a side of the first predetermined sample-mounting region, wherein the sample-moving device comprises a first sample-holding device, the first sample-holding device comprising: a sample-holding surface facing the sample to be lifted; a first contact member contacting with part of the sample; and a movement mechanism moving the first contact member in a direction along the sample-holding surface, and wherein part of the contact member enters the recessed part when the first sample-holding device is brought in proximity to the first predetermined sample-mounting region, the part of the contact member moving within the recessed part by operating the movement mechan

Abstract: A sample-holding device for holding and lifting a sample includes a sample-holding surface facing the sample; and a positioning member provided at a peripheral part of the sample-holding surface, the positioning member comprising a contact part having an outward-facing part on a back side thereof; a first rounded or chamfered end; and a second rounded or chamfered end, wherein the contact part contacts with part of the sample when the sample is held or when the sample is off-point, wherein the first end is an end of a section comprising the contact part or a part smoothly continuing from the contact part, the end being on a distant side from the sample-holding surface, and the second end is an end of the outward-facing part, the end being located on a tipping side of the outward-facing part.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a dielectric layer is formed on the substrate, and an opening is formed in the dielectric layer, in which the dielectric layer includes a damaged layer adjacent to the opening. Next, a dielectric protective layer is formed in the opening, a metal layer is formed in the opening, and the damaged layer and the dielectric protective layer are removed.

Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above the substrate, a first dielectric layer formed on the first capping layer; a second capping layer formed on the first dielectric layer; a second dielectric layer formed on the second capping layer; a plurality of conducting lines separately formed on the substrate; a third capping layer formed on the conducting lines and the second dielectric layer; and several nano-gaps formed between the adjacent conducting lines, and the nano-gaps being formed in the second dielectric layer, or further extending to the second capping layer or to the first capping layer. The nano-gaps partially open one of the second and first dielectric layers, or the nano-gaps expose the first capping layer or the second capping layer.

Abstract: A method of manufacturing an SOI wafer, including (a) forming a thermal oxide film on an SOI layer of an SOI wafer by a heat treatment under an oxidizing gas atmosphere, (b) measuring thickness of the SOI layer after forming the thermal oxide film, (c) performing a batch cleaning, wherein an etching amount of SOI layer is adjusted depending on thickness of the SOI layer measured in step (b) such that thickness of the SOI layer is adjusted to be thicker than a target value after etching, (d) measuring thickness of the SOI layer after batch cleaning, (e) performing a single-wafer cleaning, wherein an etching amount of the SOI layer is adjusted depending on thickness of the SOI layer measured in step (d) such that thickness of the SOI layer is adjusted to be the target value after etching, and removing the thermal oxide film formed in step (a) before or after step (b).

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: A method of forming at least one lithography feature, the method including: providing at least one lithography recess on a substrate, the or each lithography recess having at least one side-wall and a base, with the at least one side-wall having a width between portions thereof; providing a self-assemblable block copolymer having first and second blocks in the or each lithography recess; causing the self-assemblable block copolymer to self-assemble into an ordered layer within the or each lithography recess, the ordered layer including at least a first domain of first blocks and a second domain of second blocks; causing the self-assemblable block copolymer to cross-link in a directional manner; and selectively removing the first domain to form lithography features of the second domain within the or each lithography recess.

Abstract: Provided are a method of manufacturing a porous body capable of easily manufacturing a porous body, a porous body, a method of manufacturing a device, a device, a method of manufacturing a wiring structure, and a wiring structure. A photocurable composition including a condensing gas and a polymerizable compound is applied to a substrate or a mold, the photocurable composition is sandwiched between the substrate and the mold and then the photocurable composition is irradiated with light to cure the photocurable composition, and the mold is released from a surface of the cured photocurable composition.

Abstract: A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

Abstract: In one embodiment of the present disclosure, a method for depositing metal in a feature on a workpiece is provided. The method includes electrochemically depositing a second metal layer on a first metal layer on a workpiece having at least two features of two different sizes in a dielectric layer, wherein the second metal layer is a copper layer and wherein the first metal layer includes a metal selected from the group consisting of cobalt and nickel, wherein the first metal layer completely fills the smallest feature but does not completely fill the largest feature.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: Embodiments provided are a through electrode that can be manufactured by a method not including the step of removing a side-wall insulating film formed at the bottom part of the through hole and so having improved electrical characteristics and mechanical reliability and a manufacturing method thereof as well as a semiconductor device and a manufacturing method thereof. A through electrode is disposed in a semiconductor substrate, and includes: a conductive layer; a side-wall insulating film that is disposed between the conductive layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1), and a tubular semiconductor layer disposed between the conductive layer and the semiconductor substrate, the semiconductor layer including a same material as the material of the semiconductor substrate.

Abstract: A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall.

Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.

Abstract: A semiconductor substrate (1) is provided with integrated circuits. Dicing trenches (7) are formed in the substrate (1) between the integrated circuits, a polyimide layer (8) spanning the trenches (7) is applied above the integrated circuits, a tape layer (14) is applied above the polyimide layer (8), and a layer portion of the substrate (1) is removed from the substrate side (17) opposite the tape layer (14), until the trenches (7) are opened and dicing of the substrate (1) is thus effected. The polyimide layer (8) is severed in sections (18) above the trenches (7) when the tape layer (14) is removed. The semiconductor chip is provided with a cover layer (11) laterally confining the polyimide layer (8) near the trenches (7), in particular for forming breaking delimitations (9).

Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.

Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract: In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.

Abstract: A semiconductor device may include a substrate, a p-channel device, and an n-channel device. The p-channel device may include a first metal member, a first dielectric layer positioned between the substrate and the first metal member, a first barrier layer positioned between the first dielectric layer and the first metal member, a first first-type work function layer directly contacting the first barrier layer and positioned between the first barrier layer and the first metal member, and a first second-type work function layer directly contacting both the first first-type work function layer and the first metal member. The n-channel device may include a second metal member, a second dielectric layer positioned between the substrate and the second metal member, and a second second-type work function layer directly contacting both the second dielectric layer and the second metal member.

Abstract: The present disclosure provides a method for fabricating a fin field-effect transistor (fin-FET), including: providing a substrate having a plurality of discrete fin structures thereon; forming a chemical oxide layer on at least a sidewall of a fin structure; forming a doped layer containing doping ions on the chemical oxide layer; and annealing the doped layer such that the doping ions diffuse into the fin structure to form a doped region.

Abstract: Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.

Abstract: A method of inspecting a substrate includes irradiating light onto a substrate that has experienced a first process, obtaining spectral data of the light reflected from the substrate, detecting a defect region of the substrate from the spectral data, and extracting a first defect site that occurred in or during the first process from the defect region. Extracting the first defect site includes establishing an effective area where the first process affects the substrate, and extracting a superimposed area that is overlapped with the effective area from the defect region. The superimposed area is defined as the first defect site.

Abstract: The disclosure generally relates to methods for manufacturing a filled gap region or cavity between two surfaces forming a device microchip. In one embodiment, the cavity results from two surfaces, for example, a PCB and a chip or two chips. More specifically, the disclosure relates to a method of manufacture and the resulting apparatus having porous underfill to enable rework of the electrical interconnects of a microchip on a multi-chip module. In one embodiment, the disclosure builds on the thermal underfill concept and achieves high thermal conductivity by the use of alumina fillers. Alternatively, other material such as silica filler particles may be selected to render the underfill a poor thermal conductive. In one embodiment, the disclose is concerned with reworkability of the material.