Patents Issued in July 13, 2017
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Publication number: 20170200660Abstract: A tester apparatus is provided. Slot assemblies are removably mounted to a frame. Each slot assembly allows for individual heating and temperature control of a respective cartridge that is inserted into the slot assembly. A closed loop air path is defined by the frame and a heater and cooler are located in the closed loop air path to cool or heat the cartridge with air. Individual cartridges can be inserted or be removed while other cartridges are in various stages of being tested or in various stages of temperature ramps.Type: ApplicationFiled: January 6, 2017Publication date: July 13, 2017Applicant: Aehr Test SystemsInventors: Jovan Jovanovic, Kenneth W. Deboe, Steven C. Steps
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Publication number: 20170200661Abstract: A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive bonding pad in the die region of the wafer and a wafer acceptance test (WAT) pad in the scribe-line region of the wafer. A top surface of the WAT pad is lower than a top surface of the conductive bonding pad.Type: ApplicationFiled: January 10, 2016Publication date: July 13, 2017Inventors: Tzung-Han LEE, Chun-Yi WU, Sheng-Yu YAN, Yi-Ting CHENG
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Publication number: 20170200662Abstract: A package includes: a semiconductor element; a case having an opening and housing the semiconductor element; and a lid having a rectangular parallelepiped shape and occluding the opening of the case. In the package, the lid is joined to an end portion of the opening of the case, and includes: a bent portion formed in a more interior position on the lid than a joint portion corresponding to a longitudinal side and along the joint portion corresponding to the longitudinal side, in a top view, among sides of the lid which are joined to the case; and a flat portion not including a bent portion formed in a more interior position on the lid than a joint portion corresponding to a short side and along the joint portion corresponding to the short side, in the top view, among the sides of the lid which are joined to the case.Type: ApplicationFiled: January 13, 2017Publication date: July 13, 2017Inventors: Tomohiro MITANI, Takashi UCHIDA, Georg REFCIO
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Publication number: 20170200663Abstract: A carbon-coated thermal conductive material includes a coating layer comprising amorphous carbon on a surface of a thermal conductive material, wherein the thermal conductive material comprises a metal oxide, a metal nitride, a metal material, or a carbon-based material having a thermal conductivity of 10 W/mK or greater, the amorphous carbon is derived from carbon contained in an oxazine resin, a ratio of a peak intensity of a G band to a peak intensity of a D band is 1.0 or greater when the amorphous carbon is measured by Raman spectroscopy, an average film thickness of the coating layer is 500 nm or less, and a coefficient of variation (CV value) of a film thickness of the coating layer is 15% or less.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Applicant: SEKISUI CHEMICAL CO., LTD.Inventors: Ren-de Sun, Shoji Nozato, Akira Nakasuga, Masanori Nakamura
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Publication number: 20170200664Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.Type: ApplicationFiled: January 12, 2016Publication date: July 13, 2017Inventors: PEI-HAW TSAO, CHIEN-JUNG WANG
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Publication number: 20170200665Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Inventors: Alan B. BOTULA, Max L. LIFSON, James A. SLINKMAN, Theodore G. VAN KESSEL, Randy L. WOLF
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Publication number: 20170200666Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.Type: ApplicationFiled: October 13, 2016Publication date: July 13, 2017Applicant: Infineon Technologies AGInventors: Wolfram Hable, Martin Gruber, Juergen Hoegerl
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Publication number: 20170200667Abstract: Methods for fabrication of thermal interposers, using a low stress photopatternable silicone are provided, for use in production of electronic products that feed into packaging of LEDs, logic and memory devices and other such semiconductor products where thermal management is desired. A photopatternable silicone composition, thermally conductive material and a low melting point compliant solder form a complete semiconductor package module. The photopatternable silicone is applied on a surface of a wafer and selectively radiated to form openings which provided user defined bondline thickness control. The openings are then filled with high conductivity pastes to form high conductivity thermal links. A low melting point curable solder is then applied where the solder wets the silicone as well as the thermally conductive path that leads to low thermal contact resistance between the structured z-axis thermal interposer and the heat sink and/or substrate which can be a wafer or PCB.Type: ApplicationFiled: May 29, 2015Publication date: July 13, 2017Applicant: Dow Corning CorporationInventors: RANJITH SAMUEL JOHN, HERMAN MEYNEN, CRAIG R. YEAKLE
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Publication number: 20170200668Abstract: [Object] Provided are a flow channel member having high heat-exchange efficiency in addition to high corrosion resistance and high mechanical characteristics, a heat exchanger including the flow channel member, and a semiconductor module including the flow channel member. [Solution] A flow channel member 10 according to the present invention includes a ceramic substrate 1, a flow channel 3 inside the ceramic substrate 1 through which a fluid flows, and multiple protrusions 2 on an outer surface of the substrate 1. The flow channel member 10 according to the present invention having such a configuration has high heat-exchange efficiency in addition to high corrosion resistance and high mechanical characteristics.Type: ApplicationFiled: May 25, 2015Publication date: July 13, 2017Inventors: Masayuki MORIYAMA, Yuusaku ISHIMINE, Kazuhiko FUJIO, Keiichi SEKIGUCHI
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Publication number: 20170200669Abstract: A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a supporting structure, the supporting structure being of a soluble type. A chip including a semiconductor body is mechanically coupled to the supporting structure. The sinterable material is sintered such that each preliminary contact region forms a corresponding sintered preliminary contact, and the chip and the plurality of preliminary contact regions are coated with a dielectric coating region, and the supporting structure is removed using a jet of liquid.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Applicant: STMicroelectronics S.r.l.Inventor: Fulvio Vittorio Fontana
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Publication number: 20170200670Abstract: Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.Type: ApplicationFiled: January 23, 2017Publication date: July 13, 2017Inventors: Conor Rafferty, Mitul Dalal
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Publication number: 20170200671Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.Type: ApplicationFiled: March 23, 2017Publication date: July 13, 2017Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Publication number: 20170200672Abstract: The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: Nuwan S. Jayasena, David A. Roberts
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Publication number: 20170200673Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
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Publication number: 20170200674Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.Type: ApplicationFiled: January 12, 2016Publication date: July 13, 2017Inventors: Sunil Kumar Singh, Shesh Mani Pandey
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Publication number: 20170200675Abstract: Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.Type: ApplicationFiled: January 11, 2017Publication date: July 13, 2017Inventors: Deokyoung JUNG, Kwangjin MOON, Byung Lyul PARK, Jin Ho AN
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Publication number: 20170200676Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.Type: ApplicationFiled: December 19, 2016Publication date: July 13, 2017Inventors: Da Woon JEONG, Sung-Hun LEE, Seokjung YUN, Hyunmog PARK, JoongShik SHIN, Young-Bae YOON
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Publication number: 20170200677Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Applicant: INTEL CORPORATIONInventors: Qing Ma, Johanna M. Swan, Robert Starkston, John S. Guzek, Robert L. Sankman, Aleksandar Aleksov
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Publication number: 20170200678Abstract: The present invention provides a flexible substrate for packaging and a package. The flexible substrate for packaging includes a bendable region provided in a central region of the flexible substrate; chips provided at both sides of the bendable region and at both ends of the flexible substrate, respectively; and a wire provided to be connected between the chips and to pass through the bendable region. A portion of the wire corresponding to the bendable region is provided with an anti-stress structure, and the anti-stress structure is configured to release a tensile resistance and a compressive resistance when the bendable region is bent.Type: ApplicationFiled: February 16, 2016Publication date: July 13, 2017Inventors: Bo ZHANG, Wenbo LI
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Publication number: 20170200679Abstract: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.Type: ApplicationFiled: October 31, 2016Publication date: July 13, 2017Inventors: John A. ROGERS, Dahl-Young KHANG, Yugang SUN, Etienne MENARD
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Publication number: 20170200680Abstract: Disclosed is a wafer marking method using a laser for marking a wafer having processing tape attached thereto. The disclosed laser marking method comprises the steps of: penetrating a 532-nm wavelength laser beam through the processing tape attached to one side of the wafer; and performing marking on the one side of the wafer by moving the 532-nm wavelength laser beam at a predetermined velocity, wherein the 532-nm wavelength laser beam has a frequency of 8 kHz to 40 kHz, and an output power of 0.8 W to 2 W.Type: ApplicationFiled: August 11, 2014Publication date: July 13, 2017Applicant: EO TECHNICS CO., LTD.Inventors: Chun Hoe GU, Soo Young KIM, Sung Beom JUNG
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Publication number: 20170200681Abstract: The present application provides a manufacturing method of a display panel and a bonding cutting device, belongs to a field of display technology, and can solve a problem of low production efficiency of display panels in the prior art. The display panel comprises a display region and a bonding region, the manufacturing method of the present application comprises steps of: cutting a display motherboard along cutting lines, and simultaneously bonding flexible circuit boards to bonding regions of the cut display panels corresponding thereto. The manufacturing method of the display panel in the present application is suitable for mass production of display panels.Type: ApplicationFiled: February 16, 2016Publication date: July 13, 2017Inventors: Quanhua HE, Hao ZHANG, Lingyun SHI
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Publication number: 20170200682Abstract: A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer.Type: ApplicationFiled: January 7, 2016Publication date: July 13, 2017Inventors: I-Chia LIN, Chieh-Chen FU, Kuo Hsien LIAO, Cheng-Nan LIN
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Publication number: 20170200683Abstract: A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.Type: ApplicationFiled: November 17, 2016Publication date: July 13, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: JONG-SOO KIM, Sam-jong Choi, Sue-ryeon Kim, Tae-hyoung Koo, Hyun-hee Ju, Cheong-jun Kim, Ji-won You
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Publication number: 20170200684Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: Kenneth Rodbell, Davood Shahrjerdi
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Publication number: 20170200685Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Applicant: INTEL CORPORATIONInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
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Publication number: 20170200686Abstract: Disclosed are a semiconductor device and a manufacturing method thereof, which can easily increase the number of input/output pads by increasing regions for forming the input/output pads such that a redistribution layer is formed to extend up to an encapsulant.Type: ApplicationFiled: May 6, 2016Publication date: July 13, 2017Inventors: Sung Geun Kang, Ju Hoon Yoon, In Rak Kim
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Publication number: 20170200687Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Inventors: Ying-Ju Chen, Hsien-Wei Chen
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Publication number: 20170200688Abstract: A semiconductor package may be provided. The semiconductor package may include a substrate having a first surface over which bond fingers are arranged, the other surface facing away from the first surface and over which ball lands are arranged, and terminals which are respectively formed over the bond fingers. The semiconductor package may include a semiconductor chip disposed over the first surface of the substrate, and having an active surface facing the first surface and over which bonding pads are arranged. The semiconductor package may include bumps respectively formed over the bonding pads of the semiconductor chip, and including pillars and layers which are formed over first side surfaces of the pillars and are joined with the terminals of the substrate.Type: ApplicationFiled: April 26, 2016Publication date: July 13, 2017Inventors: Ki Young KIM, In Chul HWANG
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Publication number: 20170200689Abstract: A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir, and Pt. A concentration of the elements in total relative to the entire wire is 0.03% by mass or more and 2% by mass or less. When measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 50% or more among crystal orientations in the wire axis direction. An average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 ?m or more and 1.3 ?m or less.Type: ApplicationFiled: July 22, 2015Publication date: July 13, 2017Inventors: Takashi YAMADA, Daizo ODA, Teruo HAIBARA, Ryo OISHI, Kazuyuki SAITO, Tomohiro UNO
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Publication number: 20170200690Abstract: There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition.Type: ApplicationFiled: July 23, 2015Publication date: July 13, 2017Inventors: Takashi YAMADA, Daizo ODA, Ryo OISHI, Tomohiro UNO
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Publication number: 20170200691Abstract: A power module is fabricated, employing a clad metal that is formed by pressure-laminating aluminum and copper, in such a manner that the aluminum layer of the clad metal is bonded such as by ultrasonic bonding to the surface electrode of the power semiconductor chip and a wire is bonded to the copper layer thereof to establish electrical circuit. The clad metal is thermally treated in advance at a temperature higher than the operating temperature of the power semiconductor chip to sufficiently form intermetallic compounds at the interface between the aluminum layer and the copper layer for the intermetallic compounds so as not to grow in thickness after the bonding processes.Type: ApplicationFiled: October 9, 2015Publication date: July 13, 2017Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Junji FUJINO, Yoshihisa UCHIDA, Shohei OGAWA, Soichi SAKAMOTO, Tatsunori YANAGIMOTO
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Publication number: 20170200692Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.Type: ApplicationFiled: March 29, 2017Publication date: July 13, 2017Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20170200693Abstract: An electronic component includes a base, a laminate of a plurality of conductive metal material layers, and a solder layer made of Au—Sn alloy solder. The laminate is disposed on the base. The solder layer is disposed on the laminate. The laminate includes a surface layer made of Au as the conductive metal material layer constituting an outermost layer. The surface layer includes a solder layer-disposing region in which the solder layer is disposed and a solder layer-empty region in which the solder layer is not disposed. The solder layer-disposing region and the solder layer-empty region are spatially separated from each other.Type: ApplicationFiled: August 5, 2015Publication date: July 13, 2017Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Yoshimaro FUJII, Hiroshi OGURI, Akira SAKAMOTO, Tomoya TAGUCHI
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Publication number: 20170200694Abstract: A disclosed circuit arrangement includes a flexible substrate. A layer of pressure sensitive adhesive (PSA) is directly adhered to a first major surface of the substrate. One or more metal foil pads and electrically conductive wire are attached directly on a surface of the PSA layer. The wire has a round cross-section and one or more portions directly connected to the one or more metal foil pads with one or more weld joints, respectively. An electronic device is attached directly on the surface of the layer of PSA and is electrically connected to the one or more portions of the round wire by one or more bond wires, respectively.Type: ApplicationFiled: February 8, 2017Publication date: July 13, 2017Inventor: Robert Neuman
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Publication number: 20170200695Abstract: A method of processing a substrate that displays out-gassing when placed in a vacuum includes placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T1 and removing gaseous contamination emitted from the substrate until the out-gassing rate is determined by the diffusion of the substrate's contamination and thus essentially a steady state has been established. Afterwards, the temperature is lowered to a temperature T2 at which the diffusion rate of the substrate's contamination is lower than at T1. The substrate is further processed at the temperature T2 until the substrate has been covered with a film including a metal.Type: ApplicationFiled: March 6, 2017Publication date: July 13, 2017Inventors: Wolfgang Rietzler, Bart Scholte Van Mast
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Publication number: 20170200696Abstract: A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. A heat spreader is thermally coupled with the rear surface of the substrate, either directly or through an additional element overlying the rear surface. Additional contacts of the second microelectronic element may be coupled with contacts of the substrate through electrically conductive structure disposed beyond an edge surface of the first microelectronic element.Type: ApplicationFiled: January 19, 2017Publication date: July 13, 2017Inventor: Belgacem Haba
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Publication number: 20170200697Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate has an active region. The semiconductor substrate is doped with first dopants with a first-type conductivity. The active region is adjacent to the first surface and doped with second dopants with a second-type conductivity. The semiconductor device structure includes a doped layer over the second surface and doped with third dopants with the first-type conductivity. A first doping concentration of the third dopants in the doped layer is greater than a second doping concentration of the first dopants in the semiconductor substrate. The semiconductor device structure includes a conductive bump over the doped layer.Type: ApplicationFiled: January 12, 2016Publication date: July 13, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min-Feng KAO, Dun-Nian YAUNG, Jen-Cheng LIU, Jeng-Shyan LIN, Hsun-Ying HUANG
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Publication number: 20170200698Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Applicant: Global Foundries Inc.Inventors: Richard S. Graf, Sebastian T. Ventrone
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Publication number: 20170200699Abstract: A semiconductor structure in the form of a die comprises a silicon-containing core having a first surface, an opposite second surface and a peripheral edge surface. A circuit structure on the first surface is circumscribed by a peripheral crackstop structure which stops short of the second surface, thereby leaving an accessible portion of the peripheral edge surface free of the crackstop structure. One or more angular or orthogonal edge connector through-silicon conductive vias (“edge connector TSVs”) connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure. A method of making the structure includes forming the edge connector TSVs in the silicon wafer from which the semiconductor structures, i.e., dies, are cut.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: Stephen P. Ayotte, Glen E. Richard, Timothy M. Sullivan
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Publication number: 20170200700Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.Type: ApplicationFiled: August 11, 2015Publication date: July 13, 2017Applicant: Massachusetts Institute of TechnologyInventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
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Publication number: 20170200701Abstract: A method of fabricating a 3D fan-out structure for an integrated circuit device includes providing a substrate carrier having first and second opposing surfaces and an aperture extending between the first and second surfaces. A first semiconductor die is bonded to the first surface of the substrate carrier such that the first die covers the aperture of the substrate carrier. An encapsulant and a second die are deposited within the aperture of the substrate carrier such that an active surface of the second die is exposed and coplanar with the second surface of the substrate carrier. One or more redistribution layers are then applied on the second surface of the substrate carrier to form a 3D fan-out structure.Type: ApplicationFiled: November 18, 2016Publication date: July 13, 2017Inventors: Wei Gao, Zhiwei Gong, Dehong Ye
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Publication number: 20170200702Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.Type: ApplicationFiled: January 11, 2017Publication date: July 13, 2017Inventors: Chih-Pin HUNG, Ying-Te OU, Pao-Nan LEE
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Publication number: 20170200703Abstract: To miniaturize metal columns. A semiconductor device includes a metal column (14) that extends in a stretching direction; a polymer layer (16) that surrounds the metal column from a direction crossing the stretching direction; and a guide (12) that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture (20) containing metal particles (22) and polymers (24) in a guide (12); and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer (16) that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column (14) that stretches in a stretching direction of the guide from the metal particles.Type: ApplicationFiled: March 3, 2017Publication date: July 13, 2017Applicant: TOHOKU UNIVERSITYInventors: Mitsumasa KOYANAGI, Tetsu TANAKA, Takafumi FUKUSHIMA, Kang-Wook LEE
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Publication number: 20170200704Abstract: A semiconductor device 10 includes: multi-layered substrates 12 each having a circuit board 12c; control terminals 14 whose one end is fixed on the circuit board 12c of each multi-layered substrate 12; a resin case 15 which has openings 20 and is arranged to cover the multi-layered substrates 12, through which openings 20 the other ends of the control terminals 14 extend outwardly; and resin blocks 18 which are each inserted into the openings 20 of the resin case 15 and press-fixes the control terminals 14 against the side walls of the respective openings 20. The control terminals 14 each have a low-rigidity portion 14j at a position that is further interior of the resin case 15 than a position where each control terminal 14 is in contact with the resin block 18 in the respective openings 20 of the resin case 15.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Inventor: Yoshihiro KODAIRA
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Publication number: 20170200705Abstract: A power device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.Type: ApplicationFiled: January 12, 2016Publication date: July 13, 2017Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Xiaotian Zhang, Shekar Mallikarjunaswamy, Zhiqiang Niu, Cheow Khoon Oh, Yueh-Se Ho
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Publication number: 20170200706Abstract: A light source module according to an embodiment includes: a flexible printed circuit board that has first and second pads; and a plurality of light emitting chips that are arranged on the first pads of the flexible printed circuit board, respectively, wherein the plurality of light emitting chips include a plurality of first arrays that are arranged in a first direction and second arrays that are arranged in a second direction that is different from the first direction, at least two of light emitting chips in each first array are connected to each other by the flexible printed circuit board, light emitting chips in each second array are electrically isolated from each other, the light source module further includes connection members, each of which is connected to at least one of the light emitting chips of the second array and a corresponding second pad of the flexible printed circuit board, and the connection members extend in the second direction.Type: ApplicationFiled: July 20, 2015Publication date: July 13, 2017Applicant: LG INNOTEK Co., Ltd.Inventor: Jung Oh Lee
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Publication number: 20170200707Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Applicant: The Board of Trustees of the University of IllinoisInventors: John A. ROGERS, Ralph NUZZO, Hoon-sik KIM, Eric BRUECKNER, Sang Il PARK, Rak Hwan KIM
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Publication number: 20170200708Abstract: Proposed is a light source comprising first and second LED light sources. Each of the first and second LED light sources have: a semiconductor diode structure adapted to generate light; and a light output section above the semiconductor diode structure adapted to output light from the semiconductor diode structure in a light output direction, the area of the light output section being less than the area of the semiconductor diode structure. The second LED light source is arranged above and at least partially overlapping the first LED light source with non-aligned light output sections with respect to the light output direction.Type: ApplicationFiled: July 17, 2015Publication date: July 13, 2017Inventors: Floris Maria Hermansz Crompvoets, Norbertus Antonius Maria SWEEGERS, Hugo Johan CORNELISSEN, Marc Andre DE SAMBER
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Publication number: 20170200709Abstract: A flexible display device is disclosed. In one aspect, the display device includes a flexible display panel including a display substrate, wherein the display substrate includes an active area for pixel circuits, an inactive area adjacent to the active area and having a pad area including a plurality of pad terminals, and a thin film encapsulation layer covering the active area. The display device also includes a display driver electrically connected to the pad terminals and a plurality of driving terminals each having a rounding unit. A conductive unit is configured to electrically connect the pad terminals to the respective driving terminals.Type: ApplicationFiled: January 10, 2017Publication date: July 13, 2017Inventors: Jonghwan Kim, Sangurn Lim