Abstract: Embodiments are directed to a computer implemented method of choreographic editing of multimedia and other streams. The method includes receiving, one or more multimedia clips. The multimedia clips are displayed to a user, who can then select one or more of the clips. The user creates one or more synchronization points. An embodiment automatically adjusts the selected multimedia clips using the synchronization points. Thereafter a finished media file is created.

Abstract: Various embodiments facilitate the creation and presentation of a virtual experience. In one embodiment, the virtual experience is assembled from user model data corresponding to a three-dimensional representation of a user, user movement data corresponding to at least one movement characteristic of the user, user voice data corresponding to at least one vocal characteristic of the user, environment data corresponding to a three-dimensional representation of a location, and event data corresponding to a captured event at the location. The virtual experience is a virtual recreation of the captured event at the location, with the three-dimensional representation of the user, the vocal characteristic of the user, and the movement characteristic of the user inserted into the captured event.

Abstract: A system for performing automatic cinemagraph creation is described herein. The system comprises a memory and a processor. The memory is configured to receive series of images. The processor is coupled to the memory. The processor is to segment the series of images, select the most fitting times and mask, and apply the times and masks to the series of images to generate a cinemagraph.

Abstract: The invention relates to a method for editing a media record in a terminal device of a cellular network, which editing means removing at least one portion of the original contents of the media record. The state of the editing is shown on the display of the terminal device with a pointer arrangement according to the invention. The invention also relates to a cellular network terminal device in which the method is utilized. In the terminal device the media record editing is controlled with a program application according to the invention.

Abstract: Embodiments of apparatuses, systems and methods for video creation, editing, and sharing for social media are described. In particular, the present embodiments include components for copying and pasting snippets of media from a first media file to a second media file at a desired location within the second media file. In a further embodiment, media snippets may be copied, cut, or pasted within a single media file. For example, in an embodiment, a snippet of video may be copied from a first video file, and pasted at a selected position within a timeline of a second video file. The media files may be pasted over each other completely. In another embodiment, audio may be pasted over existing video. In another embodiment video may be pasted over existing audio. In various alternative embodiments, the media snippet may be otherwise merged with the second media file.

Abstract: The invention provides a method for processing and analyzing forensic video data using a computer program, the method comprising the steps of recording the forensic video data; providing supplementary data related to the recorded video data, wherein the supplementary data may be provided from or input by a source external of the computer program, in particular a human, or wherein the supplementary data may be extracted from the forensic video data by the computer program in an initial analyzing step; analyzing the forensic video data by the computer program using the supplementary data; and displaying a part of the forensic video data, the displayed part being based on a result of the analyzing step.

Abstract: A hard disk drive carrier assembly includes a back panel, and a connection mechanism in physical communication with the back panel of the hard disk drive carrier assembly along a first surface of the connection mechanism. The connection mechanism includes guide pin extending away from a second surface of the connection mechanism. The guide pin to align the hard disk drive carrier assembly with a mid-plane module of an information handling system when the hard disk drive carrier assembly is inserted into a bay of the information handling system. A screw is in physical communication with the connection module to mount the connection mechanism onto the back panel. The screw includes a post, and is inserted through a hole in the connection mechanism and is connected to the back panel. A first diameter of the post is smaller than a second diameter of the hole.

Abstract: A disk drive includes a metal base that has a rectangular bottom wall and side walls formed on each side of the rectangular bottom wall, the side walls including a first side wall on a shorter side, a metal cover that is fixed to the metal base with a plurality of metal screws, including two screws disposed at opposite ends of the side wall, a gap being formed between an upper end of the first side wall and the metal cover, a magnetic disk disposed on the metal base, at a position offset from a center of the metal base in a longitudinal direction towards the first side wall, and a head. The first side wall and the metal cover are electrically connected at an intermediate position of the first side wall between said opposite ends of the first side wall.

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading data from a plurality of first memory cells of a rewritable non-volatile memory module; estimating an error bit occurrence rate of the data before performing a first decoding process on the data; and performing the first decoding process on the data by using a first decoding parameter according to the estimated error bit occurrence rate, wherein the first decoding parameter corresponds to a strict level for locating an error bit in the first decoding process. As a result, a decoding efficiency of the memory storage device can be improved.

Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.

Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.

Abstract: A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

Abstract: A static random access memory (SRAM) includes a bit cell that receives an operating voltage and a reference voltage, and includes a p-type pass gate. A bit information path is connected to the bit cell by the p-type pass gate, and a pre-discharge circuit is connected to the bit information path. The pre-discharge circuit includes an n-type transistor that discharges the bit information path to the reference voltage.

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.

Abstract: A nonvolatile memory device comprises: a nonvolatile memory; a resistance-time converter that outputs an end signal at timing according to a resistance value of the nonvolatile memory; and a time-digital converter that measures the time from input of a start signal to input of the end signal and converts the measured time into a digital value. The time-digital converter includes: a ring delay circuit that includes delay elements connected in a ring configuration; a counter circuit that counts the number of times of a rising edge or a falling edge in output of one of the delay elements; a first memory circuit that stores, based on the end signal, outputs of the delay elements as first data; and a second memory circuit that stores, based on the end signal, a count value of the counter circuit as second data.

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

Abstract: Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: A nonvolatile memory (NVM) cell includes a selection transistor configured to have a selection gate terminal coupled to a word line and a source terminal coupled to a source line, a cell transistor configured to have a floating gate electrically isolated, a drain terminal coupled to a bit line and sharing a junction terminal with the selection transistor, a first coupling capacitor disposed in a first connection line coupled between the word line and the floating gate, and a P-N diode and a second coupling capacitor disposed in series in a second connection line coupled between the word line and the floating gate. An anode and a cathode of the P-N diode are coupled to the second coupling capacitor and the word line, respectively. The first and second connection lines are coupled in parallel between the word line and the floating gate.

Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.

Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.

Abstract: An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described.

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Abstract: Systems and methods are provided to detect a developed bad word-line of a flash memory. Embodiments provide an improved Background media scan (BGMS) process that can predict at the end of a block read if a word-line will potentially become bad with the use of the flash memory. Accordingly, data from the potentially bad block can be recovered and the block can be retired. The embodiments can minimize the need for the expensive chip-kill method.

Abstract: A system for generating a source of neutrons from a thermonuclear fusion reaction includes a reaction chamber and a number of particle beam emitters. The reaction system has at least four particle beam emitters supported spatially around oriented toward a common focal region of the reaction chamber for directing the plurality of plasma beams that are spatially symmetrical in three dimensional space. Each of the plasma beams are directed towards a plasma region in the geometric center. A stable collapse of the plasma region permits a controllable and sufficiently long confinement time, which in combination with necessary temperature and density conditions may ignite and sustain fusion reactions and achieve a net energy output. Optionally, laser beams or other input energy devices may also be oriented around and toward the common focal region to direct high-energy laser beams at the plasma ball to assist with instigation of the fusion reaction.

Abstract: The fusion reactor of the invention comprises a plurality of elongated triangular electrodes aligned in a cylindrical shape to form an axially symmetric containment geometry. The electrodes are separated by means of electrical insulator preferably pure swept Quartz (SiO2). The Triangular electrodes, are made out of very high electro conductive, high strength, heat resistant, radiation resistant and neutrons moderating material such as thorium carbide, uranium carbide or silicon carbide or the like which is preferably made by ceramic powder metallurgy process. Each electrode includes a cooling structure or flow channel formed in the internal structure allowing for a cooling fluid for extracting heat caused by plasma and nuclear reactions. The acceleration channels electrodes of the fusion reactor are of triangular shape and are protected with a continuously changing protective film or layer of high electro-conductive fissile or fertile material such as thorium carbide or uranium carbide.

Abstract: A power system can connect to a nuclear reactor through a standardized connection. The standardized connection is configured so that the nuclear reactor may be designed independently of the power system. Systems include a reactor core in fluid communication with a heat exchanger. A fluid loop passes through the heat exchanger. The system includes an output and inlet manifolds at the ends of the fluid loop, terminating in ports that include a standardized connection mechanism. When the secondary system is coupled to the connection mechanism, the fluid loop and the secondary system define a distal loop. A working fluid can then flow through the distal loop and transfer heat from the reactor core to the secondary system.

Abstract: A molten salt reactor comprising a reactor vessel and a molten salt contained within the reactor vessel. There is a corrosion reduction unit configured to process the molten salt to maintain an oxidation reduction ratio, (E(o)/E(r)), in the molten salt at a substantially constant level, wherein E(o) is an element (E) at a higher oxidation state (o) and E(r) is the element (E) at a lower oxidation state (r).

Abstract: A method for in-situ measuring of a liquidus temperature of a supply of the molten salt, includes withdrawing a sample of the molten salt from the supply, placing it into a sample container, and cooling the sample of the molten salt from a first temperature above the liquidus temperature of the molten salt to a second temperature at which at least a portion of the sample of the molten salt solidifies. The method includes taking a plurality of temperature measurements of the sample of the molten salt during cooling of the sample and determining the liquidus temperature of the molten salt from the measurements. The sample of the molten salt is heated from the second temperature to the first temperature and returned to the supply of the molten salt.

Abstract: A fuel pellet visual inspection device for manufacturing a nuclear fuel rod improves convenience and workability of visual inspection of a plurality of pellets by simultaneously turning over the pellet. The fuel pellet visual inspection device for manufacturing a nuclear fuel rod includes: a rotary shaft; a pair of seats hinged to the hinge shaft, arranged at both sides from the rotary shaft, and seated with a tray thereon; and a dust-collecting unit disposed under the pair of seats and collecting dust scattered from pellets.

Abstract: The present disclosure relates to a radiographic shield incorporating a radiographic shutter mechanism, and a protective jacket for a radiographic device. The radiographic shutter mechanism includes machined tungsten components which in some embodiments, includes a jigsaw puzzle type interconnection, the radiographic shield includes an S-shaped passageway in combination with the radiographic shutter mechanism. The protective jacket allows for various mounting configurations, such as integrated SCAR mounting configurations, including a ratchet snap configuration.

Abstract: The group of inventions relates to constructing structures, such as the buildings of nuclear power plants, which are erected from monolithic blocks or slabs made of concrete or reinforced concrete. A block or a slab contains a built-in container with components for the sorption extraction, from water, of radionuclides or toxic substances. The container has elements for feeding-in contaminated water and for evacuating treated water. An erection method includes building a structure using the said blocks or slabs. A method for manufacturing a building block or slab includes forming a body out of concrete, embedding into same at least one container having water-treatment components, and having fittings or flanges for feeding-in contaminated water and for evacuating treated water. The invention provides for safe operations when erecting structures, and prevents the spread of radionuclides beyond the boundaries of a structure.

Abstract: The invention relates to a radioisotope generator (1) comprising an eluent reservoir (2) and a chromatographic column (3) connected to one another by a first eluent duct (4), characterized in that it comprises a second duct (7) and a valve (8) connected said second duct (7) to the first eluent duct and the first eluent duct, said valve (8) having a first position where the second duct (7) communicates with the first eluent duct (4) and a second position where the second duct (7) communicates with the first eluent duct (4), said second duct (7) having a bypass segment (9) for a predetermined eluent volume.

Abstract: A curved radiographic detector has electromagnetic radiation sensitive elements disposed in a two-dimensional array. A curved housing encloses the two-dimensional array of radiation sensitive elements and includes a layer of aligned carbon nanotubes on a surface thereof.

Abstract: Noble metal-coated nanostructures and related methods are disclosed. According to an aspect, a nanostructure may include a structure comprising a base metal. As an example, the structure may be a nanowire. In a more specific example, the structure may be a copper nanowire or a nanowire made of a base metal such as nickel, tin, indium, zinc, the like, or combinations thereof. The base metal structure may be coated with a noble metal that conformally covers the base metal structure. Example noble metals include, but are not limited to, ruthenium, rhodium, palladium, silver, iridium, platinum, and gold. The coating may be made of one or more of the noble metals along with other materials.

Abstract: An insulated wire having an insulating coat layer on the conductor outer peripheral surface having a rectangular cross-sectional shape and also having a long side, a short side, and a corner portion with a curvature radius Rc, wherein a thickness t1 of the insulating coat layer covered on the surface, and which layer includes a long side, a thickness t2 of the insulating coat layer covered on the surface, and which layer includes a short side, and a corner portion thickness t3 of the insulating coat layer satisfy formula (1): t3/{(t1+t2)/2}?1.2 ??Formula (1) wherein the t1 and t2 are each independently from 20 ?m to 50 ?m, and wherein a ratio of the conductor cross-sectional area Sc to the insulated wire cross-sectional area Sw satisfies formula (2) 1.0>Sc/Sw?0.8; ??Formula (2) as well as a coil and an electric or electronic equipment using the same.

Abstract: A feedthrough assembly and methods of making the feedthrough assembly are shown. A feedthrough assembly including a ferrule disposed about an insulator and having an outer surface and a first aperture defined by an inner surface, wherein the first aperture is sized and shaped to include a reservoir for a braze material, the reservoir including a base, the base having a width sized to accommodate a preform of the braze material, and at least two ledges formed by the inner surface, each ledge having a first surface facing inwardly toward the insulator and a second surface facing upwardly is shown. Methods of making the feedthrough assembly including such a ferrule are shown.

Abstract: A method for manufacturing a sheet of positive temperature coefficient (PTC) material includes providing a PTC material, grinding the PTC material into a powder, and inserting the ground PTC material into a press. The ground PTC material is compressed within the press until the PTC material defines a planar shape. The PTC material is then removed from the press to thereby provide a PTC sheet.

Abstract: In certain embodiments, a method comprises ablating, by a laser set to a first power level, a first area of a polyimide base substrate and forming, by ablating the first area of the polyimide base substrate, a first carbonaceous material film comprising a first specific resistive value. The method further comprises ablating, by the laser set to a second power level, a second area of the polyimide base substrate and forming, by ablating the second area of the polyimide base substrate, a second carbonaceous material film comprising a second specific resistive value. A tapered resistive material is produced by forming the first carbonaceous material film comprising the first specific resistive value and the second carbonaceous material film comprising the second specific resistive value.

Abstract: A permanent magnet includes a stack of N patterns stacked immediately one above the other in a stacking direction, each pattern including an antiferromagnetic layer made of antiferromagnetic material, a ferromagnetic layer made of ferromagnetic material, the directions of magnetization of the various ferromagnetic layers of all the patterns all being identical to one another. At least one ferromagnetic layer includes a first sub-layer made of CoFeB whose thickness is greater than 0.05 nm, and a second sub-layer made of a ferromagnetic material different from CoFeB and whose thickness is greater than the thickness of the first sub-layer.

Abstract: An amorphous soft magnetic alloy of the formula (Fe1-?TM?)100-w-x-y-zPwBxLySiz TipCqMnrCus, wherein TM is Co or Ni; L is Al, Cr, Zr, Mo or Nb; 0???0.3, 2?w?18 at %, 2?x?18 at %, 15?w+x?23 at %, 1<y?5 at %, 0?z?4 at %; p, q, r, and s represents an addition ratio such that the total mass of Fe, TM, P, B, L and Si is 100, and 0?p?0.3, 0?q?0.5, 0?r?2, 0?s?1 and r+s>0; the composition fulfills one of the following conditions: L is Cr, Zr, Mo or Nb; or L is a combination of Al and Cr, Zr, Mo or Nb, wherein 0<Al?5 at %, 1?Cr?4 at %, 0<Zr?5 at %, 2?Mo?5 at %, and 2?Nb?5 at %; the alloy has a crystallization start temperature (Tx) which is 550° C. or less, a glass transition temperature (Tg) which is 520° C. or less, and a supercooled liquid region represented by ?Tx=Tx?Tg, which is 20° C. or more.

Abstract: An amorphous alloy magnetic core including a layered body in which amorphous alloy thin strips are layered one on another, the layered body having one end face and another end face in a width direction of the amorphous alloy thin strips, an inner peripheral surface and an outer peripheral surface orthogonal to a layering direction of the amorphous alloy thin strips, and a hole passing through from a part of the one end face as a starting point, the width direction corresponding to a depth direction of the hole.

Abstract: A superconducting magnet device includes a vacuum container having a tubular barrel portion; a magnet assembly including a superconducting coil, a refrigerant tank, and a radiation shield, the magnet assembly being housed in the vacuum container; a supporting block fixed to the barrel portion and protruding beyond the barrel portion to the inside of the vacuum container; and a connecting portion which connects the magnet assembly and the supporting block to each other such that the magnet assembly is spaced apart from the barrel portion within the vacuum container. The connecting portion has thermal conductivity lower than thermal conductivity of the supporting member. The supporting member receives weight of the magnet assembly via the connecting portion while protruding inwardly beyond at least an outer circumference surface of the radiation shield of the magnet assembly.

Abstract: In a common mode noise filter, first coil (12) includes first coil conductor (16) and second coil conductor (17) with spiral shapes. Second coil (13) includes third coil conductor (18) and fourth coil conductor (19) with spiral shapes. First coil conductor (16), third coil conductor (18), second coil conductor (17), and fourth coil conductor (19) are placed in this order from above. First metal layer (14) configured to be connected to a ground is provided above first coil conductor (16).