Abstract: A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.

Abstract: A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a protective layer over a portion of at least one material line, the at least one protected material line and at least one unprotected material line having a same critical dimension, oxidizing the at least one unprotected material line to increase the critical dimension compared to the first critical dimension of the at least one protected material line, and etching at least a portion of the oxidized unprotected material line so that the etched critical dimension of the at least one etched material line is different from the first critical dimension of the at least one protected material line.

Abstract: A method of self-aligned spacer formation is described. According to one embodiment of the invention, a substrate processing method is provided, where the method includes forming a sacrificial film over a substrate, creating a pattern in the sacrificial film, conformally depositing a first spacer layer over the patterned sacrificial film, removing horizontal portions of the first spacer layer while substantially leaving vertical portions of the first spacer layer, and selectively depositing a second spacer layer on the first spacer layer.

Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.

Abstract: Embodiments of the invention provide a substrate processing method for bottom-up formation of a film in a recessed feature. According to one embodiment, the method includes providing a substrate containing a first layer and a second layer on the first layer, the second layer having a recessed feature extending through the second layer, and depositing a non-conformal mask layer on the substrate, where the mask layer has an overhang at an opening of the recessed feature. The method further includes removing the mask layer from a bottom of the recessed feature, while maintaining at least a portion of the overhang at the opening, selectively depositing a film on the bottom of the recessed feature, and removing the mask layer overhang from the substrate. The processing steps may be repeated at least once until the film has a desired thickness in the recessed feature.

Abstract: Manufacturing of a device to connect at least one nano-object to an external electrical system, comprising a support provided with a semiconducting layer (4) in which the first doped zones (8a, 8b) are formed at a spacing from each other, an external electrical system (SEE) being connectable to the first doped zones, each first doped zone (8a, 8b) being in contact with a second doped zone (12a, 12b) on which a portion of the nano-object is located, the second doped zones (12a, 12b) being separated from each other and with a thickness (e2) less than the thickness (e1) of the first doped zones (FIG. 1).

Abstract: The present invention relates to an improved composition for ion implantation. A dopant source comprising GeF4 and an assistant species comprising CH3F is provided, wherein the assistant species in combination with the dopant gas can produces a Ge-containing ion beam current. The criteria for selecting the assistant species is based on the combination of the following properties: ionization energy, total ionization cross sections, bond dissociation energy to ionization energy ratio, and a certain composition.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having a dielectric layer formed on the substrate, where an opening is formed in the dielectric layer, and bottom of the opening exposes surface of the substrate. The method also includes forming a first metal layer over of the dielectric layer, where a temperature for forming the first metal layer is a first temperature. In addition, the method includes forming a second metal layer filling the opening, where a temperature for forming the second metal layer is a second temperature, and the second temperature is higher than the first temperature. Further, the method includes planarizing the second metal layer and the first metal layer until the top surface of the dielectric layer is exposed.

Abstract: Provided is a hydrogenation annealing method using a microwave, which performs hydrogenation annealing at a low temperature and with low power in a manufacturing process of a thin film transistor (TFT) for a display device. The hydrogenation annealing method is constituted by a loading step of loading a device requiring hydrogenation annealing into a chamber and an annealing step of irradiating a microwave having a frequency in an industrial scientific medical (ISM) band into the chamber into which the device is loaded. As hydrogenation annealing is performed at a low temperature by using the microwave for an oxide semiconductor TFT or LTPS having very large electron mobility, high integrated energy is transmitted to the device by the microwave, thereby implementing recoupling of hydrogen atoms which have been performed only at a high temperature, even at a low temperature.

Abstract: A patterns forming method begins with performing a lithography process on a photoresist film with a photomask having first apertures in a first mask region and second apertures in a second mask region to respectively form first main features and dummy features, on which the second mask region is located between the border of the photomask and the first mask region, and a size of each of the first apertures is greater than a size of each of the second apertures. Subsequently, a material is filled into the first main features to respectively form second main features and into the dummy features to seal the dummy features. Then, a substrate is etched to form patterned features by using the photoresist film having the second main features.

Abstract: A substrate processing apparatus includes: a substrate holding member configured to hold a plurality of substrates; a reaction tube configured to accommodate the substrate holding member and process the substrates; a processing gas supply system configured to supply a processing gas into the reaction tube; and an exhaust system configured to exhaust an internal atmosphere of the reaction tube. The reaction tube includes: a cylindrical portion; a gas supply area formed outside one side wall of the cylindrical portion and connected to the processing gas supply system; and a gas exhaust area formed outside the other side wall of the cylindrical portion opposed to the gas supply area and connected to the exhaust system. Each of the gas supply area and the gas exhaust area has an inner wall which partitions the interior of each of the gas supply area and the gas exhaust area into a plurality of spaces.

Abstract: A substrate processing method for removing an oxide film formed on the surface of a substrate includes modifying the oxide film into a reaction product by supplying a halogen element-containing gas and an alkaline gas onto the substrate accommodated in the interior of a processing chamber, and sublimating the reaction product by stopping the supply of the halogen element-containing gas into the processing chamber for removal from the substrate, wherein an internal pressure of the processing chamber in the sublimating is set to be higher than an internal pressure of the processing chamber in the modifying by supplying an inert gas into the processing chamber.

Abstract: A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder. The gate structure includes at least two ceramic or metal layers, and the gate dielectric material is made of a high-k dielectric material. A substrate having the gate structure and gate dielectric material formed thereon is disposed in the processing region, and the temperature of the substrate is maintained at about 60 degrees Celsius or higher. By etching the gate structure using fluorine radicals at a temperature greater or equal to 60 degrees Celsius, the at least two ceramic or metal layers have a flat cross sectional profile.

Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.

Abstract: A wiring board (1) includes an insulating substrate (11) having a cutout (12) opened in a main surface and a side surface of the insulating substrate (11), and an inner electrode (13) formed on an inner surface of the cutout (12). The inner electrode (13) includes a plurality of metal layers. The inner electrode (13) includes, as an intermediate layer, at least one metal layer (17b) selected from the group consisting of a nickel layer, a chromium layer, a platinum layer, and a titanium layer, and includes a gold layer as an outermost layer (17a). The metal layer (17b) is exposed at an outer edge portion of the inner electrode (13).

Abstract: A substrate processing system includes a chemical liquid preparation unit preparing a chemical liquid to be supplied to a substrate and a processing unit which supplies the chemical liquid, prepared by the chemical liquid preparation unit, to the substrate. The chemical liquid preparation unit supplies an oxygen-containing gas, containing oxygen gas, to a TMAH-containing chemical liquid, containing TMAH (tetramethylammonium hydroxide), to make the oxygen-containing gas dissolve in the TMAH-containing chemical liquid.

Abstract: The wafer processing system includes a rotatable wafer support member for supporting a wafer and a plurality of collections trays disposed about a peripheral edge of the wafer support member. The collection trays are arranged in a stacked configuration, each collection tray having an inner wall portion and an outer wall portion that converge to define a trough section for collecting fluid. The system includes a chamber exhaust outlet that is formed in the housing for venting gas from the interior of the housing outside of the collection trays and a chemical exhaust outlet that is formed in the housing for venting gas that flows through the collection chamber to the chemical exhaust outlet. The chemical exhaust outlet is fluidly isolated from the chamber exhaust outlet.

Abstract: A semiconductor processing apparatus is described that has a body with a wall defining two processing chambers within the body; a passage through the wall forming a fluid coupling between the two processing chambers; a lid removably coupled to the body, the lid having a portal in fluid communication with the passage; a gas activator coupled to the lid outside the processing chambers, the gas activator having an outlet in fluid communication with the portal of the lid; a substrate support disposed in each processing chamber, each substrate support having at least two heating zones, each with an embedded heating element; a gas distributor coupled to the lid facing each substrate support; and a thermal control member coupled to the lid at an edge of each gas distributor.

Abstract: A reticle container for containing a reticle including a base plate having one or more windows. Each of the windows can include mounting recess having a recess sidewall including an undercut defined therein. A transparent substrate can be disposed in the mounting recess and is retained therein by a retention member having an arcuate portion extending between a first end portion and a second end portion. At least the first end portion of the retention member can be positioned in the undercut defined in the recess sidewall such that the arcuate portion of the retention member contacts the transparent substrate to retain the transparent substrate in the mounting recess.

Abstract: A front opening wafer container with a forward and rearward sets of stacked V-shaped wafer edge receiving portions, the rearward set part of a wafer shelf component and comprising a thin film of PBT preformed and overmolded with a polycarbonate. The sets of stacked V-shaped wafer edge receiving portions providing between-shelf seating positions above on-shelf seating positions. The PBT providing a low friction sliding engagement surface for the wafer edges thereby providing uniform and consistent dropping of wafers from the between shelf position to the on-shelf position when the door of the wafer container is removed.

Abstract: A substrate container includes a casing, a rack, a lid, a lid holder, and a substrate separating mechanism. The casing has on its front face an opening. The substrate separating mechanism has a contact part that directly contacts substrates. The contact part is movable relative to the lid holder. The lid moves forward to the opening, and the contact part moves backward relative to the lid holder, whereby the lid holder holds ends of the substrates. The lid moves backward from the opening, and the contact part moves forward to the lid holder, whereby the substrate separating mechanism separates the substrates from the lid holder.

Abstract: A purge configurable wafer shipper. The container includes an enclosure portion with an open side or bottom, a door to sealing close the open side or bottom. One of the door and the container portion includes an opening formed in the enclosure to provide a fluid passageway from an interior of the wafer shipper to an exterior region. The opening may include a module receiving structure that defines the fluid passageway. A sealing member is included for insertion into the module receiving structure. The sealing member has a body portion including a support flange positioned proximate a lower portion of the body portion, a circumferential groove in the exterior surface of the body portion, and an O-ring positioned at least partially within the circumferential groove.

Abstract: An active substrate alignment system for an ion implanter, the system including a platen, a registration device adapted to selectively move a substrate engagement surface disposed adjacent the platen for limiting movement of a substrate disposed on the platen, a camera configured to capture an image of the substrate before the substrate is disposed on the platen, and a controller in communication with the camera and the registration device, the controller configured to command the registration device to move the substrate engagement surface based on the image to limit movement of the substrate in a predetermined manner.

Abstract: Provided are a corrosion-resistant member in which, in a case where the corrosion-resistant member is used as a member for an electrostatic chuck, an adsorption force of the electrostatic chuck can be made to be strong when an electric field is applied and a residual adsorption force of the electrostatic chuck can be made to be weak when the application of the electric field is stopped; a member for an electrostatic chuck; and a process for producing a corrosion-resistant member. The corrosion-resistant member includes an oxide which includes samarium and aluminum and has a perovskite type structure. The member for an electrostatic chuck includes the corrosion-resistant member according to the present invention.

Abstract: A chuck useful for supporting a wafer during an edge bevel removal (EBR) process comprises a rotatable center hub having a plurality of support arms extending outwardly from the rotatable center hub, support pins on ends of the support arms, gas passages extending through upper surfaces of the support pins, and gas conduits in the support arms, the gas conduits configured to supply gas to the gas passages or apply a vacuum to the gas passages. The support arms can include alignment cams which are rotatable from an outer non-alignment position away from a periphery of the wafer to an inner alignment position at which the wafer is centered. To supply gas or apply a vacuum force to the gas outlets in the support pins, the rotatable center hub can have a gas inlet and a plurality of gas delivery ports in fluid communication with the gas delivery conduits in the support arms.

Abstract: Implementations described herein relate to pressure control for vacuum chuck substrate supports. In one implementation, a process chamber defines a process volume and a vacuum chuck support is disposed within the process volume. A pressure controller is disposed on a fluid flow path upstream from the vacuum chuck and a flow restrictor is disposed on the fluid flow path downstream from the vacuum chuck. Each of the pressure controller and flow restrictor are in fluid communication with a control volume of the vacuum chuck.

Abstract: A conveyance system includes a conveyance chamber including a second side wall opposite to a first side wall in a depth direction of the conveyance chamber. A robot is disposed in the conveyance chamber. The robot includes a body, a first arm, a second aim, and a hand. The body is disposed between the second side wall and a reference position in the depth direction. A second leading end of the second arm is positioned between a restricted position and the reference position in the depth direction when a first inter-axis direction and a second inter-axis direction are substantially perpendicular to the first side wall. A controller is connected to the robot to control the robot to limit entrance into an area between the first side wall and the restricted position in the depth direction.

Abstract: A substrate conveying robot has left and right arms having a common pivot axis line, an arm drive unit for driving the left and right arms, and a control unit for controlling the arm drive unit. A pulley ratio between a turning pulley, a first pulley, a second pulley, and a third pulley is set so that a moving locus of the substrate holding members when the first link member is rotated about the pivot axis line by the first drive portion so as to extend and contract the arm in a state that the turning pulley is fixed is substantially linear. Thereby, the moving locus of the substrate holding member when extending and contracting the arm can be substantially linear.

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

Abstract: Methods for void-free SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO2 film in the recessed features, and repeating the coating and exposing at least once to increase the thickness of the conformal SiO2 film until the recessed features are filled with SiO2 material that is void-free and seamless in the recessed features. In one example, the recessed features filled with SiO2 material form shallow trench isolation (STI) structures in a semiconductor device.

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

Abstract: High-chi diblock copolymers are disclosed whose self-assembly properties are suitable for forming hole and bar openings for conductive interconnects in a multi-layered structure. The hole and bar openings have reduced critical dimension, improved uniformity, and improved placement error compared to the industry standard poly(styrene)-b-poly(methyl methacrylate) block copolymer (PS-b-PMMA). The BCPs comprise a poly(styrene) block, which can optionally include repeat units derived from trimethylsilyl styrene, and a second block that can be a polycarbonate block or a polyester block. Block copolymers comprising a fluorinated linking group L? comprising 1-25 fluorines between the blocks can provide further improvement in uniformity of the openings.

Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.

Abstract: An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure, and forming a dielectric layer in the trenches. The etching method further includes etching the dielectric layer in the trenches by an etching process, and controlling at least an etching temperature of the etching process while a polymer is formed on side surface of the to-be-etched structure. During the etching process of the dielectric layer, the polymer undergoes a deposition stage and a removal stage. The deposition stage has a deposition rate of the polymer greater than an etch rate of the polymer, and the removal stage has the deposition rate of the polymer less than the etch rate of the polymer.

Abstract: In the present method, a substrate to be processed, having an interlayer insulation film, is prepared (step 1). The interlayer insulation film is subjected to dry etching, while using a mask layer, thereby forming recesses (step 2). Residue is removed by dry ashing (step 3). A coating is formed on the entire surface by means of a gas process using a coating compound gas, with a molecular structure having at one terminal a first substitution group that reacts with and bonds with the surface of the interlayer insulation film, and at the other terminal a second substitution group that is hydrophilic (step 4). The coating is removed by wet cleaning (step 5). Wiring is formed in the recesses (step 6).

Abstract: Provided are a method and an apparatus for manufacturing a semiconductor device. The method comprises: forming a first wiring layer on a base substrate; forming an interlayer dielectric layer on the first wiring layer, with contact holes being provided in the interlayer dielectric layer; subjecting bottoms of the contact holes to a dry cleaning process; and forming a second wiring layer on the interlayer dielectric layer, wherein the second wiring layer is electrically connected to the first wiring layer via the contact holes.

Abstract: Disclosed is a method for reducing contact resistance, including depositing a GST layer on an InGaAs substrate, generating an InGaAs/GST/Ni stacked structure by depositing a Ni layer on the GST layer, and thermally treating the stacked structure to rearrange components of the GST layer and to generate a Ni-InGaAs alloy.

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

Abstract: A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the first dielectric layer; depositing a first metal layer to fill the feature; etching the first metal layer to form a recess; depositing a second dielectric layer to fill the recess wherein the second dielectric layer is a low-k material suitable as a metal and oxygen diffusion barrier; forming a patterned mask layer atop the substrate to expose a portion of the second dielectric layer and the etch stop layer; etching the exposed portion of the second dielectric layer to a top surface of the first metal layer to form a via in the second dielectric layer; and depositing a second metal layer atop the substrate, wherein the second metal layer is connected to the first metal layer by the via.

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.

Abstract: Disclosed herein is a method of manufacturing a packaged wafer including a step of forming grooves in a face side of a wafer along projected dicing lines to a depth than a finished thickness of the wafer, a step of forming a ring-shaped groove in and along a boundary between a device area and an outer peripheral excess area of the wafer to a depth larger than the depth of the grooves, and a step of placing a recess mold of a molding apparatus in engagement with the wafer so that a side wall of the recess mold is placed on a bottom of the ring-shaped groove and filling a space between the recess mold and the wafer with a molding resin.

Abstract: A starting semiconductor structure includes a layer of filler material (e.g., amorphous silicon), a hard mask layer over the layer of filler material, and filler material lines over the hard mask layer. A protective layer is formed over one or more, but less than all of the filler material lines, at least one protected filler material line and at least one unprotected filler material line have a same width, and, after forming the protective layer, oxidizing unprotected filler material lines, such that the oxidized unprotected line(s) have a larger width than the protected filler material line(s).

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: A fin field-effect transistor is provided. The fin field-effect transistor includes a substrate, a fin structure, a gate-stacked structure, and an isolation structure. The fin structure is disposed on the substrate, and the gate-stacked structure covers the fin structure.

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a first channel material and layers of a sacrificial material. A second stack is formed in a second device region, the second stack including layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner. The liner protects the second channel material from the wet etch.