Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

Abstract: A lid array panel includes multiple lids, where each lid includes an outer side wall. The lid array panel further includes a bridge section surrounding and attached to the outer side walls of the lids, where the lids are connected to each other by the bridge section, the lid array panel further includes a reinforcement attached to the bridge section. A package structure includes a carrier, a chip disposed on an upper surface of the carrier, a lid, a bridge section, and a reinforcement. The lid includes a top wall and an outer side wall, the top wall and the outer side wall of the lid together define a cavity, and the outer side wall of the lid is attached to the upper surface of the carrier. The bridge section surrounds, and is attached to, the outer side wall of the lid. The reinforcement is attached to the bridge section.

Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

Abstract: A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.

Abstract: Disclosed herein is a packaged wafer manufacturing method including the steps of forming a groove along each division line on the front side of a wafer, each groove having a depth greater than the finished thickness of the wafer, next removing a chamfered portion from the outer circumference of the wafer to thereby form a step portion having a depth greater than the depth of each groove, next setting a die of a molding apparatus on the bottom surface of the step portion of the wafer in the condition where a space is defined between the die and the wafer, and next filling a mold resin into this space. Accordingly, the device area of the wafer is covered with the mold resin and each groove of the wafer is filled with the mold resin to thereby obtain a packaged wafer.

Abstract: A semiconductor device includes: a semiconductor element disposed on a semiconductor substrate; a first insulating film disposed on the semiconductor substrate, the first insulating film having an upper surface and an edge; a resin layer disposed on the semiconductor substrate, the resin layer covering the semiconductor element; and a second insulating film disposed on the semiconductor substrate, the second insulating film covering the upper and side surfaces of the resin layer, wherein the second insulating film has an edge arranged apart from the side surface of the resin layer by a distance, and the distance between the edge of the second insulating film and the side surface of the resin layer is greater than a film thickness of the second insulating film.

Abstract: Embodiments of the disclosure pertain to a method for monitoring a heat exchanger unit that may include the steps of: coupling the heat exchanger unit with a heat generating device; associating a monitoring module with an airflow side of the heat exchanger unit; operating the monitoring module whereby a microcontroller performs tasks related to providing an indication; and taking an action based on the indication. The monitoring module includes an at least one sensor proximate to the airflow side; a logic circuit in operable communication with the at least one sensor, and further comprising the microcontroller.

Abstract: According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure.

Abstract: A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

Abstract: A power semiconductor device includes a power semiconductor element, a controlling element, a first lead frame and a second lead frame, respectively, a first metal wire electrically connecting the power semiconductor element and the first lead frame, and a sealing body covering these components. The first lead frame includes a first inner lead having a connecting surface to which one end of the first metal wire is connected. Among surfaces of the sealing body, in a side surface, a resin inlet mark is formed in a side surface portion from which the first lead frame and the second lead frame do not project, the resin inlet mark being greater in surface roughness than another area. The resin inlet mark is formed opposite to a side where the first metal wire is positioned on the connecting surface when seen in the direction along the mounting surface.

Abstract: An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.

Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

Abstract: A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.

Abstract: An electronic part mounting heat-dissipating substrate which includes: a conductor plate which is formed on lead frames of wiring pattern shapes; and an insulating member which is provided between the lead frames of the wiring pattern shapes on the conductor plate; wherein a plate surface of a part arrangement surface of the conductor plate and a top surface of the insulating member at a side of the part arrangement surface form one continuous surface, wherein a plate surface of a back surface of the part arrangement surface of the conductor plate and a top surface of the insulating member at a side of the back surface at the part arrangement surface-side are formed in an identical plane, wherein the substrate is formed in a circular shape

Abstract: In a memory cell unit array, memory cell units each constituted of first wires, second wires, and a nonvolatile memory cell are arranged in a two-dimensional matrix form in a first direction and a second direction. Each of the memory cell units includes a control circuit below it. The control circuit is constituted of a first control circuit and a second control circuit. The second wires are connected to the second control circuit. Some of the first wires that constitute the memory cell unit are connected to the first control circuit that constitutes this memory cell unit. Others of the first wires are connected to the first control circuit that constitutes an adjacent memory cell unit adjacent thereto in the first direction.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.

Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

Abstract: A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. The groove filled with the second material layer forms the ring structure, while the via hole filled with the first material layer forms the TSV electrode.

Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer, and a conductive structure. The stack structure includes a plurality of conductive layers and a plurality of insulating layers stacked interlacedly. The etching stop layer is formed on a sidewall of the stack structure. An energy gap of the etching stop layer is larger than 6 eV. The conductive structure is electrically connected to at least one of the conductive layers.

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.

Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

Abstract: Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of a front surface of the substrate, a mold resin that covers the front surface of the substrate so as to embed the first electronic component therein and has a concave portion above the first region, a magnetic film selectively provided in the concave portion, and a first metal film that is connected to the power supply pattern and covers the mold resin.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate linesare spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.

Abstract: A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall thickness of less than 0.2 mm and a thinned area surrounding the lens so that in the thinned area the wall thickness is reduced by at least 35%.

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

Abstract: A method for fabricating a semiconductor structure includes providing a wafer and a carrier wafer. The wafer includes a first bonding surface and a plurality of radio-frequency (RF) devices and the carrier wafer includes a second bonding surface. The method further includes performing a surface treatment process on the second bonding surface to convert a surface portion of the carrier wafer into a barrier layer to suppress movement of induced electrical charges in the carrier wafer, and then bonding the wafer with the carrier wafer through the first bonding surface and the second bonding surface, respectively.

Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

Abstract: A semiconductor device includes a substrate including, on a surface thereof, a first conductive pad and a first insulating layer formed around the first conductive pad, a semiconductor chip including, on a surface thereof, a second conductive pad and a second insulating layer around the second conductive pad, an intermediate layer formed between the substrate and the semiconductor chip, and including a conductive portion between the first and second conductive pads, and an insulating portion between the first and second insulating layers, and a molecular bonding layer formed between the substrate and the intermediate layer, and including at least one of a first molecular portion covalently bonded to a material of the first conductive pad and a material of the conductive portion, and a second molecular portion covalently bonded to a material of the first insulating layer and a material of the insulating portion.

Abstract: A semiconductor device includes a base, a semiconductor chip on the base, a conductive bonding layer between a surface of the base and a surface of the semiconductor chip, the conductive bonding layer including a resin and a plurality of conductive particles contained in the resin, and a molecular bonding layer between the surface of the semiconductor chip and a surface of the conductive bonding layer, and including a molecular portion covalently bonded to a material of the semiconductor chip and a material of the conductive bonding layer.

Abstract: An objective of the present invention is to provide a sinterable bonding material excellent in sinterability. The present invention relates to a sinterable bonding material comprising a silver filler and an organic base compound as a sintering promoter.

Abstract: A die and substrate assembly is disclosed for a die with electronic circuitry and a substrate. A sintered bonding layer of sintered metal is disposed between the die and the substrate. The sintered bonding layer includes a plurality of zones having different sintered metal densities. The plurality of zones are distributed along one or more horizontal axes of the sintered bonding layer, along one or more vertical axes of the sintered bonding layer or along both one or more horizontal and one or more vertical axes of the sintered bonding layer.

Abstract: A semiconductor device includes a semiconductor chip covered with a resin layer, the semiconductor chip including an electrode pad at a surface of the semiconductor chip, a first insulating layer covering the surface of the semiconductor chip and having a via hole at a region corresponding to the electrode pad, a conductive layer extending along a surface of the electrode pad, a side surface of the via hole, and a planar surface the first insulating layer, to a region beyond a planar region defined by the semiconductor chip, a second insulating layer on the first insulating layer and covering the conductive layer; and a molecular bonding layer formed between the first insulating layer and the second insulating layer and including a molecular portion covalently bonded to a material of the conductive layer and a material of the second insulating layer.

Abstract: A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm?1 to 4,000 cm?1 indicated by IA, and a maximum value of intensity in a wavenumber range of 450 cm?1 to 550 cm?1 is indicated by IB, IA/IB is 1.1 or greater.

Abstract: A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.

Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.

Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Abstract: Electronic module (100), which comprises a first substrate (102), a first dielectric layer (104) on the first substrate (102), at least one electronic chip (106), which is mounted with a first main surface (108) directly or indirectly on partial region of the first dielectric layer (104), a second substrate (110) over a second main surface (114) of the at least one electronic chip (106), and an electrical contacting (116) for the electric contact of the at least one electronic chip (106) through the first dielectric layer (104), wherein the first adhesion layer (104) on the first substrate (102) extends over an area, which exceeds the first main surface (108).

Abstract: An objective of the present invention is to provide a sinterable bonding material capable of providing a bonded article having a long-term reliability. The present invention relates to a sinterable bonding material comprising a silver filler and resin particles, wherein the silver filler comprises a flake-shaped filler having an arithmetic average roughness (Ra) of 10 nm or less; and the resin particles have an elastic modulus (E) of 10 GPa or less, and a heat decomposition temperature of 200° C. or more. The sintered product of the sinterable bonding material of the present invention is excellent in bonding strength and heat-release characteristics, and has an improved stress relaxation ability.

Abstract: A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.

Abstract: A passive element package includes a first substrate, first passive elements disposed on the first substrate, a second substrate disposed on the first passive elements, second passive elements disposed on the second substrate, and a sealant that seals the first passive elements and the second passive elements. The passive element package can reduce the size of a semiconductor module that includes the passive element package.