Patents Issued in October 12, 2017
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Publication number: 20170294508Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.Type: ApplicationFiled: May 3, 2016Publication date: October 12, 2017Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
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Publication number: 20170294509Abstract: A method for forming a vertical single electron transistor includes forming a heterostructured nanowire having a SiGe region centrally disposed between an upper portion and a lower portion in the nanowire. An oxide is deposited to cover the SiGe region, and a condensation process is performed to convert the SiGe to oxide and condense Ge to form an island between the upper portion and the lower portion of the nanowire. A bottom contact is formed about the lower portion, a first dielectric layer is formed on the bottom contact and a gate structure is formed about the island on the first dielectric layer. A second dielectric layer is formed on the gate structure, and a top contact is formed on the second dielectric layer.Type: ApplicationFiled: January 9, 2017Publication date: October 12, 2017Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
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Publication number: 20170294510Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.Type: ApplicationFiled: June 27, 2017Publication date: October 12, 2017Inventors: DECHAO GUO, SHOGO MOCHIZUKI, ANDREAS SCHOLZE, CHUN-CHEN YEH
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METHODS, DEVICES, AND SYSTEMS RELATED TO FORMING SEMICONDUCTOR POWER DEVICES WITH A HANDLE SUBSTRATE
Publication number: 20170294511Abstract: Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: Martin F. Schubert, Vladimir Odnoblyudov, Cem Basceri -
Publication number: 20170294512Abstract: A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep well as part of a gate structure for the JFET, the deep well may be used as an isolation region from the surrounding substrate. As a result, the channel in the JFET may be pinched laterally between doped regions located between the source and the drain of the JFET. In other example embodiments, the channel may be pinched vertically and the isolation between the JFET structure and the substrate is maintained. A JFET structure with improved isolation from the substrate may be employed in some embodiments as a low-noise amplifier. In particular, the low-noise amplifier may be coupled to small signal devices, such as microelectromechanical systems (MEMS)-based microphones.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Inventors: Shanjen Pan, Marc L. Tarabbia, John L. Melanson
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Publication number: 20170294513Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: June 21, 2017Publication date: October 12, 2017Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
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Publication number: 20170294514Abstract: A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.Type: ApplicationFiled: June 21, 2017Publication date: October 12, 2017Inventor: ROBERT J. MEARS
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Publication number: 20170294515Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.Type: ApplicationFiled: May 31, 2017Publication date: October 12, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Timothy J. MCARDLE, Judson R. HOLT, Junli WANG
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Publication number: 20170294516Abstract: A thin film transistor and a producing method thereof, and an array substrate, which belong to a technical field of the thin film transistor, can solve a problem of poor performance of a conventional thin film transistor. The producing method of the thin film transistor comprises: S1: forming a gate electrode (11) composed of graphene; S2: forming a gate insulating layer (12) composed of oxidized graphene; S3: forming an active region (13) composed of doped oxidized graphene or doped graphene; S4: forming a source electrode (14) and a drain electrode (15) composed of graphene, wherein, the graphene composing the source electrode (14), the drain electrode (15) and the gate electrode (11) is formed by reducing oxidized graphene, and the doped oxidized graphene or doped graphene composing the active region (13) is formed by treating oxidized graphene.Type: ApplicationFiled: March 24, 2016Publication date: October 12, 2017Inventors: Dacheng ZHANG, Dianjie HOU, Wenchu DONG
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Publication number: 20170294517Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.Type: ApplicationFiled: June 22, 2017Publication date: October 12, 2017Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
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Publication number: 20170294518Abstract: A semiconductor device including, a semiconductor layer including a plurality of first trenches formed therein and a second trench formed in a region between the first trenches, channel regions formed in regions between the first and second trenches in a surface layer portion of the semiconductor layer, field plate electrodes embedded at bottom portion sides of the respective first trenches, first gate electrodes embedded at opening portion sides of the respective first trenches so as to face the channel regions across first gate insulating films above the field plate electrodes, second insulating films interposed between the field plate electrodes and the first gate electrodes, an embedded insulating film embedded to an intermediate portion of the second trench, and a second gate electrode embedded in the second trench so as to face the channel regions across a second gate insulating film above the embedded insulating film.Type: ApplicationFiled: April 4, 2017Publication date: October 12, 2017Inventor: Yuto OSAWA
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Publication number: 20170294519Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Inventors: Shahrukh A. Khan, Unoh Kwon, Shahab Siddiqui, Sean M. Polvino, Joseph F. Shepard, JR.
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Publication number: 20170294520Abstract: A thin film transistor substrate including a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer including a channel region, and a source region and a drain region at first and second sides of the channel region; a gate electrode disposed on the semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and a first insulating layer disposed on the substrate, the first insulating layer exposes the upper surface of the gate electrode and surrounds the gate electrode.Type: ApplicationFiled: November 17, 2016Publication date: October 12, 2017Inventors: ILJEONG LEE, Youngwoo Park, Wangwoo Lee
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Publication number: 20170294521Abstract: A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n? region with a lower impurity concentration than the n-type drift region.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takahiro TAMURA, Yasuhiko ONISHI
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Publication number: 20170294522Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity comprises an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge.Type: ApplicationFiled: April 6, 2016Publication date: October 12, 2017Inventors: Shesh Mani Pandey, Muhammad Rahman, Srikanth Balaji Samavedam
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Publication number: 20170294523Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.Type: ApplicationFiled: April 10, 2016Publication date: October 12, 2017Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
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Publication number: 20170294524Abstract: A method for forming a fin device includes forming semiconductor fins over a first dielectric layer. A second dielectric layer is directionally deposited into or on the first dielectric layer and on tops of the fins on horizontal surfaces. The second dielectric layer is configured to protect the first dielectric layer in subsequent processing. Sidewalls of the fins are precleaned while the first dielectric layer is protected by the second dielectric layer. The second dielectric layer is removed to expose the first dielectric layer in a protected state.Type: ApplicationFiled: June 20, 2017Publication date: October 12, 2017Inventors: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang
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Publication number: 20170294525Abstract: A lateral bipolar junction transistor (LBJT) device that includes an intrinsic III-V semiconductor material having a first band gap; and a base region present on the intrinsic III-V semiconductor material. The base region is composed of an III-V semiconductor material having a second band gap that is less than the first band gap. Emitter and collector regions present on opposing sides of the base region. The emitter and collector regions are composed of epitaxial III-V semiconductor material that is present on the intrinsic III-V semiconductor material.Type: ApplicationFiled: April 6, 2016Publication date: October 12, 2017Inventors: Pouya Hashemi, Tak H. Ning, Alexander Reznicek
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Publication number: 20170294526Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.Type: ApplicationFiled: June 22, 2017Publication date: October 12, 2017Inventors: Liutauras Storasta, Chiara Corvasce, Manuel Le Gallo, Munaf Rahimo, Arnost Kopta
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Publication number: 20170294527Abstract: An insulated gate bipolar transistor (IGBT) includes: a p base layer disposed close to a front surface of an n-type silicon substrate; and a deep n+ buffer layer and a shallow n+ buffer layer disposed close to a back surface of the n-type silicon substrate. The p base layer has a higher impurity concentration than the n-type silicon substrate. The deep n+ buffer layer and shallow n+ buffer layer have higher impurity concentrations than the n-type silicon substrate. The deep n+ buffer layer is disposed throughout a region close to the back surface in the n-type silicon substrate. The shallow n+ buffer layer is selectively disposed close to the back surface in the n-type silicon substrate. The shallow n+ buffer layer has a higher impurity concentration than the deep n+ buffer layer, and is shallower from the back surface than the deep n+ buffer layer.Type: ApplicationFiled: December 13, 2016Publication date: October 12, 2017Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Tetsuo TAKAHASHI, Mitsuru KANEDA, Ryu KAMIBABA
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Publication number: 20170294528Abstract: III-nitride based high electron mobility transistors (HEMTs), such as AlGaN/GaN HEMTs on Silicon substrates, with improved heat dissipation are described herein. A semiconductor device having improved heat dissipation may include a substrate having a top surface and a bottom surface, a nucleation layer on the top surface of the substrate, a transition layer on the nucleation layer, a buffer layer on the transition layer, a barrier layer on the buffer layer, and a metal layer filling a via hole that extends from the bottom surface of the substrate to a bottom surface of the transition layer.Type: ApplicationFiled: October 2, 2015Publication date: October 12, 2017Inventors: Fan Ren, Stephen John Pearton, Mark E. Law, Ya-Hsi Hwang
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Publication number: 20170294529Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer and an aluminum (Al) based layer having an interface with the GaN layer is disclosed. The Al based layer includes Al and an alloying element that is selected from Group IIIB transition metals of the periodic table of elements. The epitaxial layers are disposed over the substrate. A gate contact, a drain contact, and a source contact are disposed on a surface of the epitaxial layers such that the source contact and the drain contact are spaced apart from the gate contact and each other. The alloying element relieves lattice stress between the GaN layer and the Al based layer while maintaining a high sheet charge density within the HEMT device.Type: ApplicationFiled: October 21, 2016Publication date: October 12, 2017Inventors: Edward A. Beam, III, Jinqiao Xie
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ELECTRONIC DEVICE INCLUDING A HEMT WITH A SEGMENTED GATE ELECTRODE AND A PROCESS OF FORMING THE SAME
Publication number: 20170294530Abstract: An electronic device can include a low-side HEMT including a segmented gate electrode; and a high-side HEMT coupled to the low-side HEMT, wherein the low-side and high voltage HEMTs are integrated within a same semiconductor die. In another aspect, an electronic device can include a source electrode; a low-side HEMT; a high-side HEMT coupled to the low-side HEMT; and a resistive element. In an embodiment, the resistive element can be coupled to the source electrode and a gate electrode of the high voltage HEMT, and in another embodiment, the resistive element can be coupled to the source electrode and a drain of the low-side HEMT. A process of forming an electronic device can include forming a channel layer over a substrate; and forming a gate electrode over the channel layer. The gate electrode can be a segmented gate electrode of a HEMT.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Peter MOENS, Jaume ROIG-GUITART, Marnix TACK, Johan Camiel Julia JANSSENS -
Publication number: 20170294531Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
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Publication number: 20170294532Abstract: A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.Type: ApplicationFiled: June 20, 2017Publication date: October 12, 2017Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Publication number: 20170294533Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.Type: ApplicationFiled: April 22, 2016Publication date: October 12, 2017Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
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Publication number: 20170294534Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.Type: ApplicationFiled: November 30, 2016Publication date: October 12, 2017Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
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Publication number: 20170294535Abstract: A semiconductor device and fabrication method thereof are provided. The method includes forming at least one dummy gate structure and sidewall spacers of the dummy gate structure in a first dielectric layer, together on a substrate, and removing the dummy gate structure, thereby forming a first opening between the sidewall spacers. The method further includes forming a gate structure in the first opening and having a top surface levelled the first dielectric layer, removing a portion of the sidewall spacers and a portion of the gate structure, respectively, to form a second opening in the first dielectric layer, on remaining sidewall spacers, and on remaining gate structure, and forming a capping layer to fill the second opening and to have a top surface levelled with the first dielectric layer.Type: ApplicationFiled: February 20, 2017Publication date: October 12, 2017Inventors: Cheng Long ZHANG, Guang Jie YUAN, Hai Yang ZHANG
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Publication number: 20170294536Abstract: A technique relates to semiconductors. A bottom terminal of a transistor and bottom plate of a capacitor are positioned on the substrate. A spacer is arranged on the bottom terminal of the transistor. A transistor channel region extends vertically from the bottom terminal through the spacer to contact a top terminal of the transistor. A capacitor channel region extends vertically from the bottom plate to contact a top plate of the capacitor. A first gate stack is arranged along sidewalls of the transistor channel region and is in contact with the spacer. A second gate stack is arranged along sidewalls of the capacitor channel region and is disposed on the bottom plate. A distance from a bottom of the first gate stack to a top of the bottom terminal is greater than a distance from a bottom of the second gate stack to a top of the bottom plate.Type: ApplicationFiled: March 27, 2017Publication date: October 12, 2017Inventor: Brent A. Anderson
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Publication number: 20170294537Abstract: A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: Kangguo Cheng, Tak H. Ning
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Publication number: 20170294538Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
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Publication number: 20170294539Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.Type: ApplicationFiled: June 21, 2017Publication date: October 12, 2017Inventors: En-Chiuan Liou, Yu-Cheng Tung
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Publication number: 20170294540Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of the substrate, and the two source/drain regions are separated from each other. The two source/drain regions are formed of an epitaxial material. The gate structure is disposed on the substrate between the two source/drain regions. The two salicide layers are disposed on the substantially flat top surfaces of the two source/drain regions, respectively.Type: ApplicationFiled: April 11, 2016Publication date: October 12, 2017Inventors: I-Cheng Hu, Kai-Hsiang Wang, Tien-I Wu, Yu-Shu Lin, Shu-Yen Chan
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Publication number: 20170294541Abstract: A highly reliable semiconductor device includes a first insulator, a second insulator, a first conductor, a third insulator, an oxide semiconductor, second and third conductors, a fourth insulator, a fourth conductor overlapping with a region between the second and third conductors, a fifth insulator, and a sixth insulator in this order. The fourth insulator is in contact with top and side surfaces of the oxide semiconductor, and a top surface of the third insulator. The fifth insulator is in contact with the side surface of the oxide semiconductor and the top surface of the third insulator so as to cover the oxide semiconductor, the second to fourth conductors, and the fourth insulator. The first, second, fifth, and sixth insulators have low permeability for hydrogen, water, and oxygen. The first and sixth insulators have a thinner thickness than the second and sixth insulators, respectively.Type: ApplicationFiled: April 3, 2017Publication date: October 12, 2017Inventor: Shunpei YAMAZAKI
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Publication number: 20170294542Abstract: A transistor with stable electrical characteristics is provided. The transistor includes a first insulator over a substrate; first to third oxide insulators over the first insulator; a second insulator over the third oxide insulator; a first conductor over the second insulator; and a third insulator over the first conductor. An energy level of a conduction band minimum of each of the first and second oxide insulators is closer to a vacuum level than that of the oxide semiconductor is. An energy level of a conduction band minimum of the third oxide insulator is closer to the vacuum level than that of the second oxide insulator is. The first insulator contains oxygen. The number of oxygen molecules released from the first insulator measured by thermal desorption spectroscopy is greater than or equal to 1E14 molecules/cm2 and less than or equal to 1E16 molecules/cm2.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Tetsuhiro TANAKA, Akihisa SHIMOMURA, Yasumasa YAMANE, Ryo TOKUMARU, Yuhei SATO, Kazuhiro TSUTSUI
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Publication number: 20170294543Abstract: An object is to provide a highly reliable transistor. In a bottom-gate transistor including an oxide semiconductor layer as a semiconductor layer where a channel is formed, an insulating layer containing excess oxygen is formed over the oxide semiconductor layer, and then an insulating layer through which impurities do not easily pass is formed without exposure to the air. As the insulating layer through which impurities do not easily pass, an aluminum oxide layer or the like can be used. When a conductive layer with a function of absorbing hydrogen is used for a source electrode and a drain electrode, the amount of hydrogen in the oxide semiconductor layer can be reduced.Type: ApplicationFiled: April 3, 2017Publication date: October 12, 2017Inventor: Shunpei YAMAZAKI
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Publication number: 20170294544Abstract: In various embodiments of the disclosed subject matter, a method for forming a thin film transistor (TFT), a related TFT, array substrate, and display apparatus are provided. The method comprises: forming a pattern of an active layer on a base substrate and insulated from a gate electrode; forming a first initial ohmic contacting layer and a second initial ohmic contacting layer on the active layer; forming a source electrode on the first initial ohmic contacting layer, and a drain electrode on the second initial ohmic contacting layer; and performing a heating treatment to the base substrate having the source electrode and the drain electrode thereon, such that metal atoms in the source electrode diffuse to the first initial ohmic contacting layer to form a first ohmic contacting layer, and metal atoms in the drain electrode diffuse to the second initial ohmic contacting layer to form a second ohmic contacting layer.Type: ApplicationFiled: June 7, 2016Publication date: October 12, 2017Inventor: Lungpao HSIN
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Publication number: 20170294545Abstract: A process for preparing a passivated emitter rear contact solar cell, which includes the steps as follows: removing the damaged layer on the surface of the silicon wafer and at the same time polishing both surfaces, texturing, forming PN junction, etching, removing the glass impurity, depositing a passivation film on the back surface, depositing a passivating antireflective layer on the front surface, making local openings on the back surface, screen printing of metal paste on both the front surface and the back surface and sintering, in which the texturing step employs a catalytic metal etching approach, and the textured structure is a nanometer-level textured structure. The present invention has combined removing the damaged layer on the surface of the silicon wafer and polishing both the front and back surfaces into one single step, and thus has simplified the production process and reduced the production cost.Type: ApplicationFiled: December 31, 2015Publication date: October 12, 2017Applicant: CSI CELLS CO., LTDInventors: Shuai ZOU, Weixu LONG, Xusheng WANG, Guoqiang XING
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Publication number: 20170294546Abstract: The present invention(s) is directed to novel conductive Mn+1Xn(Ts) compositions exhibiting high volumetric capacitances, and methods of making the same. The present invention(s) is also directed to novel conductive Mn+1Xn(Ts) compositions, methods of preparing transparent conductors using these materials, and products derived from these methods.Type: ApplicationFiled: September 23, 2015Publication date: October 12, 2017Applicant: Drexel UniversityInventors: Michael J. GHIDIU, Michel W. BARSOUM, Yury GOGOTSI, Aaron Thomas FAFARMAN, Andrew DeVries Dillon
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Publication number: 20170294547Abstract: A semiconductor layered structure includes a base layer, a quantum well structure, and a contact layer. The base layer, the quantum well structure, and the contact layer are disposed so as to be stacked in this order. In the contact layer, a region including a first main surface that is a main surface on a quantum well structure side has a p-type impurity concentration lower than a p-type impurity concentration of a region including a second main surface that is a main surface opposite to the first main surface. A photodiode includes the semiconductor layered structure and an electrode formed on the semiconductor layered structure. A sensor includes the photodiode and a read-out circuit connected to the photodiode.Type: ApplicationFiled: October 21, 2015Publication date: October 12, 2017Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kaoru SHIBATA, Koji NISHIZUKA, Suguru ARIKATA, Takashi KYONO, Katsushi AKITA
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Publication number: 20170294548Abstract: An insulating paste includes a siloxane resin and an organic solvent. The siloxane resin includes a phenyl group and an alkyl group expressed by a general formula CnH2n+1, in which n is a natural number. The number of alkyl groups is greater than the number of phenyl groups in the siloxane resin.Type: ApplicationFiled: April 11, 2017Publication date: October 12, 2017Inventors: Jumpei SATO, Ryo MATSUOKA, Shinya ISHIKAWA
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Publication number: 20170294549Abstract: One or more embodiments of the present invention are directed to a photovoltaic system. The system comprises photovoltaic cells, arranged side-by-side to form an array of photovoltaic cells. It further involves a cooling device, which comprises one or more layers, wherein the layers extend opposite to the array of photovoltaic cells and in thermal communication therewith, for cooling the cells, in operation. The one or more layers are structured such that a thermal resistance of the photovoltaic system varies across the array of photovoltaic cells, so as to remove heat from photovoltaic cells of the array with different heat removal rates, in operation. One or more embodiments of the present invention are further directed to related systems and methods for cooling such photovoltaic systems.Type: ApplicationFiled: April 12, 2016Publication date: October 12, 2017Inventors: Emanuel Loertscher, Bruno Michel, Stephan Paredes, Patrick Ruch
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Publication number: 20170294550Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: Szu-Lin Cheng, Han-Din Liu, Shu-Lu Chen, Yun-Chung Na, Hui-Wen Chen
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Publication number: 20170294551Abstract: Contrary to conventional wisdom, which holds that light-emitting diodes (LEDs) should be cooled to increase efficiency, the LEDs disclosed herein are heated to increase efficiency. Heating an LED operating at low forward bias voltage (e.g., V<kBT/q) can be accomplished by injecting phonons generated by non-radiative recombination back into the LED's semiconductor lattice. This raises the temperature of the LED's active rejection, resulting in thermally assisted injection of holes and carriers into the LED's active region. This phonon recycling or thermo-electric pumping process can be promoted by heating the LED with an external source (e.g., exhaust gases or waste heat from other electrical components). It can also be achieved via internal heat generation, e.g., by thermally insulating the LED's diode structure to prevent (rather than promote) heat dissipation. In other words, trapping heat generated by the LED within the LED increases LED efficiency under certain bias conditions.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Parthiban Santhanam, Dodd Joseph GRAY, Rajeev Jagga RAM
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Publication number: 20170294552Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having a top area at a top side, a bottom area at an underside, and side areas connecting the top area and the bottom area; electrical contact locations at the top area or at the bottom area of the optoelectronic semiconductor chip; and an electrically insulating shaped body, wherein the optoelectronic semiconductor chip is a flip-chip having the electrical contract locations only at one side, either the underside or the top side, the shaped body surrounds the optoelectronic semiconductor chip at its side areas, and the shaped body is free of a via that electrically connects the optoelectronic semiconductor chip.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Karl Weidner, Ralph Wirth, Axel Kaltenbacher, Walter Wegleiter, Bernd Barchmann, Oliver Wutz, Jan Marfeld
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Publication number: 20170294553Abstract: A manufacturing method of light-emitting device is disclosed. The method includes providing an LED wafer comprising a substrate and a semiconductor stack formed on the substrate, wherein the semiconductor stack has a lower surface facing the substrate and an upper surface opposite to the lower surface; providing a first laser to the LED wafer and irradiating the LED wafer from the upper surface to form a plurality of scribing lines on the upper surface; providing and focusing a second laser on an interior of the substrate to form a plurality of textured areas in the substrate; and providing force on the LED wafer to separate the LED wafer into a plurality of LED chips.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: Po-Shun CHIU, De-Shan KUO, Jhih-Jheng YANG, Jiun-Ru HUANG, Jian-Huei LI, Ying-Chieh CHEN, Zi-Jin LIN
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Publication number: 20170294554Abstract: A nitride semiconductor light-emitting element includes at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer. A multilayer body is provided between the n-type nitride semiconductor layer and the light-emitting layer, having at least one stack of first and second semiconductor layers. The second semiconductor layer has a greater band-gap energy than the first semiconductor layer. The first and second semiconductor layers each have a thickness of more than 10 nm and 30 nm or less. In applications in which luminous efficiency at room temperature is a high priority, the first semiconductor layer has a thickness of more than 10 nm and 30 nm or less, the second semiconductor layer has a thickness of more than 10 nm and 40 nm or less, and the light-emitting layer has V-shaped recesses in cross-sectional view.Type: ApplicationFiled: August 31, 2015Publication date: October 12, 2017Applicant: Sharp Kabushiki KaishaInventors: Yoshihiko TANI, Tetsuya HANAMOTO, Masanori WATANABE, Akihiro KURISU, Katsuji IGUCHI, Hiroyuki KASHIHARA, Tomoya INOUE, Toshiaki ASAI, Hirotaka WATANABE
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Publication number: 20170294555Abstract: A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising AlxInyGal-x-yN layers, at least one GaN based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer. The AlxInyGal-x-yN layers stacked on the light emitting layer, where 0<x<1, 0?y<1, and 0<x+y<1, and the GaN based layer interposed between two of the AlxInyGal-x-yN layers, and the ohmic contact layer is disposed on the AlxInyGal-x-yN layers.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Applicant: Genesis Photonics Inc.Inventors: Chi-Feng Huang, Ching-Liang Lin, Shen-Jie Wang, Jyun-De Wu, Yu-Chu Li, Chun-Chieh Lee
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Publication number: 20170294556Abstract: A light emitting diode and a method of manufacturing the light emitting diode are provided. The light emitting diode includes an n-type semiconductor layer, an inclined type superlattice thin film layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer is disposed on a substrate. The inclined type superlattice thin film layer is disposed on the n-type semiconductor layer and includes a plurality of thin film pairs in which InGaN thin films and GaN thin films are sequentially stacked. The active layer having a quantum well structure is disposed on the inclined type superlattice thin film layer. The p-type semiconductor layer is disposed on the active layer. Composition ratio of Indium (In) included in the InGaN thin film is increased as getting closer to the active layer. Thus, internal residual strain is reduced, and quantum confinement effect is enhanced, and internal quantum efficiency is increased.Type: ApplicationFiled: June 23, 2017Publication date: October 12, 2017Applicant: INDUSTRY FOUNDATION OF CHONNAM NATIONAL UNIVERSITYInventors: Taeksoo JI, Jinyoung PARK, Jinhong LEE, Wangki KIM, Jaesam SHIM, Kwangjae LEE
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Publication number: 20170294557Abstract: According to at least some embodiments of the present disclosure, a light-emitting diode (LED) chip includes a semiconductor material portion, a transparent conductive layer disposed above the semiconductor material portion, a current blocking layer disposed above the transparent conductive layer, one or more electrodes disposed above the current blocking layer, and a plurality of electron outflow channels that electrically interconnect at least one electrode and the semiconductor material portion across the transparent conductive layer and the current blocking layer.Type: ApplicationFiled: April 7, 2017Publication date: October 12, 2017Inventors: Liang Chen, Junxian Li, Qimeng Lv, Zhendong Wei, Yingce Liu, Xiaoping Li, Xinmao Huang, Kaixuan Chen, Yong Zhang, Zhiwei Lin, Wei Jiang, Xiangjing Zhuo, Tianzu Fang