Abstract: The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

Abstract: A display device includes: a substrate; a first thin film transistor unit disposed on the substrate and comprising a first active layer comprising a silicon layer, wherein the first active layer comprises a channel region, a source region and a drain region; a second thin film transistor unit disposed on the substrate and comprising a second active layer comprising a metal oxide layer; and a display medium disposed on the first thin film transistor unit and the second thin film transistor unit. Herein, a thickness of the silicon layer in the channel region is less than or equal to a thickness of the silicon layer in the source region.

Abstract: A display device includes a substrate; a gate insulating layer disposed on the substrate, a first gate electrode and a second gate electrode; a first active layer disposed on the gate insulating layer and comprising a polysilicon layer; a first insulating layer disposed on the first active layer and the gate insulating layer; a second active layer disposed on the first insulating layer and comprising a metal oxide layer; a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, wherein the first source electrode and the first drain electrode are disposed on the first insulating layer and respectively electrically connect to the first active layer, and the second source electrode and the second drain electrode are disposed on the second active layer and electrically connect to the second active layer; and a display medium layer disposed on the substrate.

Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

Abstract: A peeling method at low cost with high mass productivity is provided. A resin layer having a thickness greater than or equal to 0.1 ?m and less than or equal to 3 ?m is formed over a formation substrate using a photosensitive and thermosetting material, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, the resin layer is irradiated with light using a linear laser device, and the transistor and the formation substrate are separated from each other. A first region and a second region which is thinner than the first region or an opening can be formed in the resin layer. In the case of forming a conductive layer functioning as an external connection terminal or the like to overlap with the second region or the opening of the resin layer, the conductive layer is exposed.

Abstract: A peeling method at low cost with high mass productivity is provided. An oxide layer is formed over a formation substrate, a first layer is formed over the oxide layer using a photosensitive material, an opening is formed in a portion of the first layer that overlaps with the oxide layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the oxide layer, the oxide layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other.

Abstract: A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.

Abstract: A film patterning method is provided. The method comprises: performing a dry etching process on a film to be patterned, so as to form a patterned film; removing a suspended particle on the patterned film; and performing another dry etching process on the patterned film after the suspended particle is removed, to form a final pattern of the film. By moving or completely removing the suspended particle on the patterned film and then performing another dry etching process on the patterned film to etch away the etching residue, existence of the etching residue is completely avoided in the final pattern of the film, so that the product yield is improved and the product quality is ensured.

Abstract: An image sensor having a pixel part generating a signal in accordance with a light, a signal processing part performing signal processing on the signal read from the pixel part, and a power supply part connected to the signal processing part via a first wiring, and supplying a power supply to the signal processing part, and a storage package storing the image sensor, and having a second wiring configuring a parallel circuit by being connected to the first wiring. Accordingly, it is possible to solve a problem such that a wiring resistance is increased when a power supply circuit is configured inside of a solid state image sensor.

Abstract: A solid-state imaging device includes a first semiconductor substrate in which first photoelectric conversion layers photoelectrically converting incident light in a first wavelength band are formed, a second semiconductor substrate in which second photoelectric conversion layers photoelectrically converting incident light are formed, a conductive layer disposed between the first semiconductor substrate and the second semiconductor substrate and having conductivity, an insulation film disposed between the second semiconductor substrate and the conductive layer and having an insulation property, in which light passing through the first photoelectric conversion layer, the conductive layer, and the insulation film is incident on the second semiconductor substrate, a predetermined voltage is applied to the conductive layer, and a wavelength of light in a second wavelength band photoelectrically converted by the second photoelectric conversion layer when the predetermined voltage is applied to the conductive layer

Abstract: An image sensor may include: a photoelectric conversion element suitable for generating a photo charge in response to incident light; and a transfer transistor suitable for transferring the photo charge generated by the photoelectric conversion element to a floating diffusion in response to a transfer signal, the transfer transistor comprising a first transfer gate formed over the photoelectric conversion element; an opening formed in the first transfer gate and exposing the photoelectric conversion element; a second transfer gate formed in the opening; and a channel layer interposed between the first and second transfer gates and between the photoelectric conversion element and the second transfer gate.

Abstract: A substrate for a camera module includes: a first substrate; an image sensor installed on the first substrate and a memory chip installed to be embedded in the first substrate. The first substrate includes a soft substrate portion disposed at a central portion of the first substrate, and a hard substrate portion formed on upper and lower portions of the soft substrate portion, and at least a portion of the memory chip is disposed in an installation hole formed in the soft substrate portion.

Abstract: Provided are a solid-state image pickup apparatus which includes: a semiconductor substrate having a plurality of photoelectric converters; a first and a second insulating layers formed on the semiconductor substrate; an optical waveguide formed above each of the plurality of photoelectric converters and in an opening portion of the first and the second insulating layers, and has a refractive index higher than a refractive index of the first insulating layer; and a light reflecting layer formed at a boundary between the optical waveguide and the second insulating layer, and has a refractive index lower than a refractive index of the optical waveguide, where the following expression is satisfied: ?<90°, where a represents an angle formed by a boundary surface between the light reflecting layer and the second insulating layer with respect to a boundary surface between the first insulating layer and the second insulating layer.

Abstract: A trenched device wafer includes a device substrate layer having a top surface; a plurality of devices in the device substrate layer, and a trench in the top surface. The trench extends into the device substrate layer, and is located between a pair of adjacent devices of the plurality of devices. A method for forming a device die from a device wafer includes forming a trench in a top surface of the device wafer between two adjacent devices of the device wafer. The trench has a bottom surface located (a) at a first depth beneath the top surface and (b) at a first height above a wafer bottom surface. The method also includes, after forming the trench, decreasing a thickness of the device wafer, between the two adjacent devices, to a thickness less than the first height.

Abstract: Provided is a photoelectric conversion device including: a semiconductor substrate having a photoelectric conversion unit; a first conductive layer formed over the semiconductor substrate; a first diffusion prevention layer formed over the first conductive layer; and a light guide that guides an incident light into the photoelectric conversion unit, in which the first diffusion prevention layer contains hydrogen atoms and carbon atoms, and a composition ratio of the hydrogen atoms is greater than or equal to 46 at % and less than or equal to 50 at %.

Abstract: Some embodiments of the present disclosure provide a back side illuminated. (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.

Abstract: Provided are an optical receiver that can realize a reduction in the variation of sensitivity in the ultraviolet light region and a reduction in noise in the visible light region and the infrared light region, a portable electronic device, and a method of producing an optical receiver. The first light-receiving device (PD1) and the second light-receiving device (PD2) of the optical receiver (1) are each constituted by forming a second conductivity-type N-type well layer (N_well) on a first conductivity-type P-type substrate (P_sub), forming a first conductivity-type P-type well layer (P_well) in the N-type well layer (N_well), and forming a second conductivity-type N-type diffusion layer (N) in the P-type well layer (P_well). The P-type substrate P_sub, the N-type well layer (N_well), and the P-type well layer (P_well) are electrically at the same potential or are short-circuited.

Abstract: A solid-state image pickup element including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.

Abstract: A camera module is provided, including a prism base, a prism driving mechanism, a prism unit, a lens unit, and an image sensor. The lens unit is disposed on the lens driving mechanism. The prism base includes a metal member, at least one first wiring layer, and a first insulation layer disposed between the metal member and the first wiring layer. The prism driving mechanism is electrically connected to the first wiring layer. The prism unit is connected to the prism driving mechanism, and the prism driving mechanism can drive the prism unit to rotate relative to the prism base. The image sensor can catch the light reflected by the prism unit and passing through the lens unit.

Abstract: A chip-scale packaging process for wafer-level camera manufacture includes aligning an optics component wafer with an interposer wafer having a photoresist pattern that forms a plurality of transparent regions, bonding the aligned optics component wafer to the interposer wafer, and dicing the bonded optics component wafer and interposer wafer such that each optics component with interposer has a transparent region. The process further includes dicing an image sensor wafer, aligning the pixel array of each image sensor with the transparent region of a respective optics component with interposer, and bonding each image sensor to its respective optics component with interposer. Each interposer provides alignment between its respective optics component center and its respective pixel array center of the image sensor based on the respective transparent region. The interposer further provides a back focal length for focusing light from the optics component onto a top surface of the pixel array.

Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m?1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

Abstract: In some examples, a semiconductor device may comprise a semiconductor chip including a plurality of pixels, each pixel formed of a plurality of sub-pixels, such as a red sub-pixel, green sub-pixel and blue sub-pixel. Each sub-pixel may comprise a light emitting diode. A first signal line may connect to signal terminals of a first group sub-pixels (e.g., arranged in the same row), and a second signal line may connect to common terminals of a second group of sub-pixels (e.g., arranged in the same column). The number of chip pads may thus be reduced to provide increased design flexibility in location and/or allowing an increase in chip pad size. In some examples, a light transmissive material may be formed in openings of a semiconductor growth substrate on which light emitting cells of the sub-pixels were grown. The light transmissive material of some of the sub-pixels may comprise a wavelength conversion material and/or filter.

Abstract: A dual light-emission member of a display apparatus or a lighting apparatus includes: a substrate including a first area and a second area adjacent to each other, where the second area of the substrate is light-transmissive; a first light-emitting member on the substrate and disposed in the first area of the substrate; and a lens commonly disposed over the first area and the second area of the substrate so as to cover the first light-emitting member.

Abstract: A pixel structure, a display substrate and a display device are disclosed. The pixel structure comprises a plurality of first pixels, second pixels and third pixels. The first pixel comprises a first sub-pixel arranged at upper-right part and a second sub-pixel arranged at lower-left part. The second pixel comprises the second sub-pixel arranged at upper-right part and a third sub-pixel arranged at lower-left part. The third pixel comprises the third sub-pixel arranged at upper-right part and the first sub-pixel arranged at lower-left part. The second pixels are arranged at the right and upper sides of the first pixels. The third pixels are arranged at the right and upper sides of the second pixels. The first pixels are arranged at the right and upper sides of the third pixels.

Abstract: Double magnetic tunnel junctions and methods of forming the same include a bottom reference layer having a first fixed magnetization and a first thickness. A first tunnel barrier is formed on the bottom reference layer. A free layer is formed on the first tunnel barrier and has a changeable magnetization. A second tunnel barrier is formed on the free layer. A top reference layer is formed on the second tunnel barrier and has a second fixed magnetization that is opposite to the first fixed magnetization and a second thickness that is significantly smaller than the first thickness.

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

Abstract: A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

Abstract: The present technology relates to an imaging device, a manufacturing device, and a manufacturing method capable of preventing a substance such as hydrogen from entering and preventing change in performance. The imaging device includes an organic photoelectric conversion film, an upper electrode provided in an upper portion of the organic photoelectric conversion film, a lower electrode provided in a lower portion of the organic photoelectric conversion film, and a metal thin film provided between the organic photoelectric conversion film and the upper electrode or between the organic photoelectric conversion film and the lower electrode. The metal thin film is provided between the organic photoelectric conversion film and the upper electrode. The upper electrode is formed of an oxide semiconductor, a metal oxide, and the metal thin film. The present technology can be applied to a vertical spectral imaging device.

Abstract: A solid-state image pickup unit includes: a substrate made of a first semiconductor; a substrate made of a first semiconductor; a photoelectric conversion device provided on the substrate and including a first electrode, a photoelectric conversion layer, and a second electrode in order from the substrate; and a plurality of field-effect transistors configured to perform signal reading from the photoelectric conversion device. The plurality of transistors include a transfer transistor and an amplification transistor, the transfer transistor includes an active layer containing a second semiconductor with a larger band gap than that of the first semiconductor, and one terminal of a source and a drain of the transfer transistor also serves the first electrode or the second electrode of the photoelectric conversion device, and the other terminal of the transfer transistor is connected to a gate of the amplification transistor.

Abstract: An image sensor comprising: a first layer having a plurality of groups of photodiodes formed in a semiconductor substrate, each group representing a 2×2 array of photodiodes, with 2 first pixels configured to detect light of a first wavelength and 2 second pixels configured to detect light of a second wavelength, each first pixel positioned adjacent to the second pixels; and a second layer overlapping the first layer, the second layer is organic, having a plurality of organic photodiodes configured to detect light of a third wavelength, each organic photodiode positioned to partially overlap 2 first photodiodes and 2 second photodiodes of the first layer.

Abstract: The examples relate to various implementations of a software configurable luminaire and a transparent display device for use in such a luminaire. The luminaire is able to generate light sufficient to provide general illumination of a space in which the luminaire is installed and provide an image display. The general illumination is provided by additional light sources and/or improved display components of the transparent display device.

Abstract: An organic light-emitting device that includes a first electrode, a second electrode facing the first electrode, an emission layer between the first electrode and the second electrode, and a hole transport region between the first electrode and the emission layer is presented.

Abstract: An organic light emitting display panel and apparatus, and a manufacturing method therefor are provided. The organic light emitting display panel includes a plurality of light emitting units, the light emitting unit includes an anode, a first auxiliary functional structure, a light emitting structure and a cathode, the anode, the first auxiliary functional structure, the light emitting structure and the cathode are successively laminated, and the first auxiliary functional structures of different light emitting units are arranged separate from one another, the anodes of different light emitting units are arranged separate from one another, and the light emitting structures of different light emitting units are arranged separate from one another.

Abstract: Discussed in an organic light emitting display device including a first pixel, and a second pixel being adjacent the first pixel, wherein each of the first pixel and the second pixel includes a plurality of subpixels, wherein the plurality of subpixels include a green subpixel, a red subpixel, and a blue subpixel, and wherein the red subpixel and the blue subpixel are shared by the first pixel and the second pixel.

Abstract: A display device is disclosed. The display device comprises an array structure comprising a plurality of primary pixel element structures arranged in a matrix. A primary pixel element structure comprises a plurality of pixel element structures arranged in a second direction. A pixel element structure comprises first, second, and third sub-pixel elements, each comprising a light-emitting region and a light-transmitting region disposed at one side of the light-emitting region and adjacent to the light-emitting region in a first direction, and the first direction being perpendicular to the second direction. When the display device is turned off, a scene on an opposite side of the display device is observed by an observer on either side of the display device, and when the display device is turned on, a scene on the opposite side of the display device is observed by the observer on a side where no light is emitted.

Abstract: Disclosed are an organic light emitting display device and a method of manufacturing the same, which reduce a loss of light emitted from an organic light emitting device, increase a lifetime of the organic light emitting device, and decrease consumption power of the organic light emitting display device. The organic light emitting display device includes a first electrode disposed on a first substrate, a bank disposed on the first electrode for dividing a plurality of emission parts, an organic light emitting layer disposed on the first electrode and the bank, a second electrode disposed on the organic light emitting layer, and an encapsulation layer disposed on the second electrode. The encapsulation layer fills a space between adjacent banks, and a refractive index of the bank is lower than a refractive index of the organic light emitting layer and a refractive index of the encapsulation layer.

Abstract: Disclosed is a display device that may include a thin film transistor array substrate that includes a plurality of first sub-pixels and a plurality of second sub-pixels, wherein one of the plurality of first sub-pixels includes a first emission region and a first non-emission region, and one of the plurality of second sub-pixels includes a second emission region and a second non-emission region; a first bank pattern in the first and second non-emission regions, the first bank pattern including a hydrophilic material; and a second bank pattern on an upper surface of the first bank pattern, the second bank pattern includes a hydrophobic material.

Abstract: An electronic device may have a flexible portion that allows the device to be folded. The device may have a flexible display. The flexible display may have edge portions that are joined along a flexible middle portion. The flexible middle portion may overlap a bend axis and may be bent about the bend axis. Flexibility enhancement regions may be formed in a backing layer, polarizer layer, organic-light-emitting display layer, and other display layers to enhance flexibility for the middle portion. The device may have a display with a flexible tail that is bent about a bend axis. Metal trace on the flexible display may include metal trace strips that serve as power lines. Flexibility enhancement regions such as slot-shaped openings or other openings may be formed in the metal trace strips to enhance flexibility.

Abstract: Disclosed is an array substrate, a display panel, and a display device. The array substrate includes: a substrate (100), a plurality of pixel units (110) disposed on a side of the base substrate (100), a chip (200) configured for providing signal to the pixel units (110), signal lines (120) corresponding to each of pixel units (110), and via holes (130) penetrating the base substrate (100). By disposing the chip (200) on the side of the base substrate (100) opposed to the pixel units (110) and electrically connecting the pixel units (110) to the chip (200) through the signal lines (120) in the via holes (130), the frame portion which is used for accommodating the chip could be omitted and a real frameless design is achieved.

Abstract: A display device is disclosed, which includes: a substrate; a light emitting diode disposed above the substrate; a first transistor disposed above the substrate; and a second transistor disposed above the substrate. The first transistor includes: a first semiconductor layer; a first top gate electrode disposed above the first semiconductor layer; a first bottom gate electrode disposed under the first semiconductor layer; a first source electrode electrically connected to the first semiconductor layer; and a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode. In addition, the second transistor includes: a second semiconductor layer. Herein, one of the first semiconductor layer and the second semiconductor layer includes a first silicon semiconductor layer, and the other includes a first oxide semiconductor layer.

Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.

Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

Abstract: A display apparatus including a first conductive layer; a first insulating layer including a first opening exposing a first upper surface of the first conductive layer and covering at least a part of an upper edge of the first conductive layer, wherein the first upper surface of the first conductive layer includes a center portion of an upper surface of the first conductive layer; a second conductive layer on a part of the first upper surface of the first conductive layer and on the first insulating layer; and a second insulating layer including a second opening exposing a second upper surface of the second conductive layer and covering a part of an upper edge of the second conductive layer, wherein the second upper surface of the second conductive layer includes a center portion of the upper surface of the second conductive layer and the second opening has an area that is less than that of the first opening.

Abstract: An organic light emitting device includes: a substrate; a first electrode provided on the substrate; a metal pattern provided along an edge of the first electrode; and a pixel definer provided on the metal pattern. The pixel definer covers an end portion of the first electrode and an end portion of the metal pattern. The pixel definer includes an opening exposing the first electrode.

Abstract: A display apparatus includes a substrate including a display area, a peripheral area surrounding the display area, a function-adding area, of which at least a portion is surrounded by the display area, and a detour area disposed between the display area and the function-adding area. The display apparatus includes a plurality of pixel circuits disposed in the display area. A plurality of driving lines are electrically connected to the pixel circuits and extend in a direction in the display area. A first detour line is disposed in the detour area and is electrically connected to a first driving line. A second detour line is disposed in the detour area. The second detour line is electrically connected to a second driving line and is disposed in a different layer from the first detour line.

Abstract: An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line.

Abstract: Disclosed are magnetic structures, including on-chip inductors comprising laminated layers comprising, in order, a barrier and/or adhesion layer, a antiferromagnetic layer, a magnetic growth layer, a soft magnetic layer, an insulating non-magnetic spacer, a soft magnetic layer, a magnetic growth later, an antiferromagnetic layer. Also disclosed are methods of making such structures.

Abstract: A gate electrode structure and a high voltage semiconductor device having the same are disclosed. The gate electrode structure includes a gate insulation layer pattern disposed on a substrate, a gate electrode disposed on the gate insulating layer pattern and having at least one opening at a first side portion thereof, and at least one insulating pattern disposed in the at least one opening. The high voltage semiconductor device includes a drift region disposed in the substrate adjacent to the first side portion of the gate electrode, a drain region electrically connected with the drift region, and a source region disposed in the substrate adjacent to a second side portion of the gate electrode.

Abstract: An electronic device including a substrate, a semiconductor element disposed on the substrate, and a plurality of guard rings at least partially surrounding the semiconductor element, wherein adjacent guard rings are spaced apart by a substantially uniform distance as measured along an entire length of the guard rings, and at least one of the plurality of guard rings has a flared portion. In an embodiment, at least one of the plurality of guard rings electrically floats. In another embodiment, the plurality of guard rings are disposed at least partially below a primary surface of the substrate. In an embodiment, the electronic device is a high voltage MOSFET or an IGBT.

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.