Abstract: An epitaxial base is provided. The epitaxial base includes a substrate and a carbon nanotube layer. The substrate has an epitaxial growth surface and defines a plurality of grooves and bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer is attached to top surfaces of the plurality of bulges, a second part of the carbon nanotube layer is attached to bottom surfaces of the plurality of grooves, the second part of the carbon nanotube layer is separated from the first part of the carbon nanotube layer, and side surfaces of the plurality of grooves are free of carbon nanotubes.

Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.

Abstract: According to various embodiments, a method for processing a semiconductor region, wherein the semiconductor region comprises at least one precipitate, may include: forming a precipitate removal layer over the semiconductor region, wherein the precipitate removal layer may define an absorption temperature at which a chemical solubility of a constituent of the at least one precipitate is greater in the precipitate removal layer than in the semiconductor region; and heating the at least one precipitate above the absorption temperature.

Abstract: Methods of and apparatuses for processing substrates having carbon-containing material using atomic layer deposition and selective deposition are provided. Methods involve exposing a carbon-containing material on a substrate to an oxidant and igniting a first plasma at a first bias power to modify a surface of the substrate and exposing the modified surface to an inert plasma at a second bias power to remove the modified surface. Methods also involve selectively depositing a second carbon-containing material onto the substrate. ALE and selective deposition may be performed without breaking vacuum.

Abstract: A method of forming a semiconductor device includes forming a dielectric layer over a substrate, and curing the dielectric layer with a first curing process. The first curing process includes providing a first UV light source, filtering the first UV light source with a first filter, the first filter permitting a first electromagnetic radiation within a first pre-determined spectrum to pass through and blocking electromagnetic radiation outside the first pre-determined spectrum, and curing the dielectric layer with the first electromagnetic radiation of the first UV light source.

Abstract: Methods for low-temperature formation of one or more thin-film semiconductor structures on a substrate that include the steps of, forming a (poly)silane layer over a substrate, transforming one or more parts of the (poly)silane layer in one or more thin-film solid-state semiconductor structures, by exposing the one or more parts with light from an

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

Abstract: Techniques herein include forming single or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. A relatively thin portion of mandrel material stretches from a base of mandrels to each other and underneath sidewall spacers and other fill materials, thereby forming a film of mandrel material over an underlying layer, which provides advantages with etch selectivity in a patterning process. Accordingly a multi-line layer is formed with materials having different etch resistivities to be able to selectively etch one or more of the materials to create features where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer.

Abstract: A method of forming spacers for spacer-defined multiple pattering (SDMP), includes: depositing a pattern transfer film by PEALD on the entire patterned surface of a template using halogenated silane as a precursor and nitrogen as a reactant at a temperature of 200° C. or less, which pattern transfer film is a silicon nitride film; dry-etching the template using a fluorocarbon as an etchant, and thereby selectively removing a portion of the pattern transfer film formed on a top of a core material and a horizontal portion of the pattern transfer film while leaving the core material and a vertical portion of the pattern transfer film as a vertical spacer, wherein a top of the vertical spacer is substantially flat; and dry-etching the core material, whereby the template has a surface patterned by the vertical spacer on a underlying layer.

Abstract: An apparatus and method, the apparatus comprising: at least one charged substrate (3); a channel of two dimensional material (5); and at least one floating electrode (7A-C) wherein the floating electrode comprises a first area (10A-C) adjacent the at least one charged substrate, a second area (11A-C) adjacent the channel of two dimensional material and a conductive interconnection (9A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.

Abstract: Systems and methods for improving doping and/or deposition uniformity using a tunable electromagnetic field generation device are provided. In an exemplary embodiment, the system includes a chamber configured to contain a semiconductor wafer, a plasma generator, and a gas inlet, and an exhaust gas outlet. The gas inlet permits a controlled flow of a gas into the chamber through a wall of the chamber and the exhaust gas outlet permits exhausting of gas from the chamber. The system further includes a wafer support structure configured to support the semiconductor wafer during a doping or deposition process and an electromagnetic structure positioned within the chamber and at least partially surrounding an upper surface of the wafer support structure.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: A semiconductor device has an active region that includes a semiconductor layer. A transistor is formed in and above the active region, wherein the transistor has an implanted halo region that includes a halo dopant species and defines a halo dopant profile in the semiconductor layer. An implanted carbon species is positioned in the semiconductor layer, wherein the implanted carbon species defines a carbon species profile in the semiconductor layer that is substantially the same as the halo dopant profile of the implanted halo region in the semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.

Abstract: Improved methods for chemically etching silicon are provided herein. In some embodiments, a method of etching a silicon material includes: (a) exposing the silicon material to a halogen-containing gas; (b) evacuating the halogen-containing gas from the semiconductor processing chamber; (c) exposing the silicon material to an amine vapor to etch a monolayer of the silicon material; (d) evacuating the amine vapor from the semiconductor processing chamber and; (e) optionally repeating (a)-(d) to etch the silicon material to a predetermined thickness.

Abstract: A substrate processing method includes a fluorine-based gas supply step of supplying a fluorine-based gas into a processing chamber where a substrate having a silicon-based film is accommodated, a purge gas supply step of supplying a purge gas for discharging the supplied fluorine-based gas into the processing chamber. The substrate processing method further includes a nitrogen-based gas supply step of supplying a nitrogen-based gas into the processing chamber from which the fluorine-based gas has been discharged. In the substrate processing method, at least in the fluorine-based gas supply step and the purge gas supply step, a temperature of the substrate is maintained at 60° C. or less.

Abstract: A transformer includes: a rotary shaft configured to rotate about a central axis of the rotary shaft as a rotational axis; a primary-side first coil configured to extend around a first axis perpendicular to the central axis; a secondary-side second coil configured to extend around a second axis and supported by the rotary shaft, the second axis being perpendicular to the rotational axis in an area surrounded by the first coil; and a secondary-side third coil configured to extend around a third axis and supported by the rotary shaft, the third axis being perpendicular to the rotational axis and forming a predetermined angle with the second axis in the area.

Abstract: The present disclosure relates to a method of etching an atomic layer, that is capable of simultaneously removing an upper surface and a side surface of an etch subject material layer by heating with a light source of a lamp when removing the atomic layer, thereby easily reducing the planar size even in the case of patterns in the scale of several nanometers.

Abstract: A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.

Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

Abstract: An method of annealing by: providing a substrate having a III-nitride, sapphire, silicon, diamond, gallium arsenide, or silicon carbide surface; depositing a layer of a transition metal nitride directly on the surface; and annealing the substrate at at least 900° C. in an oxygen-free environment. An article having: a substrate having a III-nitride, sapphire, silicon, diamond, gallium arsenide, or silicon carbide surface; and a layer of a transition metal nitride directly on the surface.

Abstract: A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.

Abstract: A method for forming a conductive structure is disclosed, the method comprising the steps of: forming a metallic frame having a plurality of metal parts separated from each other; forming an insulating layer over the top surface or the bottom surface of the plurality of metal parts; and forming a conductive pattern layer on the insulating layer for making electrical connections with at least one portion of the plurality of metal parts.

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

Abstract: Provided is an encapsulation method not causing molding failures such as filling failures and flow marks when collectively encapsulating a large-area silicon wafer or substrate with a resin composition. Specifically, provided is a method for encapsulating a semiconductor element-mounted base material, using a curable epoxy resin composition containing: an epoxy resin (A), a curing agent (B), a pre-gelatinizing agent (C) and a filler (D). The semiconductor element-mounted base material is collectively encapsulated under conditions of (a) molding method: compression molding, (b) molding temperature: 100 to 175° C., (c) molding period: 2 to 20 min and (d) molding pressure: 50 to 350 kN.

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.

Abstract: Provided is a substrate treating apparatus. The substrate treating apparatus comprises: a housing having a treating space therein; a spin head for supporting and rotating a substrate in the treating space; and a chemical supply unit having an injection nozzle for supplying a chemical to the substrate which is supported by the spin head, wherein the injection nozzle comprises a nozzle body, and wherein the nozzle body comprises an inner space for receiving a chemical and minute holes which are connected with the inner space for discharging the chemicals to downward.

Abstract: A substrate cleaning roll that has a cylindrical shape and scrubs a surface of a substrate by rotating about a rotational axis in a longitudinal direction in contact with the substrate, the longitudinal direction being parallel to the surface of the substrate, the substrate cleaning roll including a bevel cleaner at least at one end of the substrate cleaning roll in the longitudinal direction, the bevel cleaner including a sloping surface to be in contact with an outermost edge of a bevel portion at a rim of the substrate when the substrate cleaning roll comes into contact with the substrate and cleans the surface of the substrate.

Abstract: A substrate cleaning apparatus (50) that cleans a substrate (S) includes: circumference supporting members (51) that support and rotate the substrate (S); a sponge (541) having a cleaning surface that is brought into contact with the surface to be cleaned of the substrate (S) being rotated by the circumference supporting members (51), and cleans the surface to be cleaned; an arm (53) that moves the sponge (541) in a radial direction of the substrate (S) while maintaining the cleaning surface in contact with the surface to be cleaned; and a controller (60) that controls the contact pressure of the cleaning surface on the surface to be cleaned. When the sponge (541) is located near the edge of the substrate (S), the controller (60) adjusts the contact pressure to a smaller value than that of when the sponge (541) is located near the center of the substrate (S).

Abstract: Disclosed is a substrate liquid processing method including: performing a liquid processing step of liquid-processing a substrate with a processing liquid, a rinse processing step of rinsing the liquid-processed substrate with a rinse liquid, and a water-repellency processing step of imparting water-repellency to the rinsed substrate with a water-repellent liquid; then, performing a cleaning processing step of cleaning the water-repellency-imparted substrate with a functional liquid; then, performing an alcohol processing step of bringing the cleaned substrate in contact with alcohol; and then, performing a drying processing step of drying the substrate.

Abstract: A substrate stack holder and a container comprising a multiplicity of such substrate stack holders as well as a method for parting a substrate stack.

Abstract: A substrate support assembly includes a ceramic plate having an optical transmittance of at least 60% at a predetermined wavelength, the ceramic plate comprising a top surface and a bottom surface, wherein the top surface is to support a substrate. The substrate support assembly further includes a cooling base coupled to the bottom surface of the ceramic plate. The substrate support assembly further includes a light carrying medium disposed in the base, the light carrying medium to direct light having the predetermined wavelength onto the bottom surface of the ceramic plate, wherein a majority of energy from the light is to pass through the ceramic plate or light carrying medium attached inside holes of ceramic plate and be absorbed by the substrate.

Abstract: Embodiments described herein generally relate to apparatus for processing substrates. The apparatus generally include a process chamber including a lamp housing containing lamps positioned adjacent to an optically transparent window. Lamps within the lamp housing provide radiant energy to a substrate positioned on the substrate support. Temperature control of the optically transparent window is facilitated using cooling channels within the lamp housing. The lamp housing is thermally coupled to the optically transparent window using compliant conductors. The compliant conductors maintain a uniform conduction length irrespective of machining tolerances of the optically transparent window and the lamp housing. The uniform conduction length promotes accurate temperature control. Because the length of the compliant conductors is uniform irrespective of machining tolerances of chamber components, the conduction length is the same for different process chambers.

Abstract: A method and device for coating projecting surfaces of discrete projections of a product substrate that has functional units arranged at least partially in recesses. The method includes the steps of: bringing the projecting surfaces into contact with a coating material that is applied on a carrier substrate, and separating the carrier substrate from the projecting surfaces in such a way that the coating material remains partially on the product substrate. In addition, this invention relates to a corresponding device.

Abstract: The present invention provides various aspects of support for a fabrication facility capable of routine placement and replacement of processing tools in at least a vertical dimension relative to each other.

Abstract: In some embodiments, apparatus and methods are provided for improved handling of lithography masks including a mask inverter that includes a first contact pad dedicated to inverting masks that have not been cleaned; a second contact pad dedicated to inverting masks that have been cleaned; an actuator coupled to the first and second contact pads and operable to invert the first and second contact pads; and a controller coupled to the actuator and operative to control the actuator. Numerous other aspects are provided.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Abstract: A semiconductor device including a substrate having a dielectric layer over the substrate and a first conductive feature disposed within the dielectric layer. A metal nitride material is disposed directly on a top surface of the first conductive feature. A metal oxynitride material is disposed directly on a top surface of the dielectric layer, wherein the metal nitride and the metal oxynitride are coplanar. A second conductive feature is disposed over and interfacing the metal nitride material.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature. A bottom surface of the second conductive feature is between a top surface of the first conductive feature and a bottom surface of the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. The semiconductor device also includes an etch stop layer between the first dielectric layer and the second dielectric layer. A top surface of the etch stop layer is between the top surface and the bottom surface of the first conductive feature.

Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.

Abstract: A wafer is transferred to a holding surface of a chuck table by using a transfer unit having a suction pad. The front side of the wafer is held under suction through a protective tape on the holding surface, and the suction pad is removed from the back side of the wafer. A modified layer is formed on the back side of the wafer along division lines. The wafer is transferred by mounting the wafer held by the suction pad on the holding surface and sandwiching the wafer between the suction pad and the holding surface of the chuck table. A suction force is applied to the holding surface of the chuck table to thereby hold the front side of the wafer through the protective tape on the holding surface of the chuck table under suction, and the suction pad is then removed from the back side of the wafer.

Abstract: A wafer is processed by transferring a wafer to a holding surface of a chuck table by using a suction pad. The front side of the wafer is held through a protective tape on the holding surface under suction. The suction pad is then removed from the back side of the wafer and the back side of the wafer is ground, thereby thinning the wafer and also dividing the wafer into individual device chips. The wafer is mounted on the holding surface while held by the suction pad. The wafer is sandwiched between the suction pad and the holding surface when the suction force is removed. A suction force is applied to the holding surface to thereby hold the front side of the wafer through the protective tape on the holding surface, and the suction pad is then removed from the back side of the wafer.

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Abstract: An embodiment is a method including forming a multi-layer stack over a substrate, the multi-layer stack including alternating first layers and second layers, patterning the multi-layer stack to form a fin, forming an isolation region surrounding the fin, an upper portion of the fin extending above a top surface of the isolation region, forming a gate stack on sidewalls and a top surface of the upper portion of the fin, the gate stack defining a channel region of the fin, and removing the first layers from the fin outside of the gate stack, where after the removing the first layers, the channel region of the fin includes both the first layers and the second layers.