Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

Abstract: A method includes depositing an ESL on a substrate; patterning the ESL such that a first region of the substrate is covered thereby and a second region of the substrate is exposed within an opening of the etch stop layer; depositing a first dielectric layer on the ESL in the first region and on the substrate in the second region; patterning the first dielectric layer to form a first trench through the first dielectric layer in the first region; forming a metal feature in the first trench; depositing a second dielectric layer over the metal feature in the first region and over the first dielectric layer in the second region; and performing a patterning process to form a second trench through the second dielectric layer in the first region, and to form a third trench through the second and first dielectric layers in the second region.

Abstract: An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.

Abstract: An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.

Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

Abstract: A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.

Abstract: Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties. Also provided are methods and apparatus for evaluating and optimizing the films, including methods to evaluate the amount of substrate damage resulting from a particular deposition process and methods to determine the minimum thickness of a protective layer. The methods and apparatus described herein may be used to deposit films on a variety of sensitive materials such as silicon, cobalt, germanium-antimony-tellerium, silicon-germanium, silicon nitride, silicon carbide, tungsten, titanium, tantalum, chromium, nickel, palladium, ruthenium, or silicon oxide.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure includes a conductive structure formed in the trench and on the protection layer. The conductive structure is electrically connected to the conductive pad, and the conductive structure has a concave top surface, and the lowest point of the concave top surface is higher than the top surface of the protection layer.

Abstract: A semiconductor device includes a signal processing circuit configured to generate an output signal, an output pad, an output line connecting the signal processing circuit to the output pad, the output signal from the signal processing circuit being output from the output pad through the output line, a shorting pad formed in the output line, a switch connected between the shorting pad and the output pad, and configured to connect the signal processing circuit to the output pad when the switch is on, and disconnect the signal processing circuit from the output pad when the switch is off, and a wiring line connecting the shorting pad to the output pad.

Abstract: A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.

Abstract: A power semiconductor device module includes a metal baseplate and a plastic housing that together form a tray. Power electronics are disposed in the tray. A plastic cap covers the tray. Electrical press-fit terminals are disposed along the periphery of the tray. Each electrical terminal has a press-fit pin portion that sticks up through a hole in the cap. In addition, the module includes four mechanical corner press-fit anchors disposed outside the tray. One end of each anchor is embedded into the housing. The other end is an upwardly extending press-fit pin portion. The module is manufactured and sold with the press-fit pin portions of the electrical terminals and the mechanical corner anchors unattached to any printed circuit board (PCB). The mechanical anchors help to secure the module to a printed circuit board. Due to the anchors, screws or bolts are not needed to hold the module to the PCB.

Abstract: A power semiconductor device module includes a metal baseplate and a plastic housing that together form a tray. Power electronics are disposed in the tray. A plastic cap covers the tray. Electrical press-fit terminals are disposed along the periphery of the tray. Each electrical terminal has a press-fit pin portion that sticks up through a hole in the cap. In addition, the module includes four mechanical corner press-fit anchors disposed outside the tray. One end of each anchor is embedded into the housing. The other end is an upwardly extending press-fit pin portion. The module is manufactured and sold with the press-fit pin portions of the electrical terminals and the mechanical corner anchors unattached to any printed circuit board (PCB). The mechanical anchors help to secure the module to a printed circuit board. Due to the anchors, screws or bolts are not needed to hold the module to the PCB.

Abstract: A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.

Abstract: A sensor is disclosed. The sensor comprises a first substrate; a second substrate positioned relative to the first substrate; a first electrode located between the first substrate and the second substrate, the first electrode formed on the second substrate; a sensing portion covering at least a part of the first electrode and further covering at least a portion of the second substrate; a pad electrode located between the first substrate and the second substrate, wherein the pad electrode is formed on the second substrate and is electrically coupled to the first electrode; and a bonding pad located between the first substrate and the second substrate, wherein the bonding pad is formed on the first substrate and is electrically coupled to the pad electrode.

Abstract: A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.

Abstract: A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.

Abstract: A manufacturing method of a semiconductor package includes locating a plurality of semiconductor packages on a substrate, forming a resin insulating layer covering the plurality of semiconductor devices, forming grooves, in the resin insulating layer, enclosing each of the plurality of semiconductor devices and reaching the substrate, and irradiating the substrate with laser light in positional correspondence with the grooves to separate the plurality of semiconductor devices from each other.

Abstract: An electronic sub-module includes a leadframe, a semiconductor chip disposed on the leadframe and an encapsulation material disposed on the leadframe and on the semiconductor chip. The semiconductor chip has a first contact pad on a first main face of the semiconductor chip. The sub-module also includes a first contact element on a first main face of the electronic sub-module. The first contact element is electrically connected with the first contact pad. A surface area of the first contact element is greater than a surface area of the first contact pad.

Abstract: An electronic component includes a substrate that has a first principal surface and a second principal surface, a chip that includes a mounting surface on which a plurality of terminal electrodes are formed and a non-mounting surface positioned on a side opposite to the mounting surface and that is arranged at the first principal surface of the substrate in a posture in which the mounting surface faces the first principal surface of the substrate, and a sealing resin that seals the chip at the first principal surface of the substrate so as to expose the non-mounting surface of the chip.

Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

Abstract: A power amplifier module includes a substrate, a power amplifier having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces a principal surface of the substrate, a surface acoustic wave duplexer having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces the principal surface of the substrate, a heat dissipation unit defined on another principal surface of the substrate, a heat dissipation path that connects a connecting portion between the power amplifier and the principal surface to the heat dissipation unit, an insulating resin that covers the power amplifier and the surface acoustic wave duplexer, a conductive shield that covers the insulating resin, and a first conductive unit defined on the second surface of the surface acoustic wave duplexer and electrically connected to the conductive shield.

Abstract: A thermal management structure for a device is provided. The thermal management structure includes electroplated metal, which connects multiple contact regions for a first contact of a first type located on a first side of the device. The electroplated metal can form a bridge structure over a contact region for a second contact of a second type without contacting the second contact. The thermal management structure also can include a layer of insulating material located on the contact region of the second type, below the bridge structure.

Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and a heat-sink thermally coupled to the heat-spreader. The heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor devices.

Abstract: A semiconductor device of a double-side cooling structure having a bus bar electrically connected, and coolers independently arranged on both sides of the semiconductor device for cooling is provided. The semiconductor device includes: a semiconductor chip including an element, and has a first main surface and a second main surface; a sealing resin body having a first surface and a second surface and also having a side surface; a first heatsink arranged facing the first main surface and electrically connected to the first main electrode; and a second heatsink arranged facing the second main surface and electrically connected to the second main electrode. The first heatsink is exposed only to the first surface. The second heatsink is exposed only to the second surface. An exposed surface of a heatsink to be electrically connected to the bus bar has a heat dissipation region, and an electrical connection region.

Abstract: To provide a method for manufacturing a heat dissipation component having excellent heat dissipation properties, in which there is minimal return of warping after the bonding of a circuit board, and to provide a heat dissipation component manufactured using the method. Provided is a method for manufacturing a warped flat-plate-shaped heat dissipation component containing a composite part that comprises silicon carbide and an aluminum alloy, wherein the method for manufacturing the heat dissipation component is characterized in that the heat dissipation component is sandwiched in a concave-convex mold having a surface temperature of at least 450° C. and having a pair of opposing spherical surfaces measuring 7000-30,000 mm in curvature radius, and pressure is applied for 30 seconds or more at a stress of 10 kPa or more such that the temperature of the heat dissipation component reaches at least 450° C.

Abstract: A semiconductor device includes a heat-dissipating base, a first conductive layer bonded to the top surface of the heat-dissipating base, an AlN insulating substrate bonded to the top surface of the first conductive layer, and an electrode terminal having one edge bending to form a bonding edge whose bottom surface faces the top surface of the second conductive layer and is solid-state bonded to a portion of the top surface of the second conductive layer. The crystal grain diameter at the bonded interface of the second conductive layer and electrode terminal is less than or equal to 1 ?m, and indentations from the ultrasonic horn are left in the top surface of the bonding edge.

Abstract: A heat dissipation substrate having the maximum value of the coefficient of linear expansion of 10 ppm/K or less in any direction in a plane parallel to the surface within a temperature range from room temperature to 800° C. as well as a thermal conductivity of 250 W/m·K or higher at 200° C. is produced by densifying an alloy composite of CuMo or CuW composed of Cu and coarse powder of Mo or W and subsequently cross-rolling the same alloy composite.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer.

Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Abstract: A multi-finger transistor includes a circuit suppressing a variation in voltage current distribution. The circuit connects gate fingers (21) to each other, or source fingers (31) to each other in a region which is located outside an active region (11) and on a side where a drain pad (42) is disposed. The multi-finger transistor is configured to be linearly symmetric with respect to a direction of propagation of a signal from a gate pad (22) at the position of the gate pad (22).

Abstract: A shunt strip that includes a plurality of shunts arranged in a grid with each of the shunts spaced from an adjacent shunt by a shunt-gap. A plurality of tabs connect the plurality of shunts and at least one tab is positioned within each shunt-gap. Also, a shunt with a generally parallelepiped shaped body has severed tab portions extending outwardly and downwardly from the body.

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

Abstract: A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

Abstract: A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface and a second surface on the opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer. The resin insulating layers in the build-up wiring layer include a first resin insulating layer that forms the second surface of the build-up wiring layer, and the build-up wiring layer includes first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer.

Abstract: Systems and methods for screening applicants are disclosed herein. A method of screening applicants is performed by a screening server. The server begins by receiving a selection of screening services and an applicant profile that identifies an applicant. The screening continues by generating screening results specified by the selection of screening services based on the applicant profile. A property manager is then notified that the screening results are available for the applicant based upon the applicant profile. The screening results are then provided to the property manager based upon the applicant profile. Based on these screening results, the screener or property manager can make a decision about the applicant and communicate a decision action to the applicant.

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Abstract: A semiconductor device assembly incudes an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The first major surface of the interposer is attached to a packaged semiconductor device. The opening of the interposer exposes the packaged semiconductor device.

Abstract: A semiconductor device includes a first contact receiving a first voltage, a second contact receiving a second voltage, one or more comparing elements comparing the first and second voltages, and one or more setting elements setting one or more parameters of the device in response to a comparison of the first and second voltages. When the first voltage is greater than the second voltage the setting element selects the first voltage as a high voltage, the second voltage as a low voltage, and sets a mode signal to a first value. When the second voltage is greater than the first voltage the setting element selects the first voltage as the low voltage, the second voltage as the high voltage, and sets the mode signal to a second value. The first and second values alter a condition of an electronic component coupled with the device between a first and second state.

Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

Abstract: A method for packaging a semiconductor device used in an electronic apparatus having wireless charging function is provided. The method includes coupling a semiconductor device and a coil over a redistribution layer. The method further includes forming a molding material over the semiconductor device and the coil. The method also includes forming a conductive metal slot over the molding material. An opening is formed on the conductive metal slot for allowing magnetic flux to pass through.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.

Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parrallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer, conformally depositing a barrier layer on the dielectric layer and on sides and a bottom of each one of the plurality of openings, depositing a contact layer on the barrier layer in each one of the plurality of openings, removing a portion of each contact layer from each one of the plurality of openings, and removing a portion of the barrier layer from each one of the plurality of openings, wherein at least the removal of the portion of the barrier layer is performed using an etchant including: (a) a compound selected from group consisting of -azole, -triazole, and combinations thereof; (b) a compound containing one or more peroxy groups; (c) one or more alkaline metal hydroxides; and (d) water.

Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a polymer layer over the semiconductor die and the package layer. The chip package further includes a dielectric layer over the polymer layer. The dielectric layer is substantially made of a semiconductor oxide material. In addition, the chip package includes a conductive feature in the dielectric layer electrically connected to a conductive pad of the semiconductor die.