Patents Issued in November 2, 2017
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Publication number: 20170317081Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: SEOK-HOON KIM, JIN-BUM KIM, KWAN-HEUM LEE, BYEONG-CHAN LEE, CHO-EUN LEE, JIN-HEE HAN, BON-YOUNG KOO
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Publication number: 20170317082Abstract: A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Brent R. Den Hartog, Eric J. Lukes, Matthew J. Paschal, Nghia V. Phan, Raymond A. Richetta, Patrick L. Rosno, Timothy J. Schmerbeck, Dereje G. Yilma
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Publication number: 20170317083Abstract: A semiconductor device is provided as follows. A first buffer layer is disposed on a substrate including NMOS and PMOS regions. A first drain and a first source are disposed on the first buffer layer and have heterogeneous structures. A first channel is disposed between the first drain and the first source. A first gate electrode is disposed on the first channel. A second drain and a second source are disposed on the first buffer layer. A second channel is disposed between the second drain and the second source. The second channel includes a different material from the first channel. A second gate electrode is disposed on the second channel. The first drain, the first source, the first channel and the first gate electrode are disposed in the NMOS region. The second drain, the second source, the second channel and the second gate electrode are disposed in the PMOS region.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventor: Jaehoon LEE
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Publication number: 20170317084Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.Type: ApplicationFiled: April 6, 2017Publication date: November 2, 2017Inventors: Mirco Cantoro, Tae-yong Kwon, Jae-young Park, Dong-hoon Hwang, Han-ki Lee, So-ra You
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Publication number: 20170317085Abstract: A novel semiconductor device is provided. A memory cell MC has a function of supplying a signal corresponding to the product of first data and second data to a wiring BX, and also has a function of supplying a signal corresponding to the product of the first data and third data to a wiring BY. The wiring BX is connected to a plurality of memory cells MC. Each of the plurality of memory cells MC outputs a signal corresponding to the result of the product operation to the wiring BX. The wiring BX has a function of transmitting a signal corresponding to the sum of these signals. The wiring BY is connected to a plurality of memory cells MC. Each of the plurality of memory cells MC outputs a signal corresponding to the result of the product operation to the wiring BY. The wiring BY has a function of transmitting a signal corresponding to the sum of these signals.Type: ApplicationFiled: April 18, 2017Publication date: November 2, 2017Inventor: Yoshiyuki KUROKAWA
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Publication number: 20170317086Abstract: A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.Type: ApplicationFiled: July 3, 2017Publication date: November 2, 2017Applicant: Micron Technology, Inc.Inventor: Hidekazu Nobuto
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Publication number: 20170317087Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, and first and second pass-gate transistors. A first buried contact electrically connects a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and includes a first metal layer formed in a region confined by spacers of a first gate layer and a first electrically conductive path formed at a level below the spacers. A second buried contact electrically connects a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and includes a second metal layer formed in a region confined by spacers of a second gate layer and a second electrically conductive path formed at the level below the spacers.Type: ApplicationFiled: February 21, 2017Publication date: November 2, 2017Inventors: Ying-Yan CHEN, Jui-Yao LAI, Sai-Hooi YEONG, Yen-Ming CHEN
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Publication number: 20170317088Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.Type: ApplicationFiled: September 19, 2016Publication date: November 2, 2017Inventor: Nam Jae LEE
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Publication number: 20170317089Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.Type: ApplicationFiled: November 28, 2016Publication date: November 2, 2017Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
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Publication number: 20170317090Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: ApplicationFiled: June 27, 2017Publication date: November 2, 2017Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Publication number: 20170317091Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: ApplicationFiled: June 27, 2017Publication date: November 2, 2017Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Publication number: 20170317092Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Yen-Ting Ho, Sung-Bin Lin
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Publication number: 20170317093Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.Type: ApplicationFiled: March 31, 2017Publication date: November 2, 2017Inventors: Chunming Wang, Nhan Do
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Publication number: 20170317094Abstract: A semiconductor device having good characteristics without variation and a method of manufacturing the same are provided. A part of a conductive layer for a floating gate is removed by using a spacer insulating film, a first insulating film, and a second insulating film as a mask. A floating gate having a tip portion is formed from the conductive layer for the floating gate, and a part of an insulating layer for a gate insulating film is exposed from the floating gate. The tip portion of the floating gate is further exposed by selectively removing the second insulating film among the second insulating film, the insulating layer for the gate insulating film, and the spacer insulating film.Type: ApplicationFiled: July 12, 2017Publication date: November 2, 2017Applicant: Renesas Electronics CorporationInventor: Hiroki MUKAI
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Publication number: 20170317095Abstract: Some embodiments of the present disclosure relate to method of forming a memory device. In some embodiments, the method may be performed by forming a floating gate over a first dielectric on a substrate. A control gate is formed over the floating gate and first and second spacers are formed along sidewalls of the control gate. The first and second spacers extend past outer edges of an upper surface of the floating gate. An etching process is performed on the first and second spacers to remove a portion of the first and second spacers that extends past the outer edges of the upper surface of the floating gate along an interface between the first and second spacers and the floating gate.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: Chang-Ming Wu, Shih-Chang Liu, Chia-Shiung Tsai, Ru-Liang Lee
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Publication number: 20170317096Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventors: YOOCHEOL SHIN, HONGSOO KIM, JAESUNG SIM
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Publication number: 20170317097Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: Juergen Faul, Frank Jakubowski
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Publication number: 20170317098Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Justin B. Dorhout, David Daycock, Kunal R. Parekh, Martin C. Roberts, Yushi Hu
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Publication number: 20170317099Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang, Akira Goda
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Publication number: 20170317100Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.Type: ApplicationFiled: January 19, 2017Publication date: November 2, 2017Inventors: JU-HYUN KANG, HYUN LEE, MIN-SU KIM, JI-KYUM KIM, JONG-WOO KIM
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Publication number: 20170317101Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Masaki TAMARU, Kazuyuki NAKANISHI, Hidetoshi NISHIMURA
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Publication number: 20170317102Abstract: Systems and methods herein relate to the fabrication of a single-crystal flexible semiconductor template that may be attached to a semiconductor device. The template fabricated comprises a plurality of single crystals grown by lateral epitaxial growth on a seed layer and bonded to a flexible substrate. The layer grown has portions removed to create windows that add to the flexibility of the template.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Applicant: University of Houston SystemInventor: Jae-Hyun Ryou
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Publication number: 20170317103Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Raj Verma Purakh, Shaoqiang Zhang, Rui Tze Toh
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Publication number: 20170317104Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.Type: ApplicationFiled: December 15, 2016Publication date: November 2, 2017Inventors: Yu-Gwang JEONG, Hyun Min CHO, Su Bin BAE, Shin II CHOI, Sang Gab KIM
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Publication number: 20170317105Abstract: Provided are a display device its method of manufacturing. The device includes a base; first and second thin-film transistors (TFT) on the base, adjacent to each; an organic layer covering the first and second TFT, comprising a first and second opening overlapping the drain electrodes of the first and second TFT, respectively; a common electrode on the organic layer comprising a common electrode opening overlapping the first opening and another common electrode opening overlapping the second opening; an insulating layer on a bump spacer which is on the common electrode; a first and second pixel electrode on the insulating layer overlapping the common electrode and electrically connected to the first and second TFT, respectively, wherein a minimum distance between the bump spacer and the common electrode opening is substantially equal to a minimum distance between the bump spacer and the other common electrode opening.Type: ApplicationFiled: January 23, 2017Publication date: November 2, 2017Inventors: Seul Ki KIM, Seung Ha CHOI, Hyun KIM, Yun Seok HAN
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Publication number: 20170317106Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.Type: ApplicationFiled: November 28, 2016Publication date: November 2, 2017Applicants: STMicroelectronics (Rousset 2) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Franck Arnaud, Gregory Bidal, Dominique Golanski, Emmanuel Richard
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Publication number: 20170317107Abstract: Displays can be fabricated using driver transistors formed with high quality semiconductor channel materials, and switching transistors formed with low quality semiconductor channel materials. The driver transistors can require high forward current to drive emission of the OLED pixels, but might not require very low leakage current. The switching transistors can require low leakage current to allow the pixel capacitor to retain the signal level for accurate OLED device emission, preventing abnormal displays or cross talks.Type: ApplicationFiled: July 3, 2017Publication date: November 2, 2017Inventors: Ananda H. Kumar, Srinivas H. Kumar, Tue Nguyen
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Publication number: 20170317108Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.Type: ApplicationFiled: July 10, 2017Publication date: November 2, 2017Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
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Publication number: 20170317109Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Chih-Hao WANG, Ching-Wei TSAI, Kuo-Cheng CHING, Jhon Jhy LIAW, Wai-Yi LIEN
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Publication number: 20170317110Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.Type: ApplicationFiled: March 29, 2017Publication date: November 2, 2017Inventors: Hyun Sup LEE, Jung Hun NOH, Keun Kyu SONG, Sang Hee JANG, Byung Seok CHOI
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Publication number: 20170317111Abstract: A semiconductor device capable of retaining data for a long time is provided. A first transistor and a second transistor having different electrical characteristics from those of the first transistor are provided over the same layer without an increase in the number of manufacturing steps.Type: ApplicationFiled: April 24, 2017Publication date: November 2, 2017Inventors: Yoshinori ANDO, Shinpei MATSUDA, Yuki HATA
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Publication number: 20170317112Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
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Publication number: 20170317113Abstract: A method is provided for manufacturing a thin film transistor (TFT) backplate that includes a switch TFT and a drive TFT. The method is conducted such that each of the switch TFT and the drive TFT manufactured therewith includes a source electrode/a drain electrode and a gate electrode, and also includes an etching stopper layer, a semiconductor layer, and gate isolation layer that are disposed between the source electrode/the drain electrode and the gate electrode to form a TFT structure. The gate isolation layers of the switch TFT and drive TFT are formed of different materials, such as SiOx and Al2O3, or SiOx and SiNx, or Al2O3 and a mixture of SiNx and SiOx, such that electrical properties of the switch TFT and the drive TFT are made different.Type: ApplicationFiled: July 20, 2017Publication date: November 2, 2017Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventors: Xiaowen LV, Chihyuan TSENG, Chihyu SU, Hejing ZHANG
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Publication number: 20170317114Abstract: A display device may include a first base substrate, a light-blocker, a gate wiring, a semiconductor member, a data wiring, and a drain electrode. The light-blocker is disposed on the first base substrate, and includes a light-blocking line extending in a first direction and a light-blocking protrusion protruding from the light-blocking line in a second direction different from the first direction. The gate wiring includes a gate line extending in the first direction and a gate electrode protruding from the gate line. The semiconductor member overlaps the gate electrode and includes a source region, a drain region, and a channel region. The data wiring extends in the second direction and is electrically connected to the source region. The drain electrode is electrically connected to the drain region. An edge of the gate electrode in the first direction is located in an overlap area between the drain region and the light-blocking protrusion.Type: ApplicationFiled: April 27, 2017Publication date: November 2, 2017Inventors: Jung Hun NOH, Keun Kyu SONG
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Publication number: 20170317115Abstract: A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.Type: ApplicationFiled: July 16, 2017Publication date: November 2, 2017Inventors: Shimin Ge, Hejing Zhang, Chihyuan Tseng, Chihyu Su, Wenhui Li, Longqiang Shi, Xiaowen Lv
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Publication number: 20170317116Abstract: The present application provides an electrostatic discharge guard structure for photonic platform based photodiode systems. In particular this application provides a photodiode assembly comprising: a photodiode (such as a Si or SiGe photodiode); a waveguide (such as a silicon waveguide); and a guard structure, wherein the guard structure comprises a diode, extends about all or substantially all of the periphery of the Si or SiGe photodiode and allows propagation of light from the silicon waveguide into the Si or SiGe photodiode.Type: ApplicationFiled: September 19, 2016Publication date: November 2, 2017Applicant: Huawei Technologies Co., Ltd.Inventors: Dritan CELO, Dominic John GOODWILL, Eric BERNIER
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Publication number: 20170317117Abstract: A photoelectric conversion apparatus that includes a pixel region having photoelectric conversion elements includes a semiconductor layer having first and second surfaces, and the photoelectric conversion elements are disposed between the first and second surfaces. With a virtual plane extending along the second surface between the first and second surfaces being a third plane, the pixel region includes an element isolating portion constituted by an insulator disposed closer to the first surface than the third plane, and first and second isolating portions constituted by grooves provided in the semiconductor layer to pass through the third plane. The first isolating portion overlaps the element isolating portion in a normal direction to the third plane. An end of the second isolating portion on a side on the first surface is closer to the second surface than an end of the first isolating portion on a side on the first surface is.Type: ApplicationFiled: April 24, 2017Publication date: November 2, 2017Inventors: Nobutaka Ukigaya, Hideshi Kuwabara
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Publication number: 20170317118Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
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Publication number: 20170317119Abstract: A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventor: Takekazu Shinohara
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Publication number: 20170317120Abstract: An image sensor is provided which is capable of holding data for one frame period or longer and conducting a difference operation with a small number of elements. A photosensor is provided in each of a plurality of pixels arranged in a matrix, each pixel accumulates electric charge in a data holding portion for one frame period or longer, and an output of the photosensor changes in accordance with the electric charge accumulated in the data holding portion. As a writing switch element for the data holding portion, a transistor with small leakage current (sufficiently smaller than 1×10?14 A) is used. As an example of the transistor with small leakage current, there is a transistor having a channel formed in an oxide semiconductor layer.Type: ApplicationFiled: May 16, 2017Publication date: November 2, 2017Inventor: Takayuki IKEDA
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Publication number: 20170317121Abstract: A solid-state imaging apparatus, comprising a first semiconductor region of a first conductivity type provided on a substrate by an epitaxial growth method, a second semiconductor region of the first conductivity type provided on the first semiconductor region, and a third semiconductor region of a second conductivity type provided in the second semiconductor region so as to form a pn junction with the second semiconductor region, wherein the first semiconductor region is formed such that an impurity concentration decreases from a side of the substrate to a side of the third semiconductor region, and an impurity concentration distribution in the second semiconductor region is formed by an ion implantation method.Type: ApplicationFiled: June 29, 2017Publication date: November 2, 2017Inventors: Takashi Moriyama, Masaaki Minowa, Takeshi Ichikawa, Masahiro Ogawa
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Publication number: 20170317122Abstract: An image sensor is described having a pixel array. The pixel array has a unit cell that includes visible light photodiodes and an infra-red photodiode. The visible light photodiodes and the infra-red photodiode are coupled to a particular column of the pixel array. The unit cell has a first capacitor coupled to the visible light photodiodes to store charge from each of the visible-light photodiodes. The unit cell has a readout circuit to provide the first capacitor's voltage on the particular column. The unit cell has a second capacitor that is coupled to the infra-red photodiode through a first transfer gate transistor to receive charge from the infra-red photodiode during a time-of-flight exposure. The first capacitor is coupled to the infra-red photodiode through a second transfer gate transistor to receive charge from the infra-red photodiode during the time-of-flight exposure.Type: ApplicationFiled: July 20, 2017Publication date: November 2, 2017Inventors: Chung Chun Wan, Boyd Albert Fowler
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Publication number: 20170317123Abstract: Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Feng-Chi Hung, Jhy-Jyi Sze, Shou-Gwo Wuu
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Publication number: 20170317124Abstract: An image sensor package includes an image sensor with a pixel array disposed in a semiconductor material. A first transparent shield is adhered to the semiconductor material, and the pixel array is disposed between the semiconductor material and the first transparent shield. The image sensor package further includes a second transparent shield, where the first transparent shield is disposed between the pixel array and the second transparent shield. A light blocking layer is disposed between the first transparent shield and the second transparent shield, and the light blocking layer is disposed to prevent light from reflecting off edges of the first transparent shield into the pixel array.Type: ApplicationFiled: February 10, 2017Publication date: November 2, 2017Inventors: Chia-Chun Miao, Yin Qian, Chao-Hung Lin, Chen-Wei Lu, Dyson H. Tai, Ming Zhang, Jin Li
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Publication number: 20170317125Abstract: This lensless imaging system comprises a receiving support configured to receive a sample, a light source configured to emit a light beam illuminating the sample in an illumination direction, the light source including a diode and a diaphragm, the diaphragm being positioned between the diode and the receiving support in the lighting direction, and a matrix photodetector configured to acquire at least one image of the sample, each image being formed by radiation emitted by the illuminated sample and including at least one elementary diffraction pattern, the receiving support being positioned between the light source and the matrix photodetector in the illumination direction. The system further comprises a light diffuser positioned between the diode and the diaphragm.Type: ApplicationFiled: November 9, 2015Publication date: November 2, 2017Applicant: Commissariat Á L'Énergie Atomique Et Aux Énergies AlternativesInventor: Thomas BORDY
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Publication number: 20170317126Abstract: Fabricating optical devices can include mounting a plurality of singulated lens systems over a substrate, adjusting a thickness of the substrate below at least some of the lens systems to provide respective focal length corrections for the lens systems, and subsequently separating the substrate into a plurality of optical modules, each of which includes one of the lens systems mounted over a portion of the substrate. Adjusting a thickness of the substrate can include, for example, micro-machining the substrate to form respective holes below at least some of the lens systems or adding one or more layers below at least some of the lens systems so as to correct for variations in the focal lengths of the lens systems.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Applicant: Heptagon Micro Optics Pte. Ltd.Inventors: Stephan Heimgartner, Ville Kettunen, Nicola Spring, Alexander Bietsch, Mario Cesana, Hartmut Rudmann, Jukka Alasirnio, Robert Lenart
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Publication number: 20170317127Abstract: The present technology relates to a solid-state imaging device capable of preventing defects in the appearance thereof, a camera module, and an electronic apparatus. The solid-state imaging device to be provided includes: a semiconductor substrate having pixels formed therein, the pixels each including a photoelectric conversion element; and on-chip lenses formed above the semiconductor substrate, the on-chip lenses corresponding to the pixels. The area in which the on-chip lenses are formed is extended to a peripheral area outside an imaging area formed with the pixels. The present technology can be applied to solid-state imaging devices, such as CMOS image sensors.Type: ApplicationFiled: October 22, 2015Publication date: November 2, 2017Inventor: KOSUKE HAREYAMA
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Publication number: 20170317128Abstract: A solid-state imaging device includes: a first lens layer; and a second lens layer, wherein the second lens layer is formed at least at a periphery of each first microlens formed based on the first lens layer, and the second lens layer present at a central portion of each of the first microlenses is thinner than the second lens layer present at the periphery of the first microlens or no second lens layer is present at the central portion of each of the first microlenses.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Applicant: Sony CorporationInventors: Yoichi Ootsuka, Tomoyuki Yamashita, Kiyotaka Tabuchi, Yoshinori Toumiya, Akiko Ogino
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Publication number: 20170317129Abstract: Provided is an image-capturing unit including an image-capturing chip that includes a first surface having a pixel and a second surface that is on an opposite side of the first surface and has provided thereon an output section that outputs a pixel signal read from the pixel; a transparent substrate that is arranged facing the first surface and includes a wire pattern; a mounting substrate that is arranged facing the second surface and supports the image-capturing chip; and a relay section that is arranged on the mounting substrate and relays, to the wire pattern, the pixel signal output from the output section. Also provided is an image-capturing apparatus including the image-capturing unit described above.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Applicant: NIKON CORPORATIONInventor: Tomohisa ISHIDA
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Publication number: 20170317130Abstract: An image pickup apparatus includes a silicon layer, a wire layer that contains an insulator having a lower dielectric constant than silicon oxide, a cover glass that covers a light receiving portion on a light receiving surface of the silicon layer, and a silicon substrate that covers a back surface of the wire layer, in which a guard ring is formed along an outer edge on the wire layer, a through-hole having a bottom surface that is configured by an electrode pad configured by a conductor of the wire layer and having an outer periphery portion in contact with the silicon layer over a whole periphery is provided in a region of the silicon layer that is not covered with the cover glass, and the insulator of the wire layer is not exposed to an inner surface of the through-hole.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Applicant: OLYMPUS CORPORATIONInventor: Kazuhiro YOSHIDA