Abstract: Provided is a solid-state imaging device that includes: first pixels provided with a color filter layer having a transmission band in a visible light wavelength region on a light-receiving surface of a first light-receiving element; second pixels provided with an infrared pass filter layer having a transmission band in an infrared wavelength region on a light-receiving surface of a second light-receiving element; and an infrared cut filter layer that is provided on a lower surface side of the color filter layer and transmits light in the visible light wavelength region by blocking light in the infrared wavelength region; wherein the infrared cut filter layer is formed with an infrared-absorbing composition containing a compound having a maximum absorption wavelength in an wavelength range of from 600 to 2000 nm, and at least one kind selected from a binder resin and a polymerizable compound.

Abstract: Provided is a solid-state imaging device that includes: a first pixel provided with a color filter layer having a transmission band in a visible light wavelength region on a light-receiving surface of a first light-receiving element; a second pixel provided with an infrared pass filter layer having a transmission band in an infrared wavelength region on a light-receiving surface of a second light-receiving element; an infrared cut filter layer that is provided on a position overlapping with the color filter layer and transmits light in the visible light wavelength region by blocking light in the infrared wavelength region; and a cured film provided in contact with the infrared cut filter layer.

Abstract: The present invention is directed towards a moisture resistant radiation detector core assembly which was constructed by first assembling the photon-electron conversion layer, integrated circuit and the connection elements between and then encapsulating the whole assembly. This provides improved moisture barrier properties, since the encapsulation also covers the connection elements and does not have to be opened to apply the electrical connections, as is done for known radiation detector core assemblies.

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Abstract: A light absorption apparatus includes a substrate, a light absorption layer above the substrate on a first selected area, a silicon layer above the light absorption layer, a spacer surrounding at least part of the sidewall of the light absorption layer, an isolation layer surrounding at least part of the spacer, wherein the light absorption apparatus can achieve high bandwidth and low dark current.

Abstract: Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer.

Abstract: A method makes an electromagnetic radiation detecting device including at least one thermal detector with an absorbent membrane suspended above a substrate, intended to be located in a sealed cavity. The method includes depositing, on the substrate, a gettering metallic layer including a metallic material with a gettering effect; depositing a carbonaceous sacrificial layer of amorphous carbon on the gettering metallic layer; depositing at least one sacrificial mineral layer on the carbonaceous sacrificial layer; chemical-mechanical planarization of the sacrificial mineral layer; fabricating the thermal detector so that the absorbent membrane is produced on the sacrificial mineral layer; removing the sacrificial mineral layer; and removing the carbonaceous sacrificial layer.

Abstract: A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.

Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

Abstract: A memory device includes at least one memory cell which contains a resistive memory element having a conductive metal oxide located between a first electrode and a second electrode. The conductive metal oxide has a concentration of free electrons in thermodynamic equilibrium in a range from 1.0×1020/cm3 to 1.0×1021/cm3. A method of operating the memory device includes redistributing electron density to set and reset the device. An oxide barrier layer may be located between the conductive metal oxide and the second electrode.

Abstract: An apparatus for high density memory with integrated logic. Specifically, a three terminal resistive random access memory (ReRAM) device having Schottky barriers that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes an insulating layer, a source region disposed on the insulating layer, a drain region disposed on the insulating layer, a binary or complex oxide memory material, a gate dielectric layer, and a gate electrode. As voltage is applied the Schottky barrier breaks down leading to the formation of a conductive anodic filament (CAF). The CAF is non-volatile and short-circuits the reverse-biased barrier thus keeping the device in a low resistance state. Removing the CAF switches the device back to a high resistance state. Thus, a new type of semiconductor device advantageously combines computation and memory further providing for very high density NAND chains.

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device, and at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion. The resistive memory device includes terminals configured to couple the active region to associated electrical contacts.

Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.

Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

Abstract: A touch display device includes a display panel including a plurality of first pixels and a plurality of second pixels alternately disposed along a first direction, and a touch screen layer disposed on the display panel, the touch screen layer including a plurality of first touch electrodes having a zigzag shape and disposed between one of the first and second pixels along a second direction crossing the first direction, in which a first pixel of the first pixels and a second pixel of the second pixels have different sizes from each other, and a first distance from a first touch electrode of the first touch electrodes to the first pixel is different from a second distance from the first touch electrode to the second pixel.

Abstract: Embodiments of the present invention generally relate to a touch sensible organic light emitting device. The organic light emitting device according to an exemplary embodiment of the present invention comprises: a substrate; a thin film transistor disposed on the substrate; an organic light emitting element connected to the thin film transistor and receiving a data voltage; a plurality of encapsulation thin films disposed on the organic light emitting element, and encapsulating the thin film transistor and the organic light emitting element; a planarization layer disposed on the encapsulation thin film; and a touch sensor disposed on the planarization layer.

Abstract: The invention provides a manufacturing method of a pixel structure of an organic light-emitting diode display panel. First transparent anodes located in first pixel regions and fifth pixel regions, second transparent anodes located in second pixel regions and sixth pixel regions, and third transparent anodes located in third pixel regions and fourth pixel regions are formed on a substrate. A first organic light-emitting layer is formed inside the third pixel regions and the fourth pixel regions via a first fine metal mask. A second organic light-emitting layer is formed inside the fifth pixel regions, the sixth pixel regions, the first pixel regions, and the second pixel regions via a second fine metal mask. First cathodes, second cathodes, and third cathodes are formed on the substrate.

Abstract: An organic electroluminescence device according to one aspect of the present invention includes: a base material having a top surface on which a recess is provided; a reflective layer provided along at least a surface of the recess; a filling layer filled inside the recess via the reflective layer, the filling layer having light transmissivity; a first electrode provided at least on an upper layer side of the filling layer, the first electrode having light transmissivity; an organic layer provided on an upper layer side of the first electrode, the organic layer including at least a light emitting layer; and a second electrode provided on an upper layer side of the organic layer, the second electrode having light transmissivity, wherein a coloring material is mixed into the filling layer.

Abstract: Provided is a light-emitting device which can emit monochromatic lights with high color purity due to a microcavity effect and which can provide a white light with a broad spectrum when the monochromatic lights are combined. The light-emitting device has a red-, green-, blue-, and yellow-emissive light-emitting elements each of which has a reflective electrode and a semi-transmissive and semi-reflective electrode. The red-, green-, blue-, and yellow-emissive light-emitting elements have the same structure other than the reflective electrode and a layer in contact with the reflective electrode to selectively emit red, green, blue, and yellow lights, respectively. Red, green, and blue color filters are also provided over the red-, green-, blue-, light-emitting elements, respectively. An EL layer is commonly shared by the red-, green-, blue-, and yellow-emissive light-emitting elements, and the semi-transmissive and semi-reflective electrode covers an edge portion of the EL layer.

Abstract: Discussed is an organic light emitting display device including a plurality of pixels, where red sub pixels and blue sub pixels of adjacent pixels are aligned in a first direction and are also aligned in a second direction, the second direction being a direction that intersects the first direction. Also, the green pixels of adjacent pixels are aligned in the first direction and are also aligned in the second direction. And the at least one green sub pixel of each pixel is disposed between the at least one red sub pixel and the at least one blue sub pixel of the each pixel, and the at least one green sub pixel is offset from the at least one red sub pixel and the at least one blue sub pixel in the first direction and the second direction in the each pixel.

Abstract: A novel display device that is highly convenient or reliable is provided. The display device includes a first display element, a second display element, a first transistor, a second transistor, and a third transistor. The first display element includes a liquid crystal layer. The second display element includes a light-emitting layer. The first transistor has a function of selecting the first display element. The second transistor has a function of selecting the second display element. The third transistor has a function of controlling the driving of the second display element. The first transistor and the second transistor are formed over the same surface. The third transistor is formed above the first transistor and the second transistor and includes one of a source electrode and a drain electrode of the second transistor as a gate electrode.

Abstract: An embodiment of the present disclosure provides an organic light emitting diode array substrate, an organic light emitting diode display and a method for manufacturing the same. Specifically, the organic light emitting diode array substrate comprises a substrate; a reflecting layer provided on the substrate; a photoresist layer provided on the reflecting layer, and a pixel electrode layer provided on the photoresist layer.

Abstract: A display device includes: a display substrate having an active area, which includes a pixel array, and a peripheral area around the active area; a driving chip on the display substrate; and a conductive combination member connecting the display substrate to the driving chip, wherein the display substrate includes: a first signal line in the peripheral area to transfer a driving signal from the driving chip to the active area, the first signal line including a first connection pad; a second connection pad at a different layer from the first connection pad and overlapping at least a portion of the first signal line; and a contact member contacting the first connection pad, the second connection pad, and the conductive combination member.

Abstract: An organic light-emitting display device and a method of manufacturing the same are disclosed and these improve electrical connection between a cathode and an auxiliary electrode in order to reduce the resistance of the cathode that covers a plurality of sub-pixels, and may prevent lateral current leakage using the same structure.

Abstract: Disclosed are a backplane substrate which secures sufficient storage capacitance even when using small sub-pixels in a structure having very high resolution, and an organic light emitting diode display using the same. The backplane substrate includes storage capacitors including a first storage electrode, a second storage electrode partially overlapping the first storage electrode, a second storage connection electrode overlapping the first and second storage electrodes and connected to the second storage electrode at a first node, and a first storage connection electrode overlapping the second storage connection electrode and connected to the first storage electrode at a second node at which the first and second storage electrodes do not overlap each other, in a storage capacitor region defined by intersecting a scan line, a first voltage line and a data line at each sub-pixel.

Abstract: An organic light emitting display (OLED) device includes an organic light emitting diode having an anode and a cathode. The organic light emitting diode is configured to receive a reference voltage. A control transistor includes a first control electrode and a first semiconductor active layer. The control transistor is configured to receive a control signal. A driving transistor includes a second control electrode that is electrically connected to the control transistor, an input electrode that is configured to receive a power voltage, an output electrode that is electrically connected to the anode of the organic light emitting diode, and a second semiconductor active layer that includes a different material from that of the first semiconductor active layer. A shielding electrode is disposed on the second semiconductor active layer, overlapping the driving transistor, and configured to receive the power voltage.

Abstract: A display panel and an electronic device are provided. The display panel comprises a base substrate including a display region and a border region surrounding the display region, wherein the border region includes an encapsulation region; a plurality of display units disposed in the display region; an encapsulation member disposed in the border region; a plurality of wires disposed in the border region; and a cover substrate arranged opposite to the base substrate. The display units and the wires are disposed between the base substrate and the cover substrate, the encapsulation member is disposed in the encapsulation region and configured to bond and fix the base substrate to the cover substrate, and at least one of the wires is disposed in the encapsulation region.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a scan line extending in a first direction; a data line crossing the scan line and transmitting a data signal; a driving voltage line crossing the scan line and transmitting a driving voltage; a conductive member including a portion connected to the driving voltage line and overlapping the data line, wherein a first insulation layer is interposed between the conductive member and the data line; and a control line including a plurality of main line portions each extending in the first direction, and a detour portion that is located between two of the plurality of main line portions that are adjacent one another in a plan view, wherein the detour portion connects the two adjacent main line portions together, wherein a part of the detour portion is located between the conductive member and the driving voltage line in the plan view.

Abstract: A semiconductor device including a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer includes a first source region, a first drain region, a second source region, and a second drain region connected to a channel region. The first gate electrode is disposed below the semiconductor layer. The first gate electrode is insulated from the semiconductor layer. The first gate electrode at least partially overlaps the shared channel region. The second gate electrode is disposed above the semiconductor layer. The second gate electrode is insulated by a second gate insulating layer. The second gate electrode at least partially overlaps the channel region.

Abstract: A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor.

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.

Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.

Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.

Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, having a first principal surface and a second principal surface, a silicon carbide semiconductor layer of the first conductivity type, disposed on the first principal surface, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the second principal surface and forming an ohmic junction with the semiconductor substrate. The semiconductor device satisfies 0.13?Rc/Rd, where Rc is the contact resistance between the second principal surface and the second electrode at room temperature and Rd is the resistance of the silicon carbide semiconductor layer in a direction normal to the first principal surface at room temperature.

Abstract: A silicon carbide single-crystal substrate having a first main surface angled off relative to a {0001} plane, and a first peripheral edge provided continuously with the first main surface is prepared. A silicon carbide epitaxial layer is formed on the first main surface. The silicon carbide epitaxial layer has a second main surface in contact with the first main surface, a third main surface opposite to the second main surface, and a second peripheral edge provided continuously with each of the second main surface and the third main surface. A peripheral region including the first peripheral edge and the second peripheral edge is removed. The silicon carbide epitaxial layer has a thickness of not less than 50 ?m in a direction perpendicular to the third main surface.

Abstract: Provided is a semiconductor device including a semiconductor substrate; a gate trench portion formed in a front surface of the semiconductor substrate; a dummy trench portion formed in the front surface of the semiconductor substrate; and a first front-surface-side electrode that includes metal and is formed above the front surface of the semiconductor substrate. The gate trench portion includes a gate trench formed in the front surface of the semiconductor substrate; a gate conducting portion formed inside the gate trench; and a gate insulating portion that is formed above the gate conducting portion inside the gate trench and provides insulation between the gate conducting portion and the first front-surface-side electrode. The dummy trench portion includes a dummy trench formed in the front surface of the semiconductor substrate; and a dummy conducting portion that is formed inside the dummy trench and contacts the first front-surface-side electrode.

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

Abstract: Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

Abstract: An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.