Abstract: A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.

Abstract: To provide a semiconductor device which has transistor characteristics with little variation and includes an oxide semiconductor. The semiconductor device includes an insulating film over a conductive film and an oxide semiconductor film over the insulating film. The oxide semiconductor film includes a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer. The energy level of a bottom of a conduction band of the second oxide semiconductor layer is lower than those of the first and third oxide semiconductor layers. An end portion of the second oxide semiconductor layer is positioned on an inner side than an end portion of the first oxide semiconductor layer.

Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.

Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

Abstract: Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

Abstract: A layer structure for a thin-film solar cell and production method are provided. The layer structure for the thin-film solar cell includes a photovoltaic absorber layer doped, at least in a region which borders a surface of the photovoltaic absorber layer, with at least one alkali metal. The layer structure has an oxidic passivating layer on the surface of the photovoltaic absorber layer, which is designed to protect the photovoltaic absorber layer from corrosion.

Abstract: A method for forming a back contact on an absorber layer in a photovoltaic device includes forming a two dimensional material on a first substrate. An absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) is grown over the first substrate on the two dimensional material. A buffer layer is grown on the absorber layer on a side opposite the two dimensional material. The absorber layer is exfoliated from the two dimensional material to remove the first substrate from a backside of the absorber layer opposite the buffer layer. A back contact is deposited on the absorber layer.

Abstract: A PV module includes a transparent substrate, a first solar cell unit, a crystalline silicon solar cell, and a spacer. The first solar cell unit is between the transparent substrate and the crystalline silicon solar cell, and the first solar cell unit includes a first electrode, a second electrode, and a I-III-VI semiconductor layer between the first electrode and the second electrode. The I-III-VI semiconductor layer includes at least gallium (Ga) and sulfur (S), and the energy gap thereof is more than that of crystalline silicon. Moreover, the crystalline silicon solar cell and the first solar cell unit are separated by the spacer.

Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.

Abstract: A solar cell module includes a plurality of cell strings having a plurality of solar cells, each solar cell having a semiconductor substrate, and a first conductivity-type electrode and a second conductivity-type electrode provided on a first surface of the semiconductor substrate, an interconnector electrically connecting a first conductivity-type electrode of a first solar cell, among the plurality of solar cells included in the plurality of cell strings, and a second conductivity-type electrode of a second solar cell adjacent to the first solar cell in a first direction, to connect the first and second solar cells in series, and a first shield positioned on a front surface of the interconnector between the first and second solar cells, and extending in a second direction crossing the first direction.

Abstract: A method for assembling a solar module structure comprises patterning a frontside and a backside of a double-sided printed circuit board coated with metallic foils according to desired frontside and backside interconnect layouts; applying a first coating layer to the rear side of a plurality of three-dimensional thin-film solar cells, each three-dimensional thin-film solar cell comprising: a three-dimensional thin-film solar cell substrate comprising emitter junction regions and doped base regions; emitter metallization and base metallization regions; the three-dimensional thin-film solar cell substrate comprising a plurality of single-aperture unit cells; placing the three-dimensional thin-film solar cells on the frontside of the double-sided printed circuit board; preparing a solar module assembly, comprising: a glass layer; a top encapsulant layer; the plurality of three-dimensional thin-film solar cells on the frontside of the double-sided printed circuit board; a rear encapsulant layer; a protective back

Abstract: Optically transmissive UV solar cells may be coupled to glass substrates, for example windows, in order to generate electricity while still providing suitable optical behavior for the window. The UV solar cells may be utilized to power electrochromic components coupled to the window to adjust or vary the transmissivity of the window. The UV solar cells may utilize a Schottky ZnO/ZnS heterojunction.

Abstract: Disclosed herein are embodiments of a coated type-I quantum dot comprising a core and a shell, and a silica layer, and a method for making the quantum dot. The quantum dot may be a thick-shelled quantum dot. Also disclosed are embodiments of a composition comprising one or more coated quantum dots and a polymer. The composition may be a luminescent solar concentrator. Device comprising the composition are disclosed. The device may comprise the composition, such as a luminescent solar concentrator, applied to a substrate, such as glass. The device may be a window or a solar module. Also disclosed is a method of applying the composition to the substrate to form a thin film luminescent solar concentrator.

Abstract: A solar power generator for generating electricity from sunlight in which a photovoltaic panel is provided so as to be oriented for minimising exposure to direct sunlight. A heat absorber is provided, together with a filter for receiving sunlight and filtering ultraviolet and visible light components to the photovoltaic panel and infrared components to the heat absorber. The heat absorber may include a thermoelectric module.

Abstract: A hybrid photovoltaic device (1) comprising a thin film solar cell (2) disposed in a first layer (21) comprising an array of vertically aligned nanowires (25), said nanowires having a junction with a first band gap corresponding to a first spectral range. The nanowires (25) form absorbing regions, and non-absorbing regions are formed between the nanowires. A bulk solar cell (3) s disposed in a second layer (31), positioned below the first layer (21), having a junction with a second band gap, which is smaller than said first band gap and corresponding to a second spectral range. The nanowires are provided in the first layer with a lateral density selected a such that a predetermined portion of an incident photonic wave-front will pass through the non-absorbing regions without absorption in the first spectral range, into the bulk solar cell for absorption in both the first spectral range and the second spectral range.

Abstract: Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.

Abstract: An apparatus for the manufacture of at least two arrangements of solar cell pieces is provided. The apparatus includes at least one positioning device configured for positioning two or more solar cell pieces on a support device for forming the at least two arrangements, wherein the apparatus is configured to allocate the two or more solar cell pieces to a respective arrangement of the at least two arrangements based on one or more properties of the two or more solar cell pieces.

Abstract: The present disclosure provides methods of fabricating a multijunction solar cell panel in which one or more of the steps are performed using an automated process. In some embodiments, the automated process uses machine vision.

Abstract: In various embodiments, photovoltaic devices incorporate discontinuous passivation layers (i) disposed between a thin-film absorber layer and a partner layer, (ii) disposed between the partner layer and a front contact layer, and/or (iii) disposed between a back contact layer and the thin-film absorber layer.

Abstract: A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with one or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe.

Abstract: There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved.

Abstract: An optoelectronic semiconductor chip has a semiconductor body and a substrate on which the semiconductor body is disposed. The semiconductor body has an active region disposed between a first semiconductor layer of a first conductor type and a second semiconductor layer of a second conductor type. The first semiconductor layer is disposed on the side of the active region facing the substrate. The first semiconductor layer is electrically conductively connected to a first termination layer that is disposed between the substrate and the semiconductor body. An encapsulation layer is disposed between the first termination layer and the substrate and, in plan view of the semiconductor chip, projects at least in some regions over a side face which delimits the semiconductor body.

Abstract: A semiconductor chip includes a semiconductor body with a semiconductor layer sequence. An active region intended for generating radiation is arranged between an n-conductive multilayer structure and a p-conductive semiconductor layer. A doping profile is formed in the n-conductive multilayer structure which includes at least one doping peak.

Abstract: A light-emitting diode chip includes an epitaxial layer with a plurality of recess portions and protrusion portions; and a light transmission layer having a plurality of light transmission portions between top ends of adjacent protrusion portions and forming holes with the recess portions. The light transmission portions have a horizontal dimension larger than a width of the top ends of two adjacent protrusion portions, and serve as current blocking layer. A current spreading layer covers the light transmission layer and the epitaxial layer not masked by the light transmission layer. A refractive index of the light transmission layer is between those of the epitaxial layer and the holes, indicating a difference of refractive index between the light transmission layer and the epitaxial layer. Light scattering probability can therefore be increased, thus avoiding light absorption by electrodes and improving light extraction efficiency.

Abstract: A light-emitting device package of the embodiments includes a package body; at least one light emitting device above the package body; an adhesive layer between the at least one light emitting device and the package body; and an adhesive-layer-accommodating portion disposed in the package body for accommodating the adhesive layer therein, wherein the adhesive-layer-accommodating portion has a side surface disposed to be inclined at a predetermined angle relative to an imaginary vertical plane that extends in a thickness direction of the package body.

Abstract: Disclosed is a light emitting device according to the embodiment including a conductive semiconductor layer divided into at least two or more light emitting regions; a plurality of light emitting structures on the conductive semiconductor layer; an electrode layer on the plurality of light emitting structures; a second electrode electrically connected to the electrode layer; and a first electrode electrically connected to the conductive semiconductor layer, wherein each of the light emitting structures includes a rod-shaped first conductivity type semiconductor, an active layer configured to surround the first conductivity type semiconductor and a second conductivity type semiconductor configured to surround the active layer, and each of the light emitting structures has at least two or more outer surfaces having different extending directions with respect to an upper surface of the conductive semiconductor layer.

Abstract: According to the present disclosure, optoelectronic semiconductor chip includes at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and one active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer. The p-doped semiconductor layer is electrically contacted by means of a first metallic connection layer, and a reflection-enhancing dielectric layer sequence is arranged between the p-doped semiconductor layer and the first connection layer, which dielectric layer sequence includes a plurality of dielectric layers with different refractive indices.

Abstract: A method of producing a carrier for an optoelectronic component includes providing a lead frame having an upper side and a lower side; arranging a first film on the lower side of the lead frame; arranging a second film on the upper side of the lead frame; forming a molded body from a molding material, the lead frame being embedded in the molded body; and removing the first film and the second film.

Abstract: An optoelectronic apparatus is disclosed. In an embodiment, the apparatus includes at least one wavelength conversion region which includes at least one dual emitter as wavelength conversion material, wherein the wavelength conversion region converts primary radiation at least in part into secondary radiation, and wherein the dual emitter includes a first electronic base state and a second electronic base state, together with a first electronically excited state and a second electronically excited state which may be reached from the first electronically excited state. The dual emitter further includes emission proceeding from the second electronically excited state into the second base state.

Abstract: Embodiments of the invention include a wavelength-converting material defined by AE3?x1?y+zRE3?x2+y?z[Si9-wAlw(N1?yCy)[4](N16?z?wOz+w)[12]]Eux1,Cex2, where AE=Ca, Sr, Ba; RE=Y, Lu, La, Sc; 0?x1?0.18; 0?x2?0.2; x1+x2 >0; 0?y?1; 0?z?3; 0?w?3.

Abstract: An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a top surface, a bottom surface, a plurality of lateral surfaces arranged between the top surface and the bottom surface, and a first electrode arranged on the bottom surface; a wavelength converting material covering a plurality of lateral surfaces; and a reflecting layer, formed on the wavelength converting material which is arranged on the top surface.

Abstract: Small LED sources with high brightness and high efficiency apparatus including the small LED sources and methods of using the small LED sources are disclosed.

Abstract: A light-emitting device includes a light-emitting structure, a lens, and a reflective layer. The light-emitting structure includes a light-emitting stack structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer, which are stacked, a first electrode layer electrically connected to the first-conductivity-type semiconductor layer, and a second electrode layer electrically connected to the second-conductivity-type semiconductor layer. The lens is located on the light-emitting structure. The reflective layer is located on the lens.

Abstract: An optoelectronic component includes a first lead frame section and a second lead frame section spaced apart from one another, and having an optoelectronic semiconductor chip arranged on the first lead frame section and the second lead frame section, wherein the first lead frame section and the second lead frame section respectively have an upper side, a lower side and a first side flank extending between the upper side and the lower side, a first lateral solder contact surface of the optoelectronic component is formed on the first side flank of the first lead frame section, and the first lateral solder contact surface is formed by a recess arranged on the first side flank of the first lead frame section and extends from the upper side to the lower side of the first lead frame section.

Abstract: A light emitting device includes a substrate, a plurality of first wiring members, a plurality of second wiring members and a plurality of light emitting elements. The first wiring members extend in a first direction. The second wiring members extend in a second direction. Each of the second wiring members is segmented into a plurality of second wiring portions. The light emitting elements are disposed along the second direction. A first electrode of the light emitting element is connected to a corresponding one of the first wiring members. A second electrode of the light emitting element has a first connection part and a second connection part that is linked to the first connection part. The first connection part and the second connection part are connected to a corresponding one of the second wiring members and bridge at least two of the segmented second wiring portions in the second direction.

Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Abstract: Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.

Abstract: A method of forming a thermoelectric device structure and the resultant thermoelectric device structure. The method forms a first pattern of epitaxial thermoelectric elements of a first conductivity type on a first semiconductor substrate, forms a second pattern of epitaxial thermoelectric elements of a second conductivity type on a second semiconductor substrate, separates the epitaxial thermoelectric elements of the first conductivity type and places the epitaxial thermoelectric elements of the first conductivity type and the epitaxial thermoelectric elements of the second conductivity type on a heat sink, and integrates the heat sink to a device substrate including an electronic device to be cooled.

Abstract: Aspects relate to an energy harvesting device adapted for use by an athlete while exercising. The device may utilize a mass of phase-change material to store heat energy, the stored heat energy subsequently converted into electrical energy by one or more thermoelectric generator modules. The energy harvesting device may be integrated into an item of clothing, and such that the mass of phase change material may store heat energy as the item of clothing is laundered.

Abstract: Aspects relate to an energy harvesting device adapted for use by an athlete while exercising. The device may utilize a mass of phase-change material to store heat energy, the stored heat energy subsequently converted into electrical energy by one or more thermoelectric generator modules. The energy harvesting device may be integrated into an item of clothing, and such that the mass of phase change material may store heat energy as the item of clothing is laundered.

Abstract: In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity.

Abstract: A piezoelectric sensor comprises a microcontroller, a plurality of piezoelectric sensor elements of which at least two are useable for producing a haptic signal by a voltage (HV) generated by a boost converter connected to each piezoelectric sensor element, and connected to a piezo channel of the microcontroller. A multiplexer individually controls each of the switches if an enable a signal is present. The microcontroller is configured to use each of the piezo channels as a sensor channel for reading sensor input from the respective piezoelectric sensor element and in response to detecting a sensor input in at least one of the piezo channels to set the enable signal at the increase voltage pin and/or the enable signal pin, and to set a signal to at least one piezo channel in which the sensor input was detected.

Abstract: A driving stage of a servo valve, including a hydraulic ejector and a hydraulic receiver able to be moved relative to each other, one of the two hydraulic units being integral with a mobile unit, movable relative to a body of the servo valve through actuation means, characterized in that the actuation means comprise two piezoelectric actuators connected in series. Control device comprising a servo valve comprising such a driving stage.

Abstract: A piezoelectric energy harvester has a box, a plurality of first arc-shaped metal stands and a plurality of arc-shaped piezoelectric elements. The box has an upper portion, a connection base, a buffer element and a lower portion. The connection base situates between the upper portion and the lower portion. The upper portion movably connects with the lower portion through the buffer element. The plurality of first arc-shaped metal stands situated on a side of the connection base in the box. Each of the arc-shaped piezoelectric elements locates on each of the first arc-shaped metal stands. When an external force applied on the box, the plurality of first arc-shaped metal stands deforms due to the compression from the upper portion and consequently causes the deformation of the arc-shaped piezoelectric elements for generating electricity accordingly.

Abstract: An element, including a first electrode, an intermediate layer, and a second electrode, the first electrode, the intermediate layer, and the second electrode being laminated in this order, wherein the intermediate layer has flexibility, and wherein a deformation amount on a side of the first electrode of the intermediate layer is different from a deformation amount on a side of the second electrode of the intermediate layer when a pressure is applied to the intermediate layer in a direction orthogonal to a surface of the intermediate layer.

Abstract: A crystal vibrator includes an AT-cut crystal substrate with a vibration portion having a principal surface and a peripheral portion surrounding and thinner than the vibration portion. An excitation electrode is formed on the principal surface and an extension electrode is electrically connected to the excitation electrode. The vibration portion has a first short-edge side lateral surface that abuts the peripheral portion at an acute angle and a tapered lateral surface adjacent to the first short-edge side lateral surface and inclined with respect to the X axis in the XZ? plane. The tapered lateral surface abuts the peripheral portion at an angle that is greater than the angle defined by the first short-edge side lateral surface. The extension electrode extends from the excitation electrode through the tapered lateral surface to a first short-edge side in a longitudinal direction parallel to the Z? axis.

Abstract: A data storage device and a method for manufacturing the data storage device provide a data storage device having a superior reliability and easy fabrication. The data storage device comprises a substrate including cell and peripheral circuit regions, a first conductive line on the peripheral circuit region, a peripheral contact plug between the substrate and the first conductive line, the peripheral contact plug being in contact with the first conductive line, a second conductive line on the cell region, a plurality of data storage structures between the substrate and the second conductive line, and a wiring structure between the substrate and each of the data storage structures and between the substrate and the peripheral contact plug. The first conductive line includes a bottom surface having a position from the substrate that is lower than a position of a bottom surface of the second conductive line.

Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.