Abstract: Implementations disclosed herein generally relate to methods of forming silicon oxide films. The methods can include performing silylation on the surface of the substrate having terminal hydroxyl groups. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma and H2O soak in order to perform an additional silylation. Further methods include catalyzing the exposed surfaces using a Lewis acid, directionally inactivating the exposed first and second surfaces and deposition of a silicon containing layer on the sidewall surfaces. Multiple plasma treatments may be performed to deposit a layer having a desired thickness.

Abstract: Atomic layer deposition in selected zones of a workpiece surface is accomplished by transforming the surfaces outside the selected zones to a hydrophobic state while the materials in the selected zones remain hydrophilic.

Abstract: A method of manufacturing a display apparatus is provided as follows. A substrate having a display portion on an upper surface of the substrate is prepared. A protection film having an opening is attached to a lower surface of the substrate so that the protection film overlaps the display portion. A support film is attached to the lower surface so that the support film is disposed within the opening of the protection film. A driving circuit chip is attached to the upper surface so that the driving chip is spaced apart from the display portion and the opening. At least a part of the support film is removed. The substrate is bent along a longitudinal direction of the opening.

Abstract: A thermally conductive sheet includes: a first graphite sheet; a second graphite sheet that is any of a second graphite sheet disposed to entirely overlap the first graphite sheet, a second graphite sheet disposed to partially overlap and to be shifted from the first graphite sheet, and a second graphite sheet disposed such that there is an interval of less than 5 mm between the second graphite sheet and the first graphite sheet; a first adhesive layer configured to adhere facing surfaces of the first graphite sheet and the second graphite sheet which are disposed; metal layers stacked to sandwich the first graphite sheet and the second graphite sheet which are disposed from the top and bottom; and second adhesive layers configured to adhere facing surfaces of the first graphite sheet, the second graphite sheet, and the metal layers which are disposed.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include net chemisorption of a self-assembled monolayer on the second surface to prevent deposition of the film on the second surface.

Abstract: Methods for depositing silicon oxycarbide (SiOC) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor that does not comprise nitrogen and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOC films having improved acid-based wet etch resistance.

Abstract: Disclosed are Si—C free and volatile silazane precursors for high purity thin film deposition.

Abstract: A method is provided for depositing a planarization layer over features on a substrate using sequential polymerization chemical vapor deposition. According to one embodiment, the method includes providing a substrate containing a plurality of features with gaps between the plurality of features, delivering precursor molecules by gas phase exposure to the substrate, adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules, and reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps.

Abstract: Methods of depositing conformal, dense silicon-containing films having low hydrogen content are provided herein. Methods involve pulsing a plasma while exposing a substrate to a silicon-containing precursor and reactant to facilitate a primarily radical-based pulsed plasma enhanced chemical vapor deposition process for depositing a conformal silicon-containing film. Methods also involve periodically performing a post-treatment operation whereby, for every about 20 ? to about 50 ? of film deposited using pulsed plasma PECVD, the deposited film is exposed to an inert plasma to densify and reduce hydrogen content in the deposited film.

Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.

Abstract: A method for manufacturing a photoelectric conversion device comprising the steps of fixing a first substrate including a semiconductor layer provided with a photoelectric conversion element, to a second substrate, thinning the first substrate fixed to the second substrate, from the opposite side of the first substrate from the second substrate, fixing the first substrate to a third substrate provided with a semiconductor element such that the third substrate is located on the opposite side of the first substrate from the second substrate, and removing the second substrate after the step of fixing the first substrate to the third substrate.

Abstract: Semiconductor light emitting diodes (LEDs) formed as (Al)GaN-based nanowire structures have a first semiconductor layer, a second semiconductor layer, and a thin metallic layer fabricated therebetween. The structures, operating in the deep ultraviolet (UV) spectral range, exhibit high photoluminescence efficiency at room temperature. The structures may be formed of an epitaxial metal tunnel junction operating as a reflector that enhances carrier transport to and from the semiconductor alloy layers, capable of producing external quantum efficiencies at least one order of magnitude higher than convention devices.

Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

Abstract: We describe a method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide layer grown on the silicon wafer. The method includes applying nitrogen atoms during the growth process of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer.

Abstract: In a method of manufacturing a semiconductor device having an oxide film removing step where an oxide film formed on a surface of a semiconductor substrate is partially removed, the oxide film removing step includes: a first step where a resist glass layer is selectively formed on an upper surface of the oxide film without using an exposure step; a second step where the resist glass layer is densified by baking the resist glass layer; and a third step where the oxide film is partially removed using the resist glass layer as a mask, wherein the resist glass layer is made of resist glass which contains at least SiO2, B2O3, Al2O3, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na, K, and Zn.

Abstract: Provided is a SiC substrate treatment method for, with respect to a SiC substrate (40) that has, on its surface, grooves (41), activating ions while preventing roughening of the surface of the substrate. In the method, an ion activation treatment in which the SiC substrate (40) is heated under Si vapor pressure is performed to the SiC substrate (40) has, on its surface, an ion implantation region (46) in which ions have been implanted, and has the grooves (41) provided in a region including at least the ion implantation region (46), thereby ions that are implanted in the SiC substrate (40) is activated while etching the surface of the substrate.

Abstract: This invention involves a fabrication method of fast recovery diode, which includes following steps: growing a sacrificial oxide layer on a surface of an N? substrate; forming a P type doped field-limiting ring region on the substrate; forming a P type doped anode region on the substrate; removing the sacrificial oxide layer; annealing the substrate to form a PN junction; implanting oxygen into the surface of the substrate by ion implantation; annealing the substrate to form a silicon dioxide layer on the surface of the substrate; removing the silicon dioxide layer; forming an anode electrode and a cathode electrode of the fast recovery diode. The method eliminates the curved parts near the silicon surface of the profile of PN junction, decreases electric field intensity at the surface of the substrate, therefore increases the breakdown voltage and reliability of the fast recovery diode.

Abstract: A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.

Abstract: Methods for forming transistors are provided. A substrate is placed in a processing chamber, and a plurality of epitaxial features is formed on the substrate. The epitaxial feature has at least a surface having the (110) plane and a surface having the (100) plane. An etchant or a gas mixture including an etchant and an etch enhancer or an etch suppressor is introduced into the processing chamber to remove a portion of the epitaxial feature. Etch selectivity between the surface having the (110) plane and the surface having the (100) plane can be tuned by varying the pressure within the processing chamber, the ratio of the flow rate of the etchant or gas mixture to the flow rate of a carrier gas, and/or the ratio of the flow rate of the etch enhancer or suppressor to the flow rate of the etchant.

Abstract: Disclosed is a method of etching a silicon layer by removing an oxide film formed on a workpiece which includes the silicon layer and a mask provided on the silicon layer. The method includes: (a) forming a denatured region by generating plasma of a first processing gas containing hydrogen, nitrogen, and fluorine within a processing container accommodating the workpiece therein to denature an oxide film formed on a surface of the workpiece; (b1) removing the denatured region by generating plasma of a rare gas within the processing container; and (c) etching the silicon layer by generating plasma of a second processing gas within the processing container.

Abstract: Provided is a method for controlling the rate of etching of a SiC substrate based on a composition of a storing container. The etching method of the present invention is for etching the SiC substrate by heating the SiC substrate under Si vapor pressure, in a state where the SiC substrate is stored in a crucible. The crucible is formed of a tantalum metal, and has a tantalum carbide layer provided on an internal space side of the tantalum metal, and a tantalum silicide layer provided on the side further toward the internal space side than the tantalum carbide layer. The rate of etching of the SiC substrate is controlled based on difference in a composition of the tantalum silicide layer.

Abstract: A method of manufacturing a vertical memory device includes forming a preliminary first mold structure on a substrate, which includes main and edge regions, and the first preliminary mold structure including alternating insulation and sacrificial layers, forming a first mask on the preliminary first mold structure to expose the preliminary first mold structure between a boundary of the substrate and a first target position, partially etching the insulation and sacrificial layers using the first mask to form a preliminary second mold structure, forming a second mask on the preliminary second mold structure to expose the preliminary second mold structure between the boundary of the substrate and a second target position different from the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask.

Abstract: The present invention discloses a leadframe in which two conductive pillars with a high aspect ratio and the corresponding two leads of the leadframe form a 3D space for accommodating at least one device. A first lead and a second lead are spaced apart from each other. A first conductive pillar is formed on the first lead by disposing a first via on the first lead, wherein at least one first conductive material is filled inside the first via to form the first conductive pillar. A second conductive pillar is formed on the second lead by disposing a second via on the second lead, wherein at least one second conductive material is filled inside the second via to form the second conductive pillar. The first lead, the second lead, the first conductive pillar, and the second conductive pillar form a 3D space for accommodating at least one device, wherein the at least one device is electrically connected to the first conductive pillar and the second conductive pillar.

Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.

Abstract: The present application relates to a method of generating a power semiconductor module including a carrier layer and a substrate having a terminal connection area, the method comprising: soldering the substrate to the carrier layer by forming a solder layer; wherein the solder layer is formed such, that a pre-defined cavity is provided in the solder layer adjacent to the substrate and located opposite to the terminal connection area; and welding a terminal to the terminal connection area of the substrate. The present application provides a method of generating a power semiconductor module which is especially cost-saving to perform and allows a reliable generation of high quality modules.

Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

Abstract: Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.

Abstract: The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for making the same. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, the magnetically enhanced mold compound component, and a mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with an inductive element embedded therein. Herein, the inductive element is underlying the first surface portion and not underlying the second surface portion. The magnetically enhanced mold compound component is formed over the first surface portion. The mold compound component is formed over the second surface portion, not over the first surface portion, and surrounding the magnetically enhanced mold compound component.

Abstract: To provide a film which is excellent in releasing property with respect to a resin sealed portion and excellent in low migration property and peeling property with respect to a semiconductor chip, a source electrode or a sealing glass and which is suitable as a mold release film for producing a semiconductor element having a part of the surface of a semiconductor chip, source electrode or sealing glass exposed. A film 1 which comprises a substrate 3 and an adhesive layer 5, wherein the storage elastic modulus at 180° C.

Abstract: A substrate etching system includes a support to hold a wafer in a face-up orientation, a dispenser arm movable laterally across the wafer on the support, the dispenser arm supporting a delivery port to selectively dispense a liquid etchant onto a portion of a top face of the wafer, and a monitoring system comprising a probe movable laterally across the wafer on the support.

Abstract: Provided is a substrate processing system and a substrate processing method. The substrate processing system includes a polishing part for performing a Chemical Mechanical Polishing (CMP) process on a substrate, a cleaning part for cleaning the substrate on which the polishing process is performed, and a substrate transferring part for transferring the substrate to the cleaning part before polishing the substrate in the polishing part. The substrate may be preparatorily cleaned in the cleaning part before the polishing process, and then enters the polishing part.

Abstract: The present disclosure provides a support device for conveying at least one solar cell element in a transport direction, wherein the support device comprises a support element configured for supporting the at least one solar cell element and an electric arrangement configured for providing an electrostatic force for holding the at least one solar cell element on the support element.

Abstract: A substrate washing device includes a substrate holding mechanism 70 that holds a substrate W, a substrate rotating mechanism 72 that rotates the substrate W held by the substrate holding mechanism 70, and a two-fluid nozzle 46 that ejects a two-fluid jet toward a surface of the rotating substrate W. The two-fluid nozzle 46 is formed of a conductive material. Accordingly, the electrification amount of droplets ejected as the two-fluid jet from the two-fluid nozzle 46 can be suppressed.

Abstract: An apparatus for drying of wet substrates in a post CMP cleaning apparatus is provided. The apparatus provides a waterfall or shallow reservoir of rinsing solution, such as DIW, through which a substrate may be lifted. A solvent vapor may be provided at the rinsing solution interface on the substrate, such as in a Marangoni process. In certain embodiments, the volume of solution through which the substrate is lifted is reduced, which may provide for reduced or eliminated particle reattachment to the substrate.

Abstract: Provided is a substrate processing apparatus including: a chamber in which plasma processing is performed on a substrate; a susceptor disposed in the chamber and on which the substrate is held; a shower head provided to face the susceptor with a processing space therebetween; a high frequency power source which generates plasma by applying high frequency power to the processing space; water spray devices which form a surface wet with water on a rear surface of a surface of the susceptor as a temperature adjustment surface; an evaporation chamber which isolates the wet surface from an atmosphere around the wet surface; and a pressure adjustment device which adjusts a pressure in the evaporation chamber, wherein the pressure in the evaporation chamber is adjusted by using the pressure adjustment device such that the water which forms the wet surface is evaporated, thereby controlling a temperature of the surface of the susceptor by using latent heat of evaporation of the water.

Abstract: A decapsulation apparatus has an etch plate, an off-center etch head having an opening, a cover sealing to the etch plate forming an etching chamber, a gasket surrounding the opening, a ram sealed through the cover, a pressure-controlled source of Nitrogen or inert gas continuously purging the etching chamber at a low gas pressure, a f toggle mechanism mounted to a metal plate t, an etchant supply subsystem comprising sources of etchant solutions, an etchant solution pump, supply passages and controls to select etchants and etchant ratios, and a heat exchanger heating or cooling the etchant solution, etchant waste passages f conducting used etchant away. Etchants are mixed in the passages to the reaction region, and turbulence in the reaction region is promoted by impinging etchant solution on the encapsulated device.

Abstract: An advanced temperature control system and method are described for a wafer carrier in a plasma processing chamber. In one example a heat exchanger provides a temperature controlled thermal fluid to a fluid channel of a workpiece carrier and receives the thermal fluid from the fluid channel. A proportional valve is between the heat exchanger and the fluid channel to control the rate of flow of thermal fluid from the heat exchanger to the fluid channel. A pneumatic valve is also between the heat exchanger and the fluid channel also to control the rate of flow of thermal fluid from the heat exchanger and the fluid channel. A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve and the pneumatic valve in response to the measured temperature to adjust the rate of flow of the thermal fluid.

Abstract: An embodiment relates to a wafer loading apparatus of wafer polishing equipment.

Abstract: In accordance with various embodiments, provision is made of a substrate holding device, wherein the latter may comprise a carrier plate with a recess, the recess extending from an upper side of the carrier plate to a lower side of the carrier plate through the carrier plate, a holding frame, which has a frame opening and a support area, surrounding the frame opening, for holding a substrate in the recess, wherein the holding frame inserted into the recess lies on the carrier plate in sections.

Abstract: A substrate processing apparatus including a plurality of processing devices each of which processes a substrate is provided. The apparatus comprises a conveying device including a conveyance path and conveys, to one of the plurality of processing devices, a substrate conveyed into one end of the conveyance path from an outside of the substrate processing apparatus, and an adjusting device configured to perform adjustment of a pre-alignment state of the substrate conveyed from the one end and to be conveyed into one of the plurality of processing devices, wherein the adjusting device is arranged on the conveyance path and between a processing devices of the plurality of processing devices, farthest from the one end, and a processing device, of the plurality of processing devices, closest to the one end.

Abstract: A transport device is capable of reliably determining a presence or absence of a lid provided on a container and/or determining detachment of the lid, with a simple configuration. The transport device transports a container that includes a lid on a side surface. The transport device includes a lid fall preventive member disposed so as to face an upper end of the lid of the container located in a transport position, and a lid detector that is disposed in the lid fall preventive member and detects the presence or absence of the upper end of the lid.

Abstract: A holding apparatus for a semiconductor substrate and a conveying apparatus for a semiconductor substrate. A susceptor is fixed to a rotational driving shaft to be attachable and detachable in a vertical direction, the opening portions are formed to extend through the susceptor in a thickness direction of the susceptor, and a meshing portion which meshes with the substrate holders releasably in a vertical direction so that the substrate holder can rotate according to rotation of the susceptor is provided below the susceptor.

Abstract: Provided is an electrostatic chucking device having high heat resistance. The electrostatic chucking device of the present invention includes a first ceramic plate which includes a first surface on which a substrate is able to be placed and a second surface on the opposite side thereof, and in which an internal electrode for electrostatic adsorption is embedded; a heating member fixed to the second surface; a second ceramic plate adhered to the first ceramic plate and the heating member via a first adhesive layer; and a cooling base portion adhered to the second ceramic plate via a second adhesive layer and cools at least the second ceramic plate. The first adhesive layer has a higher heat resistance than the second adhesive layer. The second adhesive layer has a smaller Young's modulus than the first adhesive layer.

Abstract: A surface protective sheet is used when grinding the rear surface of a semiconductor wafer having a circuit formed on the front surface, and is provided with: a base material comprising a support film and an antistatic coating layer which includes an inorganic conductive filler and a cured product of a curable resin (A); and an adhesive layer. The stress relaxation percentage of the base material after 1 minute at 10% elongation is at least 60%. The Young's modulus of the base material is 100-2000 MPa.

Abstract: A robot subassembly including roll, pitch, and/or vertical orientation adjustability capability of a ceramic or glass end effector. The robot subassembly includes a robot component, a mounting plate coupled to the robot component, wherein the mounting plate includes adjustable orientation relative to the robot component, and a brittle ceramic or glass end effector coupled to the mounting plate. Methods of adjusting orientation between a robot component and the end effector, as well as numerous other aspects are disclosed.

Abstract: Embodiments of the present invention provide systems, apparatus, and methods for an improved substrate handling assembly. Embodiments include a pair of actuated arms; a pair of substrate capture tips, each capture tip formed in a different distal end of each actuated arm; an actuator coupled to a proximate end of the actuated arms and operative to actuate the actuated arms; and a hard stop positioned to prevent the actuator from closing the actuated arms more than a predefined amount so that in a closed position, the actuated arms do not contact a substrate positioned to be picked up by the substrate handing assembly. Numerous additional aspects are disclosed.

Abstract: In an apparatus for treating a wafer-shaped article, a spin chuck is configured to hold a wafer-shaped article of a predetermined diameter. A non-rotating plate is positioned relative to the spin chuck such that the non-rotating plate is beneath and parallel to a wafer-shaped article when positioned on the spin chuck. A fluid dispensing nozzle passes through the non-rotating plate and terminates in a discharge end positioned above and adjacent to the non-rotating plate. The discharge end comprises a horizontal gas discharge nozzle configured to distribute gas radially outwardly across an upper surface of the non-rotating plate.

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

Abstract: A method includes performing one or more times of a sequence and reducing a film thickness of a fluorocarbon-containing film formed by performing one or more times of the sequence. Each of the one or more times of the sequence includes forming the fluorocarbon-containing film on a processing target object by generating plasma of a processing gas containing a fluorocarbon gas and not containing an oxygen gas; and etching a first region with radicals of fluorocarbon contained in the fluorocarbon-containing film. In the method, an alternating repetition in which the one or more times of the sequence and the reducing of the film thickness of the fluorocarbon-containing film are alternately repeated is performed.

Abstract: An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.