Abstract: Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction.

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.

Abstract: According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

Abstract: A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or a second potential supply line (106) are each connected directly and individually to all the circuit components via respective individual conductor path structures (V1, V2).

Abstract: A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically connected between the seal ring and a ground pad. The noise-absorbing circuit includes at least one capacitor and at least one inductor to form a first noise-absorbing path, a second noise-absorbing path and a third noise-absorbing path.

Abstract: A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate.

Abstract: A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.

Abstract: An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.

Abstract: A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.

Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure may have a first conductive structure and a second conductive structure arranged over a first substrate. A bump structure is arranged between the first conductive structure and a second substrate. A solder layer is configured to electrically couple the first conductive structure and the bump structure. The bump structure has a recess that is configured to reduce a protrusion of the solder layer in a direction extending from the first conductive structure to the second conductive structure.

Abstract: A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers.

Abstract: A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining layer that is joined to the joined member and contains 2.0 wt % or higher of copper, in which the joining layer includes a solder portion and a Cu6Sn5 portion, base metal of the solder portion contains at least tin as a constituent element and contains elemental copper, and the Cu6Sn5 portion is in contact with the nickel film.

Abstract: A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: A die package having lead structures connecting to a die that provide for electromagnetic interference reductions. Mixed impedance leads connected to the die have a first lead with a first metal core, a dielectric layer surrounding the first metal core, and first outer metal layer connected to ground; and a second lead with a second metal core, and a second dielectric layer surrounding the second metal core, and a second outer metal layer connected to ground. Each lead reducing susceptibility to EMI and crosstalk.

Abstract: Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a mounting unit providing bis(2-ethylhexyl) terephthalate (DEHT) between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the DEHT and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.

Abstract: A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

Abstract: A methodology and medium for regular and predictable cleaning the support hardware such as capillary tube in semiconductor assembly equipment components, while it is still in manual, semi-automated, and automated assembly are disclosed. The cleaning material may include a cleaning pad layer and one or more intermediate layers that have predetermined characteristics.

Abstract: A method of manufacturing a light emitting device includes: preparing a light-transmissive member including a light reflective sheet that has a through-hole, and a color conversion material layer that is composed of a light-transmissive resin containing a color conversion material and disposed in the through-hole, preparing a light emitting element, fixing the color conversion material layer to the light emitting element, covering a side surface of the light emitting element with a light-reflective member, and cutting the light-reflective member and light-reflective sheet.

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

Abstract: An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on the first insulating layer so that an inactive side thereof is directed toward the first insulating layer, and a second insulating layer disposed on the first insulating layer so as to cover the electronic component and having a redistribution pattern formed thereon so as to be electrically connected to the electronic component.

Abstract: A semiconductor device includes a package interface including N numbers of first group of data balls which are disposed on a first side thereof, N numbers of second group of data balls which are disposed on a second side thereof, and M numbers of command/address balls which are disposed between the first side and the second side; a first semiconductor chip which is stacked on the first side over the package interface, and includes 2N numbers of first group of data pads and M numbers of first command/address pads; and a second semiconductor chip which is stacked on the second side over the package interface, and includes 2N numbers of second group of data pads and M numbers of second command/address pads.

Abstract: Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure.

Abstract: An electronic component device includes a first electronic component, a second electronic component disposed on and connected to the first electronic component, a first underfill resin filled between the first electronic component and the second electronic component, the first underfill resin having a base part arranged around the second electronic component and an alignment mark formed on an upper surface of the base part, a third electronic component disposed on and connected to the second electronic component, and a second underfill resin filled between the second electronic component and the third electronic component.

Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first chip and the third chip. The chip package structure includes a first molding layer surrounding the first chip. The chip package structure includes a second molding layer surrounding the second chip. The chip package structure includes a third molding layer surrounding the third chip, the first molding layer, and the second molding layer.

Abstract: A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality of semiconductor packages on the precursor substrate, in which a gap is presented between the precursor substrate and each of the semiconductor packages; (ii) forming underfill material filling the gaps; (iii) cutting the precursor substrate along a region between adjacent ones of the semiconductor packages to form a plurality of discrete package-on-package devices; and (iv) applying supplemental underfill material to one of the package-on-package devices.

Abstract: An interconnect substrate having vertical connection channels around a cavity is characterized in that contact pads are exposed from the cavity and the vertical connection channels are made of a combination of metal posts and metallized vias. The cavity includes a recess in a core layer and an aperture in a stiffener. The metal posts, disposed over the top surface of the core layer, are sealed in the stiffener and are electrically connected to a buildup circuitry adjacent to the bottom surface of the core layer. The minimal height of the metal posts needed for the vertical connection can be reduced by the amount equal to the depth of the recess. The buildup circuitry is electrically connected to the metal posts through the metallized vias and provides the contact pads exposed from the cavity for device connection.

Abstract: A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

Abstract: A light emitting element includes a semiconductor including an active layer, and a planar shape of the light emitting elements including a concave polygon. The planar shape of the concave polygon has interior angles including at least one acute angle.

Abstract: A light-emitting device of an embodiment of the present application comprises light-emitting units; a transparent structure having cavities configured to accommodate at least one of the light-emitting units; and a conductive element connecting at least two of the light-emitting units.

Abstract: A light emitting device array including a circuit substrate and a plurality of device layers is provided. The circuit substrate includes a plurality of bonding pads and a plurality of conductive bumps located over the bonding pads. The device layers are capable of emitting different colored lights electrically connected with the circuit substrate through the conductive bumps and the bonding pads. The device layers capable of emitting different colored lights have different thicknesses and the conductive bumps bonded with the device layers capable of emitting different colored lights have different heights such that top surfaces of the device layers capable of emitting different colored lights are located on a same level of height.

Abstract: A light source module includes a circuit board having a plurality of chip mounting regions, the plurality of chip mounting regions respectively having at least one connection pad; at least one alignment component respectively disposed on the plurality of chip mounting regions, and having a convex or concave shape; and a plurality of LED chips respectively mounted on the plurality of chip mounting regions, respectively having at least one electrode electrically connected to the at least one connection pad, and respectively coupled to the at least one alignment component.

Abstract: A light-mixing multichip package structure includes a circuit substrate, a first light-emitting module, a first package body, a second light-emitting module and a second package body. The first light-emitting module includes a plurality of first light-emitting elements disposed on the circuit substrate and electrically connected to the circuit substrate. The first package body is disposed on the circuit substrate to enclose the first light-emitting elements. The second light-emitting module includes a plurality of second light-emitting elements disposed on the circuit substrate and electrically connected to the circuit substrate, and the first light-emitting module and the first package body are surrounded by the second light-emitting elements. The second package body is disposed on the circuit substrate to enclose the first light-emitting module, the second light-emitting module and the first package body.

Abstract: A light emitting device package includes a cell array including a plurality of semiconductor light emitting units, and having a first surface and a second surface opposite the first surface, each of the plurality of semiconductor light emitting units having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked on each other.

Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract: An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, and first and second electrodes on the layer. A first region of the first type is between the layer and the first electrode and contacting the first electrode. A second region of a second conductivity type is between the layer and the second electrode. A third region of the second type is connected to the second electrode, between the first and second regions, and between the layer and the second electrode. A fourth region of the first type is between the second region and the second electrode and contacting the second electrode. A fifth region of the second type is between the layer and the second region and has an impurity concentration greater than the second region and the third region. A sixth region of the first type is between the second region and the third region.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: An ESD clamp circuit includes a power supply, a ground supply, an ESD detection transistor, a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor, and a first resistor connected in series with the capacitor between the power and ground supplies. The ESD clamp circuit also includes a clamp transistor having a first terminal connected to the power supply and a second terminal connected to the ground terminal, an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to the gate of the clamp transistor, a feedback transistor connected across the inverter, and a second resistor having a first terminal connected to the gate of the clamp transistor and to a second terminal to the ground supply.

Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

Abstract: A semiconductor device is provided. The semiconductor device includes an active region, a gate line, a first metal interconnect, a power rail, and a second metal interconnect. The gate line overlaps the active region and extends along a first direction. The first metal interconnect overlaps the active region and the gate line. The first metal interconnect extends along a second direction intersecting the first direction. The power rail is disposed in a higher layer than the first metal interconnect. The power rail extends along the second direction. The second metal interconnect is disposed in a same layer as the power rail, the second metal interconnect extends along the second direction.

Abstract: A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the substrate and the first nitride semiconductor layer, a third nitride semiconductor layer brought together with the second nitride semiconductor layer to form a second heterojunction interface, between the substrate and the second nitride semiconductor layer, and a first contact electrically connected to the first and second heterojunction interfaces.

Abstract: A semiconductor device has a plurality of transistors, which have first electrodes in first trenches, and includes: two second trenches, which are formed side by side between the first trenches. A second electrode is formed in each of the two second trenches. A first impurity region is formed between the first trench and the second trench; a second impurity region is formed to abut on the first trench; a third impurity region is formed to abut on the second trench; a fourth impurity region, which is formed between two of the second trenches and has a higher impurity concentration than the first impurity region; and a fifth impurity region is formed below the first impurity region and the fourth impurity region. A third electrode is formed to be electrically connected to the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region.

Abstract: Some embodiments include a resistor that may be used in audio conversion for an ADC. The resistor may be made up of an n-well as well as a p-well polysilicons. The n-well and p-well polysilicons may include a shallow trench isolator. The n-well and p-well components may be in series with other n-well or p-well components respectively. Similarly, multiple n-well components which are in series, may be in parallel with multiple p-well components.

Abstract: A discrete capacitor of the present invention includes a substrate having a front surface portion, an impurity diffusion layer formed on the front surface portion of the substrate, an oxide film formed on the substrate and having a first opening to selectively expose the impurity diffusion layer, a dielectric film formed on the impurity region having been exposed from the oxide film, and a first electrode opposed to the impurity diffusion layer with the dielectric film therebetween, wherein the impurity concentration on the front surface portion of the impurity diffusion layer is 5×1019 cm?3 or more.