Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

Abstract: A semiconductor device includes a substrate, a circuit layer formed on a first surface of the substrate and including a via pad and an interlayer insulating layer covering the via pad, a via structure configured to fully pass through the substrate, partially pass through the interlayer insulating layer and be in contact with the via pad, a via isolation insulating layer configured to pass through the substrate and be spaced apart from outer side surfaces of the via structure in a horizontal direction and a pad structure buried in the substrate and exposed on a second surface of the substrate opposite the first surface of the substrate.

Abstract: Disclosed are a pixel amplification apparatus and a CMOS image sensor thereof. The pixel amplification apparatus includes a pixel bias sampling unit that samples a first pixel bias voltage, a pixel bias current supply unit that supplies an output node of a pixel signal with a first pixel bias current based on a sampled bias voltage outputted from the pixel bias sampling unit, and a pixel bias current adding unit that additionally supplies the output node with a second pixel bias current in response to a second pixel bias voltage and a period control signal.

Abstract: Disclosed is an optical detector in which a boundary line BY defining an edge of a semiconductor region 14 is covered with signal read wiring E3 and a capacitor is configured between the semiconductor region 14 and the signal read wiring E3. High frequency components peak components of a carrier are quickly extracted to the outside via the capacitor, but the signal read wiring E3 covers the boundary line BY so that a semiconductor potential in the vicinity of the boundary line is stabilized and an output signal is stabilized.

Abstract: A mask includes a substrate, an effective pixel formation region and a reference pattern formation region. A pixel pattern for forming a pixel component that constitutes a pixel is arranged in the effective pixel formation region. A reference pattern for indicating a reference position where pixel pattern should be arranged in the effective pixel formation region is arranged in the reference pattern formation region. Pixel pattern is arranged to be displaced from the reference position toward a center side of the effective pixel formation region.

Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A buffer layer is disposed over the second side of the substrate. A plurality of elements is disposed over the buffer layer. The elements and the buffer layer have different material compositions. A plurality of light-blocking structures is disposed over the plurality of elements, respectively. The radiation-sensing regions are respectively aligned with a plurality of openings defined by the light-blocking structures, the elements, and the buffer layer.

Abstract: An image pickup apparatus includes a first pixel electrode connected to a pixel circuit, a second pixel electrode adjoining the first pixel electrode and connected to the pixel circuit, a photoelectric conversion film continuously covering the first and second pixel electrodes, and an opposite electrode facing the first and second pixel electrodes via the film. The film includes a recessed portion recessed toward a portion between the first and second pixel electrodes on a surface opposite to the first and second pixel electrodes. The depth of the recessed portion is greater than the first pixel electrode's thickness, and a distance from the first pixel electrode to the recessed portion is greater than a distance from the first pixel electrode to the second pixel electrode. The opposite electrode is provided continuously along the surface via the film, and the recessed portion surrounds a part of the opposite electrode.

Abstract: A light-emitting diode is provided. The light-emitting diode comprises: a first light-emitting structure, comprising: a first area; a second area; a first isolation path having an electrode isolation layer between the first area and the second area; an electrode contact layer covering the first area; and an electrical connecting structure covering the second area; wherein each of the first area and the second area sequentially comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, and the electrode contact layer covers a sidewall of the first area.

Abstract: A light-emitting device comprises a carrier; and a first semiconductor element comprising a first semiconductor structure and a second semiconductor structure, wherein the second semiconductor structure is closer to the carrier than the first semiconductor structure is to the carrier, the first semiconductor structure comprises a first MQW structure configured to emit a first light having a first dominant wavelength during normal operation, and the second semiconductor structure comprises a second MQW structure configured not to emit light during normal operation.

Abstract: The emissive device includes first and second adjacent pixels (1a, 1b) sharing a common semiconductor light-emitting stack (2) and each defining an area (4a, 4b) of photon emission. The first and second pixels (1a, 1b) are configured in such a way that supplying current to the first pixel (1a) causes photons to be emitted, by the light-emitting stack (2), only in the emission area (4a) of said first pixel (1a).

Abstract: A light-emitting structure includes a first epitaxial unit; a second epitaxial unit disposed next to the first epitaxial unit; a crossover metal layer including a first protruding portion laterally overlapping the first epitaxial unit and the second epitaxial unit wherein the first protruding portion is electrically connected with the first epitaxial unit and the second epitaxial unit; a conductive connecting layer disposed below the first epitaxial unit and the second epitaxial unit and surrounding the first protruding portion; and an electrode arranged on the conductive connecting layer.

Abstract: A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line. A set path is formed through the first diode and the random access memory cell element, and a reset path is formed through the random access memory cell element and the second diode. The first diode is configured to performed a read operation and a set operation. The second diode is configured to perform a reset operation. The memory cell has higher forward current, lower leakage current and smaller size comparing with conventional memory cells.

Abstract: A switching device includes a first electrode, a switching layer and a second electrode that are disposed over a substrate. The switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom is doped in the oxide or the nitride. A valence of the first atom and a valence of the second atom are different from each other.

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

Abstract: According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines.

Abstract: A memory that includes a memory device having a phase change layer that can be reset by using a reset gate is provided. A memory device includes memory elements arranged in two or more rows and two or more columns. Each memory element includes a pillar-shaped phase change layer, a reset gate insulating film surrounding the pillar-shaped phase change layer, and a reset gate surrounding the reset gate insulating film. The reset gates are connected in a row direction and in a column direction, and are heaters. The pillar-shaped phase change layers are electrically insulated from the reset gates.

Abstract: A semiconductor memory device according to an embodiment comprises: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; and a memory cell disposed at an intersection of the first wiring line and the second wiring line, the memory cell including a first film whose resistance changes electrically, a second film having conductivity, and a third film having an insulating property which are stacked sequentially in a third direction that intersects the first and second directions.

Abstract: A first electrode and an insulation material layer are sequentially formed over a substrate. A doping mask pattern is formed over the insulation material layer. The doping mask pattern exposes a portion of the insulation material layer. Dopants are injected into the exposed portion of the insulation material layer. The doping mask pattern is removed. A second electrode layer is formed over the insulation material layer. One or more pillar-shaped structures, each of which includes a second electrode, an insulation layer and a first electrode formed by respectively patterning the second electrode layer, the insulation material layer, and the first electrode layer. Each of the one or more pillar-shaped structures includes, in the insulation layer, a part of the exposed portion of the insulation material layer that is doped with the dopants. A threshold switching operation is performed in a region doped with the dopants of the insulation layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction.

Abstract: An organic light-emitting diode substrate is provided. The organic light-emitting diode substrate comprises a substrate; a conductive layer formed over the substrate comprising a plurality of anodes and a plurality of cathodes, wherein each of the anodes are electrically insulated from the rest of the anodes and the cathodes; and a light-emitting layer formed over the plurality of anodes and the plurality of cathodes and being electrically connected with the plurality of anodes and the plurality of cathodes.

Abstract: An organic EL display device includes: a TFT substrate that includes a display area in which pixels are arranged in a matrix; and a color filter substrate that is provided to face the TFT substrate and includes an area transmitting light in a predetermined wavelength range for each of the pixels. Each of the pixels of the TFT substrate includes a pair of electrodes, at least two light emission layers that are arranged between the pair of electrodes, and a charge generation layer that is arranged between the at least two light emission layers, is a layer to generate a pair of positive and negative charges, and has different film thicknesses in accordance with the predetermined wavelength range of the corresponding area.

Abstract: An electronic device may have a display. The display may have an active region in which display pixels are used to display images. The display may have one or more openings and may be mounted in a housing associated with the electronic device. An electronic component may be mounted in alignment with the openings in the display. The electronic component may include a camera, a light sensor, a light-based proximity sensor, status indicator lights, a light-based touch sensor array, a secondary display that has display pixels that may be viewed through the openings, antenna structures, a speaker, a microphone, or other acoustic, electromagnetic, or light-based component. One or more openings in the display may form a window through which a user of the device may view an external object. Display pixels in the window region may be used in forming a heads-up display.

Abstract: In one embodiment, an apparatus includes a substrate including material having a low birefringence. One or more electrodes of a touch sensor are disposed on the substrate.

Abstract: A method of forming a flexible display apparatus includes: forming a flexible substrate on a support substrate; forming a light-emitting diode on the flexible substrate; forming a first encapsulation layer on the light-emitting diode; forming a second encapsulation layer; bonding the first encapsulation layer to the second encapsulation layer using an adhesive layer between the first encapsulation layer and the second encapsulation layer; separating the support substrate from the flexible substrate and cutting the flexible substrate to form the flexible display apparatus; and forming a polarizing plate on the second encapsulation layer.

Abstract: The present disclosure discloses an OLED display substrate and a manufacturing method thereof, and a display apparatus. The OLED display substrate is a top emitting OLED display substrate, and comprises a reflective layer covering side surfaces of a pixel defining layer, thus the reflective layer and a first electrode of the OLED form a reflective cup which increases the reflection of light emitted from the OLED.

Abstract: An organic light-emitting device and a flat panel display apparatus, the device including a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode and including an emission layer, wherein the organic layer includes a hole transport region between the first electrode and the emission layer, the hole transport region including an auxiliary layer and at least one selected from a hole transport layer and a hole injection layer, and an electron transport region between the emission layer and the second electrode, the electron transport region including at least one selected from a hole blocking layer, an electron transport layer, and an electron injection layer, wherein the auxiliary layer includes a compound represented by Formula 1 and a compound represented by Formula 2:

Abstract: A curved display device is disclosed. In one aspect, the display device includes a substrate comprising a flat portion and at least one curved portion, a display unit comprising a first display area on the flat portion, and a second display area on the curved portion, and a thin-film encapsulating layer sealing the display unit, and comprising at least one organic layer and at least one inorganic layer. The display device also includes a functional layer over the thin-film encapsulating layer, wherein the thin-film encapsulating layer comprises a first region overlapping the curved portion, and a second region overlapping the flat portion. The inorganic layer contacts the functional layer, and wherein the inorganic layer has a first surface roughness in the first region different from a second surface roughness in the second region.

Abstract: A display device is provided including a first substrate provided with a pixel, the pixel being provided with a light emitting region of a light emitting device formed by stacking a first electrode, a light emitting layer and second electrode in this order, a first insulating layer having an opening exposing the first electrode at a position corresponding to the light emitting region and provided above the first electrode, a second insulating layer having a certain thickness provided over the first insulating layer and outer region of the opening, and a sealing film provided covering the light emitting device above the second electrode.

Abstract: An organic light emitting display device including a substrate, a semiconductor device disposed on the substrate, an insulation layer including an inclined structure disposed on the semiconductor device, a first electrode disposed on the insulation layer, a pixel defining layer disposed on the insulation layer and the first electrode, the pixel defining layer having a pixel opening exposing the first electrode positioned on the inclined structure, an organic light emitting layer disposed on the exposed first electrode and the pixel defining layer, and a second electrode disposed on the organic light emitting layer and the pixel defining layer. Light generated from the organic light emitting layer may be directed in different directions by the inclined structure.

Abstract: A method of forming an organic light emitting diode (OLED) display device is discussed. The method according to an embodiment includes forming a first bank pattern on a substrate and in an emission region and a non-emission region; forming a second bank pattern on the first bank pattern; forming an organic emission layer on the substrate in the emission region; and forming a planarization film on the substrate to include an opening under the first and second bank patterns in the non-emission region. The second bank pattern is on the first bank pattern in the non-emission region, and the first bank pattern is in the opening of the planarization film in the non-emission region.

Abstract: The present disclosure discloses an array substrate, display panel and display device. The array substrate comprises: a base substrate, and peripheral routes and a plurality of pixel structures located on the base substrate. The orthographic projection of at least one pixel structure on the base substrate has an overlapping region with the periphery region in which the peripheral routes reside. The film layer where the peripheral routes reside is located between the film layer where the pixel structures reside and the base substrate or located at a side of the film layer. The array substrate allows the display region to be enlarged to cover a part or all of the periphery region where the peripheral routes reside. This can narrow down the bazel width of the display panel and even make it bezel-less.

Abstract: The present invention provides a double-sided display substrate and a manufacturing method thereof and a display device. The double-sided display substrate includes several sub-pixel units, the sub-pixel unit includes a front side light-emitting layer provided for front side displaying, a back side light-emitting layer provided for back side displaying, a pixel electrode layer, a common electrode layer, and a driving transistor, and the front side light-emitting layer and the back side light-emitting layer are interposed between a corresponding pixel electrode layer and the common electrode layer, respectively, the common electrode layer corresponding to the back side light-emitting layer and/or the front side light-emitting layer is disposed in the same layer as a gate electrode layer of the driving transistor. According to the double-sided display substrate, quick manufacture and spread of the double-sided display substrate are realized.

Abstract: An organic light-emitting display apparatus, including a substrate including a display region and a fan-out region outside the display region; a plurality of pixel electrodes in the display region of the substrate; a plurality of first signal lines connected electrically to the pixel electrodes in the display region in one direction and constituting a plurality of first line portions in the fan-out region; a plurality of second signal lines connected electrically to the pixel electrodes in the display region to intersect the first signal lines and constituting a plurality of second line portions in the fan-out region; and a dummy pattern between the first line portions.

Abstract: An organic light emitting diode display device comprises a substrate including a pixel region, the pixel region including a first portion and a second portion, a first electrode in the second portion of the pixel region, a bank layer separating the first portion and the second portion of the pixel region, an emitting layer in the second portion of the pixel region but not in the first portion of the pixel region, an emission assisting layer extending in the first portion of the pixel region and in the second portion of the pixel region, the emission assisting layer in the first portion of the pixel region being more conductive than the emission assisting layer in the second portion of the pixel region, and a second electrode on the emission assisting layer in the first portion of the pixel region and in the second portion of the pixel region.

Abstract: A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.

Abstract: A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Abstract: A semiconductor device of the embodiment includes an SiC layer of 4H—SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.

Abstract: A method is presented for tuning work functions of transistors. The method includes forming a work function stack over a semiconductor substrate, depositing a germanium oxide layer and a barrier layer over the work function stack, and annealing the germanium oxide layer to desorb oxygen therefrom to trigger oxidation of at least one conducting layer of the work function stack. The work function stack includes three layers, that is, a first layer being a TiN layer, a second layer being a titanium aluminum carbon (TiAlC) layer, and a third layer being a second TiN layer.

Abstract: A Schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by Schottky contact in a range where the p-type contact regions are not provided The p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.

Abstract: A source region of a MOSFET includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region.

Abstract: A super junction semiconductor device includes an impurity layer of a first (conductivity) type formed in a semiconductor portion having first and second parallel surfaces, a super junction structure between the first surface and impurity layer and including first columns of the first type and second columns of a second (conductivity) type, a body zone of the second type formed between the first surface and one of the second columns at least partially in the vertical projection of the second columns, and a field extension zone of the second type electrically connected to the body zone and arranged in the vertical projection of one of the columns. An area impurity density in the field extension zone is between 1×1012 and 5×1012 cm?2. A mean net impurity concentration in the field extension zone is higher than in the second columns and lower than in the body zone.

Abstract: Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.

Abstract: A transistor device includes: a first source region and a first drain region spaced apart from each other in a first direction of a semiconductor body; at least two gate regions arranged between the first source region and the first drain region and spaced apart from each other in a second direction of the semiconductor body; at least one drift region adjoining the first source region and electrically coupled to the first drain region; at least one compensation region adjoining the at least one drift region and the at least two gate regions; a MOSFET including a drain node connected to the first source region, a source node connected to the at least two gate region, and a gate node. Active regions of the MOSFET are integrated in the semiconductor body in a device region that is spaced apart from the at least two gate regions.