Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.

Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

Abstract: An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract: A device includes a vertical transistor comprising a first buried layer over a substrate, a first well over the first buried layer, a first gate in a first trench, wherein the first trench is formed partially through the first buried layer, and wherein a dielectric layer and the first gate are in the first trench, a second gate in a second trench, wherein the second trench is formed partially through the first buried layer, and wherein the second trench is of a same depth as the first trench, a first drain/source region and a second drain/source region formed on opposite sides of the first trench and a first lateral transistor comprising a second buried layer formed over the substrate, a second well over the second buried layer and drain/source regions over the second well.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device comprises a substrate; an isolation structure over the substrate; two fins extending from the substrate and through the isolation structure; a gate stack engaging channel regions of the two fins; a dielectric layer disposed over the isolation structure and adjacent to S/D regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. The lower portions of the four S/D features are surrounded at least partially by the dielectric layer. The upper portions of the four S/D features merge into two merged second S/D features with one on each side of the gate stack. Each of the two merged S/D features has a curvy top surface.

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor body, a first doped region, a second doped region, a gate and a dielectric layer. The semiconductor body is disposed on a dielectric substrate and has a protrusion portion, a first portion and a second portion. The first portion and the second portion are respectively disposed at two opposite sides of the protrusion portion. The first doped region is disposed in a top of the protrusion portion. The second doped region is disposed in an end of the first portion far away from the protrusion portion. The gate is disposed on the first portion and adjacent to the protrusion portion. The dielectric layer is disposed between the gate and the protrusion portion, and between the gate and the first portion.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Abstract: Various embodiments include methods and integrated circuit (IC) structures. In some cases, an IC can include: a substrate; a deep trench within the substrate; a buried oxide (BOX) layer adjacent the deep trench; a first fin structure over the deep trench; a second fin structure over the BOX layer; an ONO layer over the first fin structure; and a gate electrode contacting the ONO layer.

Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.

Abstract: A method of forming an SRAM cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate transistor, and a second vertical pass-gate transistor over a semiconductor substrate. The method includes forming a first conductive trace over a top surface of the first vertical pull-down transistor and the first vertical pass-gate transistor, forming a second conductive trace over a top surface of the second vertical pull-down transistor and the second vertical pass-gate transistor, and forming a first vertical pull-up transistor over a first portion of the first conductive trace. The method also includes forming a second vertical pull-up transistor over a first portion of the second conductive trace. The method also includes forming a first via over the first conductive trace and forming a second via over the second conductive trace.

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.

Abstract: A nonvolatile memory device includes a substrate including a device isolation layer defining an active region, a floating gate and a selection gate arranged side by side at intervals of a first gap over the substrate, a coupling plate formed in the device isolation layer and overlapped with the floating gate, and a contact plug suitable for electrically coupling the coupling plate and the selection gate.

Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.

Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.

Abstract: A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.

Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Abstract: A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.

Abstract: Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

Abstract: The memory string comprises: a first semiconductor layer; a stacked body in which a plurality of conductive layers and a plurality of interlayer insulating layers are stacked along a first direction above the first semiconductor layer; and a second semiconductor layer having a longitudinal direction along the first direction and provided above the first semiconductor layer. The memory insulating layer includes a charge accumulation layer between the second semiconductor layer and the plurality of the conductive layers. The core insulating layer has a longitudinal direction along the first direction, and is provided in the second semiconductor layer. The oxide film layer is provided between the core insulating layer and the second semiconductor layer.

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: A display apparatus includes a substrate partitioned into a central area and a peripheral area disposed adjacent to the central area. The central area includes a display area; a first insulating layer corresponding to the peripheral area of the substrate; at least one slit corresponding to a region of the first insulating layer; and a cladding layer, which covers the at least one slit, on the first insulating layer.

Abstract: To provide a display device in which plural kinds of circuits are formed over one substrate and plural kinds of transistors corresponding to characteristics of the plural kinds of circuits are provided. The display device includes a pixel portion and a driver circuit that drives the pixel portion over one substrate. The pixel portion includes a first transistor including a first oxide semiconductor film. The driver circuit includes a second transistor including a second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are formed over one insulating surface. A channel length of the first transistor is longer than a channel length of the second transistor. The channel length of the first transistor is greater than or equal to 2.5 micrometer.

Abstract: An oxide semiconductor transistor used in a pixel element of a display device and a method of manufacturing the same are disclosed. The oxide semiconductor transistor used in a pixel element of a display device comprises a substrate, a first gate electrode located on the substrate, a source electrode and a drain electrode located on the first gate electrode and a second gate electrode located on the source electrode and the drain electrode. Here, the first gate electrode is electrically connected to the second gate electrode, the same voltage is applied to the first gate electrode and the second gate electrode, and a width of the second gate electrode is shorter than a length between the source electrode and the drain electrode.

Abstract: A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

Abstract: A semiconductor device includes a first insulating layer having a first side wall, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a first electrode located below the oxide semiconductor layer and connected with one portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with the other portion of the oxide semiconductor layer.

Abstract: This disclosure provides an array substrate, comprising a substrate plate, and a thin film transistor and a pixel electrode formed on the substrate plate, said thin film transistor comprising a source/drain electrode, an active region and a gate electrode stacked sequentially on said substrate plate, wherein said source/drain electrode and said pixel electrode are arranged in the same layer on the substrate plate. According to this disclosure, while the properties of a high reflectivity and a high aperture ratio are guaranteed, the times of the patterning process are decreased and the process steps are saved, resulting in an improved production tempo and an effectively controlled cost. This disclosure also provides a method for fabricating an array substrate, a liquid crystal display panel comprising said array substrate and a reflective liquid crystal display.

Abstract: The present disclosure provides an array substrate and a method of manufacturing the same, and a display device comprising the array substrate. The array substrate comprises: a substrate; gate lines and data lines arranged to intersect one another on the substrate; a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines; and/or, a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines; wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer.

Abstract: The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out region, first signal lines and second signal lines are provided to intersect each other in the pixel region, and extend into the fan-out region, respectively, a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer. A size of the via hole formed in the second insulation layer by etching is smaller than that of the via hole formed in the prior art.

Abstract: The present application discloses a display panel comprising an array of pixel units, each pixel unit comprising a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the red sub-pixel comprising a red light emitting portion; the green sub-pixel comprising a green light emitting portion; and the blue sub-pixel comprising a blue light emitting portion; at least one of the red sub-pixel, the green sub-pixel, and the blue sub-pixel comprising a white light emitting portion for enhancing brightness of the at least one sub-pixel. A first white color coordinate and a second white color coordinate are substantially the same. The first white color coordinate is a white color coordinate of combined light of light emitted from the red sub-pixel, the green sub-pixel, and the blue sub-pixel. The second white color coordinate is a white color coordinate of combined light of light emitted from equal area units of the red light emitting portion, the green light emitting portion, and the blue light emitting portion.

Abstract: A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.

Abstract: A thin film transistor substrate includes a gate electrode, a channel layer overlapping the gate electrode, a source electrode overlapping the channel layer, a drain electrode overlapping the channel layer and the source electrode, and a spacer disposed between the source electrode and the drain electrode.

Abstract: A display device including a pixel electrode portion electrically connected to a thin film transistor; a semiconductor light emitting device configured to emit light to form an individual pixel, and including a conductive electrode; a conductive adhesive layer adhered to the semiconductor light emitting device, and configured to electrically connect the pixel electrode portion to the conductive electrode; and a buffer layer including an elastic material to protect the thin film transistor, and disposed between the thin film transistor and the conductive adhesive layer.

Abstract: A semiconductor device having a configuration hardly generating variations in the current value due to a deteriorated EL element is to be provided. A capacitance element is disposed between the gate and the source of a driving TFT, video signals are inputted to the gate electrode, and then it is in the floating state. Suppose an EL element is deteriorated and the anode potential rises, that is, the source potential of the driving TFT rises, the potential of the gate electrode of the driving TFT, being in the floating state by coupling of the capacitance element, is to rise by the same amount. Accordingly, even when the anode potential rises due to the deteriorated EL element, the rise is added to the gate electrode potential as it is, and the gate-source voltage of the driving TFT is allowed to be constant.

Abstract: An array substrate manufacturing method, including: forming an active layer of a thin film transistor, in which photoresist with a partial thickness at a location corresponding to a channel area between source/drain electrodes of the thin film transistor on the active layer is reserved; forming a source/drain metal layer, and further forming source/drain electrodes; lifting off the photoresist with the partial thickness on the channel area between the source/drain electrodes. The array substrate manufacturing method can avoid damaging the metal oxide layer in the etching process for source/drain electrodes, and lower production cost, simplify processes, and increase yield and product profit.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a display area and a non-display area. The non-display area includes at least one light sensor each including a light blocking layer on a substrate and for blocking light emitted from a backlight source; an insulating layer on the light blocking layer; a amorphous silicon layer on the insulating layer at a location corresponding to the light blocking layer and for sensing external light; an input electrode and an output electrode on the amorphous silicon layer and not contacting each other. The input electrode and the output electrode both contact the amorphous silicon layer, a part of the amorphous silicon layer between the input electrode and the output electrode forms a conductive channel. The output electrode is connected with a photoelectric detection circuit for inputting drain current generated by the conductive channel into the photoelectric detection circuit.

Abstract: A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche photodiodes operating in Geiger mode, quenching resistors connected in series to the respective avalanche photodiodes, and signal lines to which the quenching resistors are connected in parallel. A mounting substrate is configured so that a plurality of electrodes corresponding to the respective channels are arranged on a third principal surface side and so that a signal processing unit for processing output signals from the respective channels is arranged on a fourth principal surface side. In a semiconductor substrate, through-hole electrodes electrically connected to the signal lines are formed for the respective channels. The through-hole electrodes and the electrodes are electrically connected through bump electrodes.

Abstract: A pixel array in a solid-state imaging device includes first and second signal lines provided for each column. A pixel belongs to a first or second group on a row-by-row basis and includes a photoelectric conversion film, a FD line for accumulating signal charge, and an amplifier transistor for providing a voltage according to the signal charge. The pixel in the first group further includes a selection transistor for proving output voltage of the amplifier transistor to the first signal line, and the pixel in the second group further includes a selection transistor for proving output voltage of the amplifier transistor to the second signal line. The first signal line is disposed between the FD line in the first group and the second signal line, and the second signal line is disposed between the FD line in the second group and the first signal line.

Abstract: An image sensor includes a photodiode disposed in semiconductor material to accumulate image charge in response to light directed through a back side of the semiconductor material. A scattering structure is disposed proximate to the front side of the semiconductor material such that the light that is directed into the semiconductor material through the back side is scattered back through the photodiode. A deep trench isolation structure is disposed in the semiconductor material that isolates the photodiode and defines an optical path such that the light that is scattered back through the photodiode in the optical path is totally internally reflected by the DTI. An antireflective coating is disposed on the back side of the semiconductor material and totally internally reflects the light scattered by the scattering structure to confine the light to remain in the optical path until it is absorbed.

Abstract: Various embodiments include methods and apparatuses for forming and using pixels for image sensors. In one embodiment, an image sensor having at least two pixel electrodes per color region, and having at least two modes is disclosed. The example image sensor includes a first, unbinned, mode; and a second, binned, mode. In the first, unbinned mode, the at least two pixel electrodes per color region are to be reset to substantially similar levels. In the second, binned mode, a first pixel electrode of the at the least two pixel electrodes is to be reset to a high voltage that results in efficient collection of photocharge, and a second pixel electrode of the at the least two pixel electrodes is to be reset to a low voltage that results in less efficient collection of photocharge. Other methods and apparatuses are disclosed.

Abstract: A method for fabricating an image sensor in accordance with an embodiment of the inventive concepts may include forming first and second photodiodes within a substrate, forming first and second gate electrodes over the substrate, the first gate electrode vertically partially overlapping the first photodiode and the second gate electrode vertically partially overlapping the second photodiode, forming an impurity injection region comprising first and second type impurities between the first and the second gate electrodes, and performing an annealing process to form a floating diffusion region comprising the first type impurities and a channel region comprising the second type impurities. The channel region surrounds lateral surfaces and a bottom surface of the floating diffusion region.

Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.

Abstract: A photoelectric conversion device includes a photoelectric conversion region having a plurality of photoelectric conversion elements and a first MOS transistor configured to read a signal in response to an electric charge of each photoelectric conversion element; and a peripheral circuit region having a second MOS transistor configured to drive the first MOS transistor and/or amplify the signal read from the photoelectric conversion region, the photoelectric conversion region and the peripheral circuit region being located on the same semiconductor substrate, wherein an impurity concentration in a drain of the first MOS transistor is lower than an impurity concentration in a drain of the second MOS transistor.

Abstract: An image sensor includes a sensing layer, a filter unit, and a conductive layer. The filter unit is disposed on the sensing layer. The conductive layer surrounds the filter unit, and is disposed on the sensing layer. Therefore, light passing through the filter unit and falling on an adjacent sensing unit is minimized, and the image quality of the image sensor is improved.

Abstract: A photoelectric conversion device includes a photoelectric conversion unit disposed above a substrate and a reading circuit. The photoelectric conversion unit includes a first electrode disposed above the substrate, a second electrode disposed above the first electrode, and a photoelectric conversion film disposed between the first electrode and the second electrode. The second electrode includes an opening, and is disposed in contact with the photoelectric conversion film at a boundary between adjacent photoelectric conversion units. An insulating film is disposed in contact with the second electrode.