Abstract: The present invention provides a semiconductor device that can reduce the power consumption. The semiconductor device includes a plurality of sub-blocks each including a memory cell array, and a plurality of sub-search units corresponding to the respective sub-blocks. Of the data stored in each row of the memory cell array, each sub-block searches for data that matches the input search data according to a search instruction, and outputs a search result indicating hit or miss for each row. Each sub-search unit includes a flag data generation part that generates flag data for presearch to compare with part of the input search data based on the data stored in the corresponding memory cell array, and a search part that compares part of the input search data with the flag data generated by the flag data generation part, and outputs the search instruction to the corresponding sub-block based on the comparison result.

Abstract: An electronic device includes a storage device and a plurality of instruction units. The plurality of instruction units respectively instruct to turn off a power supply of the storage device. At least one instruction unit among the plurality of instruction units instructs to supply power to the storage device in accordance with a total of the number of power supply off operations for the storage device respectively instructed by the plurality of instruction units.

Abstract: A memory device includes a memory array storing data, a sense amplifier configured to read a plurality of data bits from the memory array and output a sense data signal including the data bits read from the memory array, a data multiplexer configured to receive the sense data signal and generate a plurality of group signals, a plurality of local data registers coupled to the data multiplexer, at least one of the local data registers being configured to generate a serial data output signal according to an output mode, and a plurality of output circuits coupled to respective ones of the plurality of local data registers, at least one of the output circuits being configured to receive the serial data output signal output from the at least one of the local data registers and sequentially output the data bits included in the serial data output signal.

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.

Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first power line located in a memory cell array region. The semiconductor device may include a second power line located in a column decoder region. The semiconductor device may include a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line. The semiconductor device may include a metal-oxide-semiconductor (MOS) capacitor located below the third power line.

Abstract: According to one embodiment, the magnetic memory includes a structure including a first magnetic layer and a conductive layer, a second magnetic layer, an intermediate layer, a third magnetic layer, and a fourth magnetic layer. The first magnetic layer is provided between the second magnetic layer and the conductive layer. The intermediate layer is provided between the second magnetic layer and the first magnetic layer. The third magnetic layer is provided between a second electrode and the intermediate layer. The fourth magnetic layer is provided between a first electrode and the intermediate layer. Further, the magnetic memory includes a first conductive-type first semiconductor layer electrically connected with the first electrode, a first conductive-type second semiconductor layer electrically connected with the second magnetic layer, and a second conductive-type third semiconductor layer electrically connected with the first semiconductor layer and the second semiconductor layer.

Abstract: In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.

Abstract: A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

Abstract: An integrated circuit memory contains a memory cell connected to a bit line that does not float during a portion or all of the read sensing part of the read cycle. The memory cell includes a data storage device. The data storage device may be a ferroelectric capacitor, a linear capacitor, a floating gate transistor, a magnetic device, a resistive device or other type of data storage device capable of placing a charge on the bit line corresponding to a specific data state of the memory cell. The bit line and a reference bit line are connected to a differential amplifier and precharged to specified voltages. Preferably, a self-nulling sense amplifier circuit is connected to the bit lines that compensates for sense amplifier offset by applying additional charges on the bit lines. Alternatively, charge sources may be connected to the bit lines to provide additional charges on the bit lines during the read cycle.

Abstract: A method and system for determining market estimates with market based measures. Market estimates for a set of time periods are received from plural qualified institutions that have agreed to a pre-determined set of regulations to participate in establishing, conducting business and processing transactions based on calculated market term estimates. A set of market term estimates (e.g., LIBOR, interest rates, etc.) is calculated in real-time for each time period in the set of time periods. The calculated set of market term estimates is sent to qualified institutions. The qualified institutions are required to conduct business and make transactions based on the calculated set of market term estimates. The calculated set of market term estimates is created and used on both cloud communication networks and non-cloud communications networks.

Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.

Abstract: A refresh control circuit may be provided. The refresh control circuit may include a row address control circuit configured to reset a corresponding block control signal among a plurality of block control signals, based on a stop signal for stopping a refresh operation of a specific block being enabled. The refresh control circuit may include a refresh enable control circuit configured to combine the plurality of block control signals and a plurality of refresh control signals, and output a refresh enable signal.

Abstract: A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC, a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.

Abstract: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

Abstract: A semiconductor device includes a first row address generation circuit and a second row address generation circuit. The first row address generation circuit generates a first row address for refreshing memory cells connected to word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal. The second row address generation circuit generates a second row address for refreshing memory cells connected to word lines included in a first down block and a second down block from the refresh command and the active signal in response to the period selection signal and a second period signal.

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Abstract: The present invention provides a memory cell of a static random access memory based on resistance reinforcement, which includes a latch circuit and a bit selection circuit. The latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network. The bit selection circuit consists of NMOS transistors N5 and N6. The latch circuit form four storage nodes X1, X1B, X2, X2B. Compared to the conventional memory cell of a 6T structure, a resistance-capacitance network is added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset at a cost of increasing a small amount of area, thus ensuring correctness of data.

Abstract: Examples described in this disclosure relate to a memory cell having a magnetic Josephson junction device with a doped magnetic layer. In one example, a memory cell including a magnetic Josephson junction (MJJ) device is provided. The MJJ device may include at least a first layer formed above a second layer and a third layer formed below the second layer, where the first layer is a free magnetic layer, the second layer is a non-magnetic layer, where the third layer is a fixed magnetic layer. The free magnetic layer may comprise a magnetic alloy doped with at least one of Vanadium, Zirconium, Molybdenum, or Hafnium, and the fixed magnetic layer may comprise an un-doped second magnetic alloy.

Abstract: Apparatus and method for performing burst mode programming in a memory system are disclosed. A memory system may program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming may be selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which may include a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, may be used to program the blocks selected for burst mode programming. In this regard, burst mode programming may be performed more quickly than normal mode programming.

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured, based on a metric associated with a portion of the non-volatile memory, to store a read technique indicator that indicates that the portion is to be read using a high-reliability read technique.

Abstract: A non-volatile memory device of the present disclosure includes: a plurality of bit lines; a plurality of word lines; a memory cell array having a plurality of memory cells each including a non-volatile storage element and being disposed at crossing sections of the bit lines and the word lines; a reference voltage generator circuit that generates a readout reference voltage serving as a reference for discrimination of data values stored on the memory cells; a readout circuit that reads the data values stored on the memory cells by detecting values of readout voltages from the memory cells relative to the readout reference voltage in a state where a predetermined current-limited readout current is applied to the bit lines; and an address compensation circuit that changes the readout reference voltage in accordance with a placement position of a memory cell to be read of the memory cells in the readout circuit.

Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

Abstract: Receiving one or more first write commands to write a first set of data to a storage device. The first set of data is programmed in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells. One or more second write commands to write a second set of data to the storage device is received. The second set of data is programmed in the plurality of memory cells with which the first set of data is programmed. The second set of data is programmed using a second plurality of program levels available in the plurality of memory cells different from the first plurality of program levels. Each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits.

Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory includes a channel layer; a data storage layer disposed on the channel layer; a plurality of control gates arranged on the data storage layer and spaced apart from one another; and one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.

Abstract: Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.

Abstract: Provided is a one-time programmable (OTP) memory device, which includes a data input circuit that receives a supply voltage and applies the supply voltage to one of a plurality of bit lines that is selected by a write switch, and an OTP memory cell array including a plurality of OTP memory cells arranged in a plurality of rows and columns. The OTP memory cells on the same row connected to the same bit line. The OTP memory device also includes a column decoder that selects one of the plurality of columns of the OTP memory cells to apply the supply voltage thereto, and a detection amplifier that performs a read operation of the OTP memory cells connected to one of the plurality of bit lines that is selected by a read switch.

Abstract: A method and apparatus may include determining a failure of a drive. The drive comprises a plurality of platters, each platter comprises two half-platters, and data of the drive is stored via erasure encoding. The method can also include rebuilding a portion of the drive upon which the failure occurred, wherein other portions of the drive are not rebuilt.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

Abstract: A plasma confinement system is provided that includes a confinement chamber that includes one or more enclosures of respective helicity injectors. The one or more enclosures are coupled to ports at an outer radius of the confinement chamber. The system further includes one or more conductive coils aligned substantially parallel to the one or more enclosures and a further set of one or more conductive coils respectively surrounding portions of the one or more enclosures. Currents may be provided to the sets of conductive coils to energize a gas within the confinement chamber into a plasma. Further, a heat-exchange system is provided that includes an inner wall, an intermediate wall, an outer wall, and pipe sections configured to carry coolant through cavities formed by the walls.

Abstract: Method and apparatus for heating and/or compressing plasmas to thermonuclear temperatures and densities are provided. In one aspect, at least one of at least two plasmoids separated by a distance is accelerated towards the other. The plasmoids interact, for instance to form a resultant plasmoid, to convert a kinetic energy into a thermal energy. The resultant plasmoid is confined in a high energy density state using a magnetic field. One or more plasmoids may be compressed. Energy may be recovered, for example via a blanket and/or directly via one or more coils that create a magnetic field and/or circuits that control the coils.

Abstract: A method is provided for coating the substrate of a component, such as a zirconium alloy cladding tube, for use in a water cooled nuclear reactor under normal operating conditions and under high temperature oxidation conditions. The method includes heating a pressurized carrier gas to a temperature between 200° C. and 1200° C., adding chromium or chromium-based alloy particles having an average diameter of 20 microns or less to the heated carrier gas, and spraying the carrier gas and particles onto the substrate at a velocity, preferably from 800 to 4000 ft./sec. (about 243.84 to 1219.20 meters/sec.), to form a chromium and/or chromium-based alloy coating on the substrate to a desired thickness.

Abstract: A method is described herein for coating the substrate of a component for use in a water cooled nuclear reactor to provide a barrier against corrosion. The method includes providing a zirconium alloy substrate; and coating the substrate with particles selected from the group consisting of metal oxides, metal nitrides, FeCrAl, FeCrAlY, and high entropy alloys. Depending on the metal alloy chosen for the coating material, a cold spray or a plasma arc spray process may be employed for depositing various particles onto the substrate. An interlayer of a different material, such as a Mo, Nb, Ta, or W transition metal or a high entropy alloy, may be positioned in between the Zr-alloy substrate and corrosion barrier layer.

Abstract: A system for attenuating seismic forces includes a reactor pressure vessel containing nuclear fuel and a containment vessel that houses the reactor pressure vessel. Both the reactor pressure vessel and the containment vessel may include a bottom head. Additionally, the system may include a base support that is configured to contact a support surface on which the containment vessel is positioned in a substantially vertical orientation. An attenuation device may be located between the bottom head of the reactor pressure vessel and the bottom head of the containment vessel. Seismic forces that travel from the base support to the reactor pressure vessel via the containment vessel may be attenuated by the attenuation device in a direction that is substantially lateral to the vertical orientation of the containment vessel.

Abstract: An apparatus for supporting radioactive fuel assemblies, such as spent nuclear fuel. In one aspect, the invention is an apparatus, which can be in the form of a fuel rack having adjustable height pedestals.

Abstract: A method of forming one or more structures by additive manufacturing comprises introducing a first layer of a powder mixture comprising graphite and a fuel on a surface of a substrate. The first layer is at least partially compacted and then exposed to laser radiation to form a first layer of material comprising the fuel dispersed within a graphite matrix material. At least a second layer of the powder mixture is provided over the first layer of material and exposed to laser radiation to form inter-granular bonds between the second layer and the first layer. Related structures and methods of forming one or more structures are also disclosed.

Abstract: The present invention relates to filters used to remove debris from water being sucked into a piping system. It has particular application use in nuclear power plants, which, after a loss of coolant accident, must pump cooling water back into the reactor core from a collection sump. This water may contain various types of debris that must be removed before the water is sent back into the reactor cooling system. There are restrictions on the allowable pressure drop across the strainer and the space available for installing this equipment. The finned strainer of the present invention addresses these issues while maximizing the quantity of debris filtered from the water.

Abstract: The present invention relates to a radiation shielding material. A radiation shielding material containing a lead component, which is used in the related art, has a problem in that the radiation shielding material is harmful to a human body and is heavy in weight.

Abstract: A container and system for handling damaged nuclear fuel, and a method of making the same. In one embodiment, the invention is a damaged fuel container having a specially designed top cap that can be detachably coupled to the elongated tubular wall by simply translating the top cap into proper position within the elongated tubular wall, wherein biased locking elements automatically lock the top cap to the elongated tubular wall. In another embodiment, the vent screens of the damaged fuel container are integrally formed rather than being separate components. In still other embodiments, the lower vent screens are arranged on an upstanding portion of the damaged fuel container. In an even further embodiment, the elongated tubular wall is formed by an extrusion process.

Abstract: The present invention relates to a method and an apparatus for separating and recovering a radioisotope from a solution. More particularly, certain embodiments of the invention relate to a method for recovering a radioisotope from a solution by electro-trapping and release using a microfluidic cell (10). The radioisotope may subsequently be used in the preparation of radiopharmaceuticals.

Abstract: A radionuclide generation system comprises a tube system configured to permit insertion and removal of irradiation targets into an instrumentation finger of a nuclear reactor, and an irradiation target drive system configured to insert the irradiation targets into the instrumentation finger and to remove the irradiation targets from the instrumentation finger. The radionuclide generation system further comprises an instrumentation and control unit which is linked to an online core monitoring system and being configured to calculate an optimum irradiation time for the irradiation targets based on the actual state of the reactor as provided by the online core monitoring system.

Abstract: An irradiation target processing system for insertion and retrieving irradiation targets into and from an instrumentation tube in a nuclear reactor core comprises, a target retrieving system, target insertion system and transport gas supply system, mounted on a movable support, wherein: the target retrieving system comprises a target exit port coupled to a target storage container and exhaust system; the target insertion system comprises a target filling device, target retention tubing with target supply junction connectable to the instrumentation tube, and a target diverter coupled to the target filling device, target retention tubing and target retrieving system; and the transport gas supply system comprises a first gas supply tubing coupled to the exit port of the target retrieving system, a second gas supply tubing coupled to a junction for supplying gas to the instrumentation tube, and a transport gas supply junction coupled to the first and second gas supply tubing.

Abstract: Systems and methods of fabricating electrodes, including thin metallic films, include depositing a first metallic layer on a substrate and passivating the deposited layer. The processes of deposition and passivation may be done sequentially. In some embodiments, a plurality of substrates may be coated with a metallic layer and further processed at a later time, including passivation and disposal of additional layers as discussed herein.