Patents Issued in May 1, 2018
  • Patent number: 9960286
    Abstract: A bus bar for a silicon solar cell. The bus bar is a strip of electrically conductive material with a plurality of protrusions extending from at least one side of the bus bar.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: May 1, 2018
    Assignee: UTILIGHT LTD.
    Inventor: Moshe Finarov
  • Patent number: 9960287
    Abstract: A passivation layer is deposited on a first portion of a region of the solar cell. A grid line is deposited on a second portion of the region. The passivation layer is annealed to drive chemical species from the passivation layer to deactivate an electrical activity of a dopant in the first portion of the region of the solar cell.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 1, 2018
    Assignee: PICASOLAR, INC.
    Inventors: Seth Daniel Shumate, Douglas Arthur Hutchings, Hafeezuddin Mohammed, Matthew Young, Scott Little
  • Patent number: 9960288
    Abstract: Some implementations provide a device (e.g., solar panel) that includes an active layer and a solar absorbance layer. The active layer includes a first N-type layer and a first P-type layer. The solar absorbance layer is coupled to a first surface of the active layer. The solar absorbance layer includes a polymer composite. In some implementations, the polymer composite includes one of at least metal salts and/or carbon nanotubes. In some implementations, the active layer is configured to provide the photovoltaic effect. In some implementations, the active layer further includes a second N-type layer and a second P-type layer. In some implementations, the active layer is configured to provide the thermoelectric effect. In some implementations, the device further includes a cooling layer coupled to a second surface of the active layer. In some implementations, the cooling layer includes one of at least zinc oxides, indium oxides, and/or carbon nanotubes.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 1, 2018
    Assignee: The United State of America as represented by the Administrator of NASA
    Inventors: Jin Ho Kang, Chase Taylor, Cheol Park, Godfrey Sauti, Luke Gibbons, Iseley Marshall, Sharon E. Lowther, Peter T. Lillehei, Joycelyn S. Harrison, Robert G. Bryant
  • Patent number: 9960289
    Abstract: A solder joint material includes a copper-based metal material including mainly a copper, a surface-treated layer that is provided on the copper-based metal material and includes an amorphous layer including oxygen and a metal with a higher oxygen affinity than a copper, and a Sn-based solder plating layer provided on the surface-treated layer.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 1, 2018
    Assignee: HITACHI METALS, LTD.
    Inventors: Hideyuki Sagawa, Keisuke Fujito, Takayuki Tsuji, Hiromitsu Kuroda
  • Patent number: 9960290
    Abstract: A solar cell is disclosed. The disclosed solar cell includes a semiconductor substrate, a conductive region disposed in or on the semiconductor substrate, and an electrode including a plurality of finger lines connected to the conductive region, and formed to extend in a first direction while being parallel, and 6 or more bus bar lines formed to extend in a second direction crossing the first direction. Each bus bar line has a width of 35 to 350 ?m at at least a portion thereof. Each bus bar line has a distance between opposite ends thereof in the second direction smaller than a distance between outermost ones of the finger lines respectively disposed at opposite sides in the second direction.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 1, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Jinsung Kim, Sunghyun Hwang, Donghae Oh
  • Patent number: 9960291
    Abstract: A solar cell includes a support substrate; a back electrode layer on the a support substrate; a light absorbing layer on the back electrode layer; a buffer layer on the light absorbing layer; a front electrode layer on the buffer layer; and a fourth through hole formed through the back electrode layer, the light absorbing layer, the buffer layer and the front electrode layer, wherein at least a portion of the fourth through hole is inclined with respect to a top surface of the support substrate.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 1, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Jong Seon Jeong
  • Patent number: 9960292
    Abstract: A solar cell includes negative metal contact fingers and positive metal contact fingers. The negative metal contact fingers are interdigitated with the positive metal contact fingers. The metal contact fingers, both positive and negative, have a radial design where they radially extend to surround at least 25% of a perimeter of a corresponding contact pad. The metal contact fingers have bend points, which collectively form a radial pattern with a center point within the contact pad. Exactly two metal contact pads merge into a single leading metal contact pad that is wider than either of the exactly two metal contact pads.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 1, 2018
    Assignee: SunPower Corporation
    Inventors: Staffan Westerberg, Peter John Cousins
  • Patent number: 9960293
    Abstract: The present invention relates to a method for preparing a transparent electrode using a carbon nanotube (CNT) film, and more particularly, to a method for preparing a transparent electrode, the method comprising the steps of forming a CNT film on a desired substrate using a dispersed solution of CNT and then reducing/forming metal nanoparticles on the surface of the CNT film. According to the present invention, a transparent electrode in which gold nanoparticles are formed on the surface of high density CNT film having high purity, can be prepared. The inventive transparent electrode has high visible ray penetration and an excellent electrical conductivity by hyperfine metal particles uniformly formed on the surface thereof as well as a uniform increase in electrical conductivity over the whole CNT film, and thus it can be applied to various displays as well as image sensors, solar cells, touch panels, digital papers, electromagnetic shielding agents, static charge preventing agents and the like.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: May 1, 2018
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Hee-Tae Jung, Byung-Seon Kong
  • Patent number: 9960294
    Abstract: The invention provides highly fluorescent materials comprising a compound of formula (I): The chromophores are particularly useful for absorption and emission of photons in the visible and near infrared wavelength range. The photo-stable highly luminescent chromophores are useful in various applications, including in wavelength conversion films. Wavelength conversion films have the potential to significantly enhance the solar harvesting efficiency of photovoltaic or solar cell devices.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: May 1, 2018
    Assignee: Nitto Denko Corporation
    Inventors: Mila Rachwal, Michiharu Yamamoto
  • Patent number: 9960295
    Abstract: A Single-Photon Avalanche Diode (SPAD) is disclosed. The SPAD may include an active region for detection of incident radiation, and a cover configured to shield part of the active region from the incident radiation. An array is also disclosed and includes SPADs arranged in rows and columns. A method for making the SPAD is also disclosed.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: May 1, 2018
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Stuart McLeod, Pascal Mellot, Lindsay Grant
  • Patent number: 9960296
    Abstract: A solar energy collecting system includes a substrate and at least one solar chip. The substrate includes a first surface, a second surface and a plurality of lateral surfaces, wherein the first surface faces the second surface, the lateral surfaces are adjacent to the first and second surfaces, and a first micro structure is formed on the first or the second surface. The solar chip is near one of the lateral surfaces. Solar light penetrates the first and the second surface and is refracted or reflected by the first micro structure to leave the substrate via the lateral surface and be absorbed by the solar chip.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: May 1, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Hui-Hsiung Lin, Chia-Wei Yu, Yu-Nan Pao
  • Patent number: 9960297
    Abstract: Embodiments of the invention describe apparatuses, optical systems, and methods related to utilizing optical cladding layers. According to one embodiment, a hybrid optical device includes a silicon semiconductor layer and a III-V semiconductor layer having an overlapping region, wherein a majority of a field of an optical mode in the overlapping region is to be contained in the III-V semiconductor layer. A cladding region between the silicon semiconductor layer and the III-V semiconductor layer has a spatial property to substantially confine the optical mode to the III-V semiconductor layer and enable heat dissipation through the silicon semiconductor layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 1, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Erik Johan Norberg, Anand Ramaswamy, Brian Koch
  • Patent number: 9960298
    Abstract: A method for the preparation of copper indium gallium diselenide/disulfide (CIGS) nanoparticles utilizes a copper-rich stoichiometry. The copper-rich CIGS nanoparticles are capped with organo-chalcogen ligands, rendering the nanoparticles processable in organic solvents. The nanoparticles may be deposited on a substrate and thermally processed in a chalcogen-rich atmosphere to facilitate conversion of the excess copper to copper selenide or copper sulfide that may act as a sintering flux to promote liquid phase sintering and thus the growth of large grains. The nanoparticles so produced may be used to fabricate CIGS-based photovoltaic devices.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 1, 2018
    Assignee: Nanoco Technologies Ltd.
    Inventors: Christopher Newman, Ombretta Masala, Paul Kirkham, Cary Allen, Stephen Whitelegg
  • Patent number: 9960299
    Abstract: Disclosed is an avalanche photodiode using a silicon nanowire, including a first silicon nanowire formed of silicon (Si), a first conductive region formed by doping one surface of the first silicon nanowire with a first dopant, and a second conductive region formed by doping one surface of the first silicon nanowire with a second dopant having a conductive type different from that of the first dopant so as to be arranged continuously in a longitudinal direction from the first conductive region, wherein, when the magnitude of a reverse voltage applied to both ends of the first silicon nanowire is equal to or greater than a preset breakdown voltage, avalanche multiplication of inner current occurs due to the incidence of light from the outside.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: May 1, 2018
    Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Suk Won Jung, Yeon Shik Choi, Young Chang Jo, Jae Gi Son, Ki Man Jeon, Woo Kyeong Seong, Kook Nyung Lee, Min Ho Lee, Hyuck Ki Hong
  • Patent number: 9960300
    Abstract: The invention relates to flexible photovoltaic (PV) modules, and in particular to those having a polyvinylidene fluoride (PVDF) glazing layer. The PVDF layer may be a monolayer or a multi-layer structure.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 1, 2018
    Assignee: Arkema Inc.
    Inventors: Gregory S. O'Brien, Jiaxin Jason Ge
  • Patent number: 9960301
    Abstract: A flexible, lightweight photovoltaic cell array includes one or more individual photovoltaic cell strings attached to a polyimide film substrate and covered with a polyvinyl fluoride film. Each photovoltaic cell string includes one or more photovoltaic cells attached to a flexible printed circuit board. The photovoltaic cell array may be manufactured by a method that includes bonding at least one photovoltaic cell to a flexible printed circuit board, mounting the flexible printed circuit board on a polyimide film substrate, and covering the flexible printed circuit board with a substantially transparent polyvinyl fluoride film.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: May 1, 2018
    Assignee: Orbital Sciences Corporation
    Inventor: Robert Minelli
  • Patent number: 9960302
    Abstract: A solar module is provided. The solar module includes a number of photovoltaic structures. Each photovoltaic structure has an interdigitated back contact, and the photovoltaic structures are cascaded, wherein any two adjacent structures are electrically coupled by overlapping their edges.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 1, 2018
    Assignee: Tesla, Inc.
    Inventors: Jiunn Benjamin Heng, Peter J. Rive, Zhigang Xie, Bobby Yang
  • Patent number: 9960303
    Abstract: Device for concentrating and harvesting sunlight comprising: A panel having rigid layer having a patterned electrical circuit thereon. An array of sunlight concentrating and harvesting units, each unit being formed by at least one rigid element and a portion of the rigid layer; and including: a rigid optical concentrating element, a photovoltaic cell sandwiched within the panel for converting sunlight into electrical energy, and an electrical conductor. The electrical conductor being the primary heat sink for the photovoltaic cell, the photovoltaic cell being primarily cooled via conduction. The electrical conductor and the optical concentrating element being dimensioned and arranged within the unit such that the electrical conductor does not materially impede transmission of sunlight to the photovoltaic cell. The electrical conductor transmitting electrical and thermal energy received from the photovoltaic cell away from the unit.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 1, 2018
    Assignee: MORGAN SOLAR INC.
    Inventors: John Paul Morgan, Michael Sinclair, Nigel Morris, Pascal Dufour, Stefan Myrskog, Brett Barnes, Philip Chang, Stephen Caelers
  • Patent number: 9960304
    Abstract: Provided is a solar cell for which accurate mutual alignment between a condenser lens and a power generating element corresponding thereto can be performed. In a solar cell 23, a plurality of grid electrodes 31 each formed in a linear shape are arrayed on a light receiving surface 23a along the width direction of the light receiving surface 23a. The plurality of grid electrodes 31 include a first center grid electrode 31a forming a cross portion 34 exhibiting a center-specific geometry caused by electrodes crossing each other at the center of the light receiving surface 23a.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 1, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Inagaki, Kenji Saito, Yoshiya Abiko, Koji Mori, Takashi Iwasaki, Yoshiki Kuhara
  • Patent number: 9960305
    Abstract: A wafer precursor for creating photovoltaic (PV) concentrator modules and a method for fabricating solar concentrator modules using the wafer precursor. The method includes providing a crystalline silicon wafer substrate that can be used to make multiple concentrator cells to be incorporated into concentrator modules. The method also includes applying fingers as horizontal grid lines onto the crystalline silicon wafer substrate. The method also includes applying bus bars onto the crystalline silicon wafer substrate to form separate top grid structures. The number of separate top grid structures is at least two when the concentrator module is part of an optical system that has a concentration ratio of between about 8 and about 16 times sunlight. The number of top grid structures is at least three when the concentrator module is part of an optical system that has a concentration ratio of between about 17 and about 50.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: May 1, 2018
    Assignee: The United States of America as represented by Secretary of the Navy
    Inventor: Randall B. Olsen
  • Patent number: 9960306
    Abstract: A condensing photoelectric conversion apparatus includes a first photoelectric conversion module and a second photoelectric conversion module. The first and second condensing photoelectric conversion modules each include a power generating element, a condensing lens located on the power generating element and having a front surface with a convex portion and a flat rear surface, a transparent first resin located between the power generating element and the rear surface of the condensing lens, a colored second resin located on the rear surface of the condensing lens and around the power generating element, and a third resin located between the condensing lens of the first photoelectric conversion module and the condensing lens of the second photoelectric conversion module, and having a refractive index n1 satisfying a relational expression n0?0.05?n1?n0+1.0 with a refractive index n0 of the condensing lens.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: May 1, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tohru Nakagawa, Akio Matsushita
  • Patent number: 9960307
    Abstract: A method to produce thin film solar cells in superstrate or substrate configuration is an efficient way to minimize the loss due to absorption in CdS layer and to eliminate the CdCl2 activation treatment step. This is achieved by applying a sacrificial metal-halide layer between the CdS-layer and the CdTe-layer of the solar cells.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 1, 2018
    Assignees: China Triumph International Engineering Co., Ltd., CTF SOLAR GMBH
    Inventors: Krishnakumar Velappan, Bastian Siepchen, Bettina Späth, Christian Drost, Shou Peng
  • Patent number: 9960308
    Abstract: A number of micro-sized rectangular dot-like n-type semiconductor regions 121 are created in a p-type semiconductor region which is a base body 11. Contact parts 14, each of which is in contact with one n-type semiconductor region 121 and almost entirely covers the same region, are mutually connected by a wire part 15 as a common cathode terminal. The n-type semiconductor regions 121 receives no light; their function is to collect carriers generated within and outside the surrounding depletion layers. Appropriate setting of the spacing of the n-type semiconductor regions 121 enables efficient collection of the carriers generated in the p-type semiconductor region while improving the SN ratio of the photo-detection signal by a noise-reduction effect due to a decrease in the p-n junction capacitance. Carriers originating from light of shorter wavelengths are barely reflected in the photo-detection signal. Thus, unfavorable influences of the shorter wavelengths of light are eliminated.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 1, 2018
    Assignee: MICRO SIGNAL CO., LTD.
    Inventors: Kunihiro Watanabe, Masaya Okada, Kazunori Nohara
  • Patent number: 9960309
    Abstract: A photoelectronic device includes a semiconductor substrate doped with a first type impurity, a second semiconductor layer doped with a second type impurity of an opposite type to the first type impurity, a transparent electrode formed on a second surface of the second semiconductor layer, the second surface being opposite a first surface on which the semiconductor substrate is formed, and a barrier layer disposed between the second semiconductor layer and the semiconductor substrate or between the second semiconductor layer and the transparent electrode. The second semiconductor layer has a band gap energy less than that of the semiconductor substrate, and the barrier layer includes a semiconductor material or an insulator having a band gap greater than that of the semiconductor substrate.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinseong Heo, Kiyoung Lee, Jaeho Lee, Sangyeob Lee, Eunkyu Lee, Seongjun Park
  • Patent number: 9960310
    Abstract: A combination of doping, rapid pulsed optical and/or thermal annealing, and unique detector structure reduces or eliminates sources of electronic noise in a CdZnTe (CZT) detector. According to several embodiments, methods of forming a detector exhibiting minimal electronic noise include: pulse-annealing at least one surface of a detector comprising CZT for one or more pulses, each pulse having a duration of ˜0.1 seconds or less. The at least one surface may optionally be ion-implanted. In another embodiment, a CZT detector includes a detector surface with two or more electrodes operating at different electric potentials and coupled to the detector surface; and one or more ion-implanted CZT surfaces on or in the detector surface, each of the one or more ion-implanted CZT surfaces being independently connected to one of the two or more electrodes and the surface of the detector. At least two of the ion-implanted surfaces are in electrical contact.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 1, 2018
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Lars Voss, Adam Conway, Art Nelson, Rebecca J. Nikolic, Stephen A. Payne, Erik Lars Swanberg, Jr.
  • Patent number: 9960311
    Abstract: An illuminated address display for a building and residence having a housing with a front wall with an inclined upper portion and vertical lower portion, solar cells on the inclined upper portion and a group of small rectangular panels suspended from the lower portion of the housing. On the small rectangular housing there is an address identifier consisting of alphanumeric digits which disclose the address of the residence or building. The alphanumeric digits have segments which extend through the panels and are backlit by light emitting diodes which are mounted on a removable cover on the bottom of the housing. Inside of the housing are batteries and a solar charge controller to prevent overcharging of the batteries and an “on/off” switch.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 1, 2018
    Inventor: Isaac Benezra
  • Patent number: 9960312
    Abstract: The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: May 1, 2018
    Inventors: Kurt H. Weiner, Gaurav Verma
  • Patent number: 9960313
    Abstract: A solar battery module and manufacturing method for a solar battery module having improved output are provided. The solar battery module 1 is a transparent substrate 10, transparent resin layer 13b, solar battery cell 12, colored resin layer 13a and back sheet 11 laminated in this order. The light-receiving surface 12a of the solar battery cell 12 faces the transparent resin layer 13b side. The backside 12b of the solar battery cell faces the colored resin layer 13a. The MFR [melt flow rate] of the transparent resin layer 13b is lower than the MFR of the colored resin layer 13a.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 1, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Masanori Maeda
  • Patent number: 9960314
    Abstract: Compositions for solution-based deposition of CIGS films are described. The compositions include ternary, quaternary or quinary chalcogenide nanoparticles (i.e., CIGS nanoparticles) and one or more inorganic salts dissolved or dispersed in a solvent to form an ink. The ink can be deposited on a substrate by conventional coating techniques and then annealed to form a crystalline layer. Further processing can be employed to fabricate a PV device. The inorganic salts are included to (i) tune the stoichiometry of the CIGS precursor ink to a desirable ratio, thus tuning the semiconductor band gap, to (ii) dope the CIGS layer with additives, such as Sb and/or Na, to promote grain growth, and/or to (iii) modify and improve the coating properties of the CIGS precursor ink.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: May 1, 2018
    Assignee: Nanoco Technologies Ltd.
    Inventors: Zugang Liu, Cary Allen
  • Patent number: 9960315
    Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 1, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9960316
    Abstract: A composite substrate includes a sapphire substrate and a layer of a nitride of a group 13 element provided on the sapphire substrate. The layer of the nitride of the group 13 element is composed of gallium nitride, aluminum nitride or gallium aluminum nitride. The composite substrate satisfies the following formulas (1), (2) and (3). A laser light is irradiated to the composite substrate from the side of the sapphire substrate to decompose crystal lattice structure at an interface between the sapphire substrate and the layer of the nitride of the group 13 element. 5.0?(an average thickness (?m) of the layer of the nitride of the group 13 element/a diameter (mm) of the sapphire substrate)?10.0 . . . (1); 0.1? a warpage (mm) of said composite substrate×(50/a diameter (mm) of said composite substrate)2?0.6 . . . (2); 1.10?a maximum value (?m) of a thickness of said layer of said nitride of said group 13 element/a minimum value (?m) of said thickness of said layer of said nitride of said group 13 element . . .
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 1, 2018
    Assignee: NGK INSULATORS, LTD.
    Inventors: Katsuhiro Imai, Makoto Iwai, Takanao Shimodaira
  • Patent number: 9960317
    Abstract: A lamination includes a sheet substrate and a display element layer. The sheet substrate includes a plurality of product regions cut out into a plurality of products and a blank region surrounding the product regions. The display element layer is formed on each of a plurality of display areas placed on each of the plurality of product regions for displaying an image. The sheet substrate adheres to a top of a substrate. The substrate has light transmissivity. A protective film is adhered to the lamination so as to cover the display areas. A divider line is formed in a blank region that surrounds the product regions by removing a portion of the lamination. The substrate is removed from the sheet substrate by irradiating the sheet substrate with a laser beam.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 1, 2018
    Assignee: Japan Display Inc.
    Inventors: Kenji Toribatake, Kazufumi Watabe
  • Patent number: 9960318
    Abstract: A light emitting diode includes a light emitting structure including first and second conductive type semiconductor layers, an active layer, a first electrode electrically connected to the first conductive type semiconductor layer, a current blocking layer disposed on a lower surface of the light emitting structure, and a second electrode electrically connected to the second conductive type semiconductor layer. The second electrode includes a first reflective metal layer adjoining the second conductive type semiconductor layer, and a second reflective metal layer covering a lower surface of the current blocking layer and a lower surface of the first reflective metal layer, and adjoining the second conductive type semiconductor layer. A contact resistance between the second reflective metal layer and the second conductive type semiconductor layer is higher than a contact resistance between the first reflective metal layer and the second conductive type semiconductor layer.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: May 1, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Tae Gyun Kim, Joon Hee Lee, Ki Hyun Kim, Sung Su Son
  • Patent number: 9960319
    Abstract: The surface of a light emitting device is roughened to enhance the light extraction efficiency of the surface, but the amount of roughened area is selected to achieve a desired level of light extraction efficiency. Photo-lithographic techniques may be used to create a mask that limits the roughening to select areas of the light emitting surface. Because the amount of roughened area can be precisely controlled, the light extraction efficiency can be precisely controlled, substantially independent of the particular process used to roughen the surface. Additionally, the selective roughening of the surface may be used to achieve a desired light emission output pattern.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: May 1, 2018
    Assignee: Lumileds LLC
    Inventors: Maciej Benedict, Paul S. Martin, Boris Kharas
  • Patent number: 9960320
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first metal pillar, a second metal pillar, and an insulating layer. The semiconductor layer includes a first surface, a second surface, and a light emitting layer. The first metal pillar is electrically connected to the second surface. The first metal pillar includes first and second metal layers. The first metal layer is provided between the second surface and at least a part of the second metal layer. The second metal pillar is arranged side by side with the first metal pillar, and electrically connected to the second surface. The second metal pillar includes third and fourth metal layers. The third metal layer is provided between the second surface and at least a part of the fourth metal layer. The insulating layer is provided between the first and second metal pillars.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 1, 2018
    Assignee: ALPAD CORPORATION
    Inventors: Susumu Obata, Akihiro Kojima
  • Patent number: 9960321
    Abstract: A multi-layered contact to a semiconductor structure and a method of making is described. In one embodiment, the contact includes a discontinuous Chromium layer formed over the semiconductor structure. A discontinuous Titanium layer is formed directly on the Chromium layer, wherein portions of the Titanium layer extend into at least some of the discontinuous sections of the Chromium layer. A discontinuous Aluminum layer is formed directly on the Chromium layer, wherein portions of the Aluminum layer extend into at least some of the discontinuous sections of the Titanium layer and the Chromium layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 1, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky
  • Patent number: 9960322
    Abstract: Solid state lighting devices include one or more notch filtering materials arranged to filter light emissions to exhibit a spectral notch. At least one notch filtering material may be arranged in at least one coating deposited directly on an emitter chip or on a lumiphoric material that itself is coated or otherwise deposited on an emitter chip. A notch filtering material may be combined with a lumiphoric material. Emissions of a resulting lighting device may include a CRI Ra value of at least 80 and a GAI value in a range of from 75 to 100 or from 80 to 100.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: May 1, 2018
    Assignee: CREE, INC.
    Inventor: Antony Paul van de Ven
  • Patent number: 9960323
    Abstract: A LED module includes a lens group, an LED illuminant, a circuit board and a heat sink; the LED illuminant includes an LED chip and a heat sink holder; the LED chip is attached to the heat sink holder which is disposed on the circuit board by Surface Mounted Technology; the lens group covers the heat sink, and is located above the LED chip; encapsulant is filled in a confined space formed between the lens group and the heat sink through a process of injection. Compared with the prior art, in the LED module of the present invention, the encapsulant replaces the original air medium in the transmission process of the light emitted by the LED chip; moreover, matching between the refractive index of the encapsulant and the lens of the lens group improves the light out-coupling efficiency. Lighting efficiency is improved by 10˜15% compared with the prior art.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 1, 2018
    Assignee: Hangzhou Hpwinner Opto Corporation
    Inventors: Kai Chen, Jianming Huang
  • Patent number: 9960324
    Abstract: A light-emitting device including a substrate, a first light-emitting diode disposed on the substrate, a molding member encapsulating the first light-emitting diode, and luminophores dispersed in the molding member and including a surface-modified luminophore, in which the surface-modified luminophore includes a fluorinated coating and a fluoride luminophore including a manganese activator. The fluoride luminophore is selected from the group consisting of K2SiF6, Na2SiF6, Rb2SiF6, K2GeF6, Na2GeF6, and Rb2GeF6.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: May 1, 2018
    Assignees: Seoul Semiconductor Co., Ltd., LITEC-LP GmbH
    Inventors: Chung Hoon Lee, Walter Tews, Gundula Roth, Detlef Starick
  • Patent number: 9960325
    Abstract: A semiconductor device and manufacturing method therefor, provided with the aims of constraining resin burr formation while having good electric connectivity and joining strength, and LED device, provided with the aim of improving adhesion between silicon resin and leads while having good luminescent characteristics. For these purposes, an organic film is formed through self-assembly by functional organic molecules at surface border regions of outer leads of a QFP. The functional organic molecules consist of a first functional group bonding with metals, a principal chain, and a second functional group inducing hardening in thermosetting resins. The principal chain consists of a glycol chain, or else of a glycol chain and one or more among methylene, fluoromethylene, or siloxane chains. The principal chain also preferably includes one or more among a hydroxyl radical, ketone, thioketone, primary amine, secondary amine, and aromatic compounds.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 1, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Takahiro Fukunaga, Yasuko Imanishi
  • Patent number: 9960326
    Abstract: A light emitting device includes a base substrate having a recessed portion at a flat upper surface thereof. The recessed portion has an inner wall. A sealing member is provided in the recessed portion. The sealing member contains surface-treated particles, or particles coexisting with a dispersing agent. The particles have a particle diameter of 1 nm or more and 100 ?m or less. The particles are made of an organic material or an inorganic material. The organic material and the inorganic material are free of a phosphor. The at least a part of an edge portion of the sealing member is a region located in the vicinity of an edge of the recessed portion which is a boundary between a surface of the inner wall and the flat upper surface. The at least one of the particles and aggregates of particles are unevenly distributed in the region.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 1, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Masafumi Kuramoto, Akiko Yamasaki, Hirofumi Ichikawa, Yasunori Shimizu, Akihiro Ota
  • Patent number: 9960327
    Abstract: Embodiments of the present disclosure provide a light emitting device and display equipment. The light emitting device, includes a light emitting diode (LED) and an optical lens, the optical lens including a light incident surface and a light emergent surface, the light incident surface including a free-form convex surface; wherein there is a first angle between a symmetry axis and the connecting line between the center point of the light emitting surface and any point on the light incident surface, and the curvature of the light incident surface decreases with the increase of the first angle; there is a second angle between a symmetry axis and the connecting line between the center point of the light emitting surface and any point on the light emergent surface, and the curvature of the light emergent surface increases with the increase of the second angle.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: May 1, 2018
    Assignees: Hisense Electric Co., Ltd., Hisense USA Corporation, Hisense International Co., Ltd.
    Inventors: Xiaoping Li, Fulin Li, Kun Shao
  • Patent number: 9960328
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that that comprises a transparent, translucent, non-opaque, or otherwise optically-transmissive, external surface.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 1, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: David Clark, Curtis Zwenger
  • Patent number: 9960329
    Abstract: Methods and apparatus are provided to improve long-term reliability of LED packages using reflective opaque die attach (DA) material. In one novel aspect, a protected area surrounding edges of the LED is determined. The DA is applied to the determined protected area by a dispense process, a stamping process, or a screen printing process, such that the effect of temperature degradation is reduced. A heat distribution model is used to determine the protected area, which is between edges of the LED and a predefined isothermal line where the temperature is 1/e that of the temperature at edges of the LED. In another embodiment, the protected area is further based on a spreading ratio of the substrate size to the LED size. In another novel aspect, with multiple LEDs in the LED package, the spreading ratio is further based on pitch distances to the immediate adjacent LEDs and the substrate boundary.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 1, 2018
    Assignee: Luminus, Inc.
    Inventors: Qifeng Shan, Hongtao Ma, Tao Tong
  • Patent number: 9960330
    Abstract: Application of a wavelength conversion element is substantially independent of the fabrication of a side-emitting light emitting device. In an example embodiment, the wavelength conversion element is situated around the periphery of a non-wavelength converting lightguide that is situated above the light emitting surface. One or more specular and/or diffusing reflectors are used to direct the light in the lightguide toward the wavelength conversion element at the periphery. In another embodiment, an interference filter may be used to provide predominantly side-emitted light at interfaces between the elements of the light emitting device.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: May 1, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Jianghong Yu, Nicolaas Joseph Martin Van Leth, Giovanni Cennini, Kenneth Vampola, Hugo Johan Comelissen
  • Patent number: 9960332
    Abstract: A light-emitting apparatus of the present invention has (i) a semiconductor device which emits light toward a higher position than a substrate and (ii) a plurality of external connection terminals, and includes: a light-reflecting layer, provided on the substrate, which reflects the light emitted by the semiconductor device; and a covering layer which covers at least the light-reflecting layer and which transmits the light reflected by the light-reflecting layer. Further, the semiconductor device is provided on the covering layer, and is electrically connected to the external connection terminals via connecting portions, and the semiconductor device and the connecting portions are sealed with a sealing resin so as to be covered. Therefore, the light-emitting apparatus has increased efficiency with which light is taken out, and can prevent a reflecting layer from being altered, deteriorating, and decreasing in reflectance.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 1, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Konishi, Masaki Kondo, Takaaki Horio, Takanobu Matsuo, Toshio Hata, Kiyohisa Ohta
  • Patent number: 9960333
    Abstract: A light-emitting device includes a substrate having a first surface extended in a first direction, a second surface opposite to the first surface, a third surface between the first and second surfaces and extended in the first direction, and a fourth surface opposite to the third surface, a conductive member including at least four element mounting portions arranged in the first direction on the first surface, a first wiring portion on the second surface, a second wiring portion on the third surface, and a third wiring portion on the fourth surface, and first, second, third, and fourth light-emitting elements respectively mounted on the four element mounting portions. With the first, second, and third wiring portions, the first and second light-emitting elements are connected in series, the third and fourth light-emitting elements are connected in series, and the first and third light-emitting elements are connected in parallel.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 1, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Tadaaki Ikeda, Takuya Nakabayashi
  • Patent number: 9960334
    Abstract: Disclosed is a thermoelectric material with excellent thermoelectric conversion performance. The thermoelectric material is expressed by Chemical Formula 1 below: CuxSe1-yXy??<Chemical Formula 1> where X is at least one element selected from the group consisting of F, Cl, Br and I, 2<x?2.6 and 0<y<1.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 1, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Kyung-Moon Ko, Tae-Hoon Kim, Cheol-Hee Park
  • Patent number: 9960335
    Abstract: Cracking in a thermoelectric element made of a filled-skutterudite-type alloy is suppressed. A p-type thermoelectric element includes: a p-type thermoelectric conversion layer made of an alloy having a filled-skutterudite structure containing antimony; a p-side first metal layer that contains titanium simple substances and iron simple substances, and is laminated on the p-type thermoelectric conversion layer; and a p-side second metal layer that contains titanium simple substances, and is laminated on the p-side first metal layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 1, 2018
    Assignee: SHOWA DENKO K.K.
    Inventors: Yasutaka Yoshida, Kenichiro Nakajima
  • Patent number: 9960336
    Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer that are connected in series while alternating between the p-type and the n-type thermoelectric elements. The integrated circuit may include first and second substrates each having formed thereon a plurality of thermoelectric legs of a respective type of thermoelectric material. The first and second thermoelectric substrates also may have respective conductors, each coupled to a base of an associated thermoelectric leg and forming a mounting pad for coupling to a thermoelectric leg of the counterpart substrate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 1, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Jane Cornett, Baoxing Chen, William Allan Lane, Patrick M. McGuinness, Helen Berney