Patents Issued in May 1, 2018
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Patent number: 9960236Abstract: Methods for forming body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a method comprises: forming a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each body contact, adjacent to the gate, has a width extending parallel to the y-axis that is less than the width of the body contact parallel to the y-axis at a distance on an x-axis from the gate.Type: GrantFiled: November 16, 2016Date of Patent: May 1, 2018Assignee: INTERSIL AMERICAS LLCInventors: Dev Alok Girdhar, Jeffrey Michael Johnston
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Patent number: 9960237Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.Type: GrantFiled: April 13, 2015Date of Patent: May 1, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
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Patent number: 9960238Abstract: Systems and methods for molecular sensing are described. Molecular sensors are described which are based on field-effect or bipolar junction transistors. These transistors have a nanopillar with a functionalized layer contacted to either the base or the gate electrode. The functional layer can bind molecules, which causes an electrical signal in the sensor.Type: GrantFiled: May 22, 2015Date of Patent: May 1, 2018Assignees: CALIFORNIA INSTITUTE OF TECHNOLOGY, SANOFIInventors: Aditya Rajagopal, Chieh-feng Chang, Oliver Plettenburg, Stefan Petry, Axel Scherer, Charles L. Tschirhart
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Patent number: 9960239Abstract: An electronic device is presented; the device comprises an electrode structure located in electrical contact with a semiconducting element. The electrode structure is configured with two or more groups of regions comprising regions of a first group having first charge injection properties and regions of a second group having second charge injection properties being lower than the first charge injection properties. The regions of the second group are configured to provide barrier for injection of charge carriers from regions of the first group into the semiconductor element to thereby allow tailoring of desired electronic properties of the device.Type: GrantFiled: December 7, 2014Date of Patent: May 1, 2018Assignee: Technion Research & Development Foundation LimitedInventors: Nir Tessler, Ariel Jaques Ben Sasson, Michael Greenman
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Patent number: 9960240Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.Type: GrantFiled: October 21, 2015Date of Patent: May 1, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
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Patent number: 9960241Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.Type: GrantFiled: January 6, 2016Date of Patent: May 1, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sangjine Park, Kee Sang Kwon, Jae-Jik Baek, Boun Yoon
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Patent number: 9960242Abstract: A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.Type: GrantFiled: March 24, 2017Date of Patent: May 1, 2018Assignee: Silicon Storage Technology, Inc.Inventor: Chunming Wang
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Patent number: 9960243Abstract: A semiconductor device includes a transistor cell with a stripe-shaped trench gate structure that extends from a first surface into a semiconductor body. A gate connector structure at a distance to the first surface is electrically connected to a gate electrode in the trench gate structure. A gate dielectric separates the gate electrode from the semiconductor body. First sections of the gate dielectric outside a vertical projection of the gate connector structure are thinner than second sections within the vertical projection of the gate connector structure.Type: GrantFiled: November 22, 2016Date of Patent: May 1, 2018Assignee: Infineon Technologies AGInventors: Thomas Aichinger, Wolfgang Bergner
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Patent number: 9960244Abstract: A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.Type: GrantFiled: August 25, 2017Date of Patent: May 1, 2018Assignee: Taiwan Semiconductor Co., Ltd.Inventors: Yi-Lung Tsai, Aryadeep Mrinal, Mohammad Amanullah, Po-Wen Yang, Shu-Siang Liang
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Patent number: 9960245Abstract: A transistor device including a semiconductor material layer, a gate layer, and an insulation layer between the gate layer and the semiconductor material layer is provided. The semiconductor material layer includes a first conductive portion, a second conductive portion, a channel portion between the first conductive portion and the second conductive portion, and a first protruding portion formed integrally. The channel portion has a first boundary adjacent to the first conductive portion, a second boundary adjacent to the second conductive portion, a third boundary, and a fourth boundary. The third boundary and the fourth boundary connect the terminals of the first boundary and the second boundary. The first protruding portion is protruded outwardly from the third boundary of the channel portion. The first gate boundary and the second gate boundary are overlapped with the first boundary and the second boundary of the channel portion.Type: GrantFiled: March 15, 2017Date of Patent: May 1, 2018Assignee: Industrial Technology Research InstituteInventors: Tai-Jui Wang, Tsu-Chiang Chang, Chieh-Wei Feng, Shao-An Yan, Wei-Han Chen
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Patent number: 9960246Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.Type: GrantFiled: December 5, 2016Date of Patent: May 1, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Lian, Chih-Lin Wang, Kang-Min Kuo, Chih-Wei Lin
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Patent number: 9960247Abstract: A method for fabricating a silicon carbide power device may include steps of: forming a first n-type silicon carbide layer on top of a second n-type silicon carbide layer; depositing a first metal layer on the first silicon carbide layer; patterning the first metal layer; depositing and patterning a dielectric layer onto at least a portion of the pattered first metal layer; and depositing and patterning a second metal layer to form a Schottky barrier. In one embodiment, the first metal layer is a high work function metal layer, which may include Silver, Aluminum, Chromium, Nickel and Gold. In another embodiment, the second metal layer is called a “Schottky metal” layer, which may include Platinum, Titanium and Nickel Silicide.Type: GrantFiled: January 19, 2017Date of Patent: May 1, 2018Inventors: Ruigang Li, Zheng Zuo, Bochao Huang, Da Teng
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Patent number: 9960248Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.Type: GrantFiled: June 7, 2017Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: Jagar Singh
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Patent number: 9960249Abstract: A method of substantially offsetting polarization charges in an electronic device having a heterobarrier comprising providing a substrate; providing at least one pair of stacks of semiconductor materials; one of the pair of stacks having one or more of spontaneous and piezoelectric polarity where the total polarization charge is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced and the pair of stacks operate to store electrical energy.Type: GrantFiled: July 17, 2015Date of Patent: May 1, 2018Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Pankaj B Shah
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Patent number: 9960250Abstract: Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.Type: GrantFiled: May 5, 2017Date of Patent: May 1, 2018Assignee: Semiconductor Components Industries LLCInventors: Kyu-hyun Lee, Young-chul Kim, Kyeong-seok Park, Bong-yong Lee, Young-chul Choi
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Patent number: 9960251Abstract: An ESD protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the ESD protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type. Wherein no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.Type: GrantFiled: August 19, 2015Date of Patent: May 1, 2018Assignee: NXP USA, Inc.Inventors: Jean Philippe Laine, Patrice Besse
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Patent number: 9960252Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.Type: GrantFiled: September 7, 2016Date of Patent: May 1, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
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Patent number: 9960253Abstract: A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor. The lightly doped region extends beneath and adjacent to a gate region of the chemical sensitive sensor. Modifying the gain of the chemically sensitive sensor is achieved by manipulating the lightly doped region under the electrodes.Type: GrantFiled: February 12, 2014Date of Patent: May 1, 2018Assignee: Life Technologies CorporationInventor: Keith G. Fife
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Patent number: 9960254Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).Type: GrantFiled: February 6, 2017Date of Patent: May 1, 2018Assignee: International Business Machines CorporationInventors: Raqiang Bao, Dechao Guo
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Patent number: 9960255Abstract: A method for manufacturing a thin film transistor is provided. The method comprises depositing sequentially a gate insulating layer and a gate metal layer on a semiconductor substrate; etching the gate metal layer uncovered by the first photoresist pattern; implementing a first ion implantation on the semiconductor substrate; etching a side wall of the first photoresist pattern; implementing a second ion implantation on the semiconductor substrate to form a source and a drain. The source and the drain include a heavily doped drain region and a lightly doped drain region.Type: GrantFiled: June 12, 2016Date of Patent: May 1, 2018Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Jiangbo Ye
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Patent number: 9960256Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.Type: GrantFiled: May 20, 2014Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Andy Chih-Hung Wei
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Patent number: 9960257Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.Type: GrantFiled: March 12, 2015Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
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Patent number: 9960258Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in Which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.Type: GrantFiled: July 11, 2016Date of Patent: May 1, 2018Assignee: Micron Technology, Inc.Inventor: Yongjun Jeff Hu
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Patent number: 9960259Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.Type: GrantFiled: January 19, 2015Date of Patent: May 1, 2018Assignee: HITACHI, LTD.Inventors: Naoki Tega, Naoki Watanabe, Shintaroh Sato
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Patent number: 9960260Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.Type: GrantFiled: August 7, 2013Date of Patent: May 1, 2018Assignee: Guang Zhou New Vision Opto-Electronic Technology Co., Ltd.Inventors: Miao Xu, Dongxiang Luo, Hongmeng Li, Jiawei Pang, Ying Guo, Lang Wang
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Patent number: 9960261Abstract: A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.Type: GrantFiled: May 26, 2017Date of Patent: May 1, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 9960262Abstract: A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.Type: GrantFiled: February 25, 2016Date of Patent: May 1, 2018Assignee: Raytheon CompanyInventors: Brian D. Schultz, Eduardo M. Chumbes
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Patent number: 9960263Abstract: A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.Type: GrantFiled: October 13, 2016Date of Patent: May 1, 2018Assignee: Mitsubishi Electric CorporationInventor: Takahiro Nakamoto
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Patent number: 9960264Abstract: A high electron mobility transistor includes a first III-V compound layer, a second III-V compound layer, a source electrode, a drain electrode, a gate electrode, a first moat, and a second moat. The second III-V compound layer is disposed on the first III-V compound layer. The source electrode and the drain electrodes are disposed above the first III-V compound layer. The gate electrode is disposed above the second III-V compound layer located between the source and the drain electrodes in a first direction. The second III-V compound layer includes a first region under the gate electrode. The first moat is at least partially disposed between the first region and the source electrode in the first direction. The second moat is at least partially disposed between the first region and the drain electrode in the first direction.Type: GrantFiled: May 31, 2017Date of Patent: May 1, 2018Assignee: Wavetek Microelectronics CorporationInventors: Chih-Yen Chen, Hsien-Lung Yang
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Patent number: 9960265Abstract: In one embodiment, a III-V high electron mobility semiconductor device includes a semiconductor substrate including a GaN layer, an AlGaN layer on the GaN layer wherein a 2 DEG is formed near an interface of the GaN layer and the AlGaN layer. An insulator may be on at least a first portion of the AlGaN layer and a P-type GaN gate region may be overlying a second portion of the AlGaN layer wherein the 2 DEG does not underlie the P-type GaN gate region.Type: GrantFiled: February 2, 2017Date of Patent: May 1, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Abhishek Banerjee, Peter Moens, Gordon M. Grivna
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Patent number: 9960266Abstract: Passivated AlGaN/GaN HEMTs having no plasma damage to the AlGaN surface and methods for making the same. In a first embodiment, a thin HF SiN barrier layer is deposited on the AlGaN surface after formation of the gate. A thick HF/LF SiN layer is then deposited, the thin HF SiN layer and the thick HF/LF Sin layer comprising bi-layer SiN passivation on the HEMT. In a second embodiment, a first thin HF SiN barrier layer is deposited on the AlGaN surface before formation of the gate and is annealed. Following annealing of the first SiN layer, the gate is formed, and a second HF SiN barrier layer is deposited, followed by a thick HF/LF SiN layer, the three SiN layers comprising tri-layer SiN passivation on the HEMT.Type: GrantFiled: May 11, 2017Date of Patent: May 1, 2018Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Marko J. Tadjer, Andrew D. Koehler, Travis J. Anderson, Karl D. Hobart
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Patent number: 9960267Abstract: In a semiconductor device provided with a MOSFET part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer and a drift layer, the gate pad part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure where a p-type diffusion region electrically connected with the a source electrode layer and a p-type impurity non-diffusion region are alternately formed on a surface of the drift layer.Type: GrantFiled: March 31, 2014Date of Patent: May 1, 2018Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventor: Nobuki Miyakoshi
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Patent number: 9960268Abstract: A semiconductor device includes a drift region of a device structure arranged in a semiconductor layer. The drift region includes at least one first drift region portion and at least one second drift region portion. A majority of dopants within the first drift region portion are a first species of dopants having a diffusivity less than a diffusivity of phosphor within the semiconductor layer. Further, a majority of dopants within the second drift region portion are a second species of dopants. Additionally, the semiconductor device includes a trench extending from a surface of the semiconductor layer into the semiconductor layer. A vertical distance of a border between the first drift region portion and the second drift region portion to the surface of the semiconductor layer is larger than 0.5 times a maximal depth of the trench and less than 1.5 times the maximal depth of the trench.Type: GrantFiled: October 7, 2016Date of Patent: May 1, 2018Assignee: Infineon Technologies AGInventors: Markus Zundel, Christian Kampen, Jacob Tillmann Ludwig
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Patent number: 9960269Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, and a gate electrode. The semiconductor substrate has a trench in the main surface. The gate electrode is formed in the trench. A distribution of an impurity concentration in the base region has a plurality of peak values along a direction of depth from the main surface toward the back surface, and the number of peak values is four or more.Type: GrantFiled: February 1, 2017Date of Patent: May 1, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Yanagigawa, Hiroyoshi Kudou
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Patent number: 9960270Abstract: A method for manufacturing a semiconductor device includes: forming a recess in a semiconductor substrate, the recess having a bottom and a sidewall extending from the bottom to a first side of the semiconductor substrate; forming an auxiliary structure on the sidewall and the bottom of the recess and forming a hollow space within the recess; filling the hollow space with a filling material; forming a plug on the first side of the semiconductor substrate to cover the auxiliary structure at least on the sidewall of the recess; forming an opening in the plug to partially expose the auxiliary structure in the recess; removing the auxiliary structure at least partially from the sidewall of the recess to form cavities between the auxiliary structure and the sidewall; and sealing the opening in the plug.Type: GrantFiled: May 12, 2017Date of Patent: May 1, 2018Assignee: Infineon Technologies Austria AGInventor: Oliver Blank
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Patent number: 9960271Abstract: An integrated circuit and method are disclosed. In the method, a stack of sacrificial layers is formed on a semiconductor layer such that a first portion of the stack has an extra sacrificial layer as compared to a second portion. First and second multi-layer fins are etched through the first and second portions and into the semiconductor layer. First and second vertical field effect transistors (VFETs) are formed using the fins. During VFET formation, multiple etch processes are performed to remove the sacrificial layers. The last of these etch processes is a selective isotropic etch process that removes the extra sacrificial layer and etches back first and second upper dielectric spacers on the first and second multi-layer fins. Due to the extra sacrificial layer, the first upper dielectric spacer will be taller than the second and the first VFET will have a higher threshold voltage than the second.Type: GrantFiled: April 18, 2017Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Chun-chen Yeh, Tenko Yamashita, Kangguo Cheng
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Patent number: 9960272Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.Type: GrantFiled: May 16, 2017Date of Patent: May 1, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, ChoongHyun Lee, Shogo Mochizuki, Hemanth Jagannathan
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Patent number: 9960273Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having a first region and a second region; a first fin feature formed on the substrate within the first region; and a second fin feature formed on the substrate within the second region. The first fin feature includes a first semiconductor feature of a first semiconductor material formed on a dielectric feature that is an oxide of a second semiconductor material. The second fin feature includes a second semiconductor feature of the first semiconductor material formed on a third semiconductor feature of the second semiconductor material.Type: GrantFiled: November 16, 2015Date of Patent: May 1, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chung-Cheng Wu, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
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Patent number: 9960274Abstract: FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.Type: GrantFiled: September 27, 2016Date of Patent: May 1, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hao-Yu Chen, Chang-Yun Chang, Cheng-Chuan Huang, Fu-Liang Yang
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Patent number: 9960275Abstract: Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.Type: GrantFiled: April 18, 2017Date of Patent: May 1, 2018Assignee: Applied Materials, Inc.Inventors: Chih-Yang Chang, Raymond Hoiman Hung, Tatsuya E. Sato, Nam Sung Kim, Shiyu Sun, Bingxi Sun Wood
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Patent number: 9960276Abstract: The present invention provides an ESL TFT substrate structure and a manufacturing method thereof. In the ESL TFT substrate structure, an etch stop layer (5) includes a first via (51) and a second via (52) formed therein to correspond to two side portions of an oxide semiconductor layer (4). A drain terminal (6) is set in engagement with the oxide semiconductor layer (4) through the first via (51). A passivation protection layer (7) includes a through hole (72) formed therein to extend to and communicate with the second via (52). An electrode layer (8) is formed on the passivation protection layer (7) and has a side portion that is adjacent to the drain terminal (6) and is set in engagement with the oxide semiconductor layer (4) through the through hole (72) and the second via (52) to form a source terminal (81) and an opposite side portion that is extended in a direction away from the drain terminal (6) to form a pixel electrode (82).Type: GrantFiled: June 23, 2015Date of Patent: May 1, 2018Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Wenhui Li
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Patent number: 9960277Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.Type: GrantFiled: November 28, 2017Date of Patent: May 1, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9960278Abstract: To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed. In addition, when the aluminum oxide film is formed, entry and diffusion of water or hydrogen into the oxide semiconductor layer from the air due to heat treatment in a manufacturing process of a semiconductor device or an electronic appliance including the transistor can be prevented.Type: GrantFiled: April 2, 2012Date of Patent: May 1, 2018Inventors: Yuhei Sato, Keiji Sato, Toshinari Sasaki, Tetsunori Maruyama, Atsuo Isobe, Tsutomu Murakawa, Sachiaki Tezuka
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Patent number: 9960279Abstract: Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved. One embodiment of the present invention is a semiconductor device which includes a base insulating film; an oxide semiconductor film formed over the base insulating film; a gate insulating film formed over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film provided therebetween. The base insulating film shows a signal at a g value of 2.01 by electron spin resonance. The oxide semiconductor film does not show a signal at a g value of 1.93 by electron spin resonance.Type: GrantFiled: December 4, 2014Date of Patent: May 1, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Kosei Noda, Yuhei Sato, Yuta Endo
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Patent number: 9960280Abstract: A transistor with stable electric characteristics is provided. An aluminum oxide film containing boron is formed in order to prevent hydrogen from diffusing into an oxide semiconductor film.Type: GrantFiled: December 18, 2014Date of Patent: May 1, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuichi Sato, Naoto Yamade
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Patent number: 9960281Abstract: Thin film transistors are provided that include a metal oxide active layer with source and drain regions having a reduced resistivity relative to the metal oxide based on doping of the source and drain regions at room temperature. In an aspect, a transistor structure is provided, that includes a substrate, and source and drain regions within a doped active layer having resulted from doping of an active layer comprising metal-oxide and formed on the substrate, wherein the doped active layer was doped at room temperature and without thermal annealing, thereby resulting in a reduction of a resistivity of the source and drain regions of the doped active layer relative to the active layer prior to the doping. In an aspect, the source and drain regions have a resistivity of about 10.0 m?·cm after being doped with stable ions and without subsequent activation of the ions via annealing.Type: GrantFiled: February 9, 2015Date of Patent: May 1, 2018Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Lei Lu, Man Wong, Hoi Sing Kwok
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Patent number: 9960282Abstract: A method for manufacturing a semiconductor device is discussed. The method includes forming a gate electrode on a substrate, forming a gate insulating film over the substrate, depositing an In—Ga—Zn oxide over the gate insulating film while heating the substrate to a temperature of 200 to 300° C., an atomic percent ratio of Zn in the In—Ga—Zn oxide as-deposited being higher than that of In or Ga, heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an active layer crystallized throughout an entire thickness of the active layer, and forming a source electrode and a drain electrode.Type: GrantFiled: July 6, 2017Date of Patent: May 1, 2018Assignee: LG DISPLAY CO., LTD.Inventors: Min-Cheol Kim, Youn-Gyoung Chang, Kwon-Shik Park, So-Hyung Lee, Ho-Young Jung, Ha-Jin Yoo, Jeong-Suk Yang
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Patent number: 9960283Abstract: Disclosed is a thin-film transistor. The thin-film transistor includes: a substrate; a first gate, a first gate insulation layer, a semiconductor layer, an etching stop layer, and the second gate stacked on a surface of the substrate, in which the semiconductor layer has a thickness of 200 nm-2000 nm; the etching stop layer includes a first via and a second via formed therein; and the first via and the second via are arranged to each correspond to the semiconductor layer; and a source and a drain respectively extending through the first via and the second via to connect to the semiconductor layer. The thin-film transistor has an increased ON-state current and switching speed.Type: GrantFiled: December 22, 2014Date of Patent: May 1, 2018Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventors: Longqiang Shi, Zhiyuan Zeng, Hejing Zhang, Yutong Hu
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Patent number: 9960284Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.Type: GrantFiled: October 30, 2015Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Patent number: 9960285Abstract: One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.Type: GrantFiled: October 24, 2012Date of Patent: May 1, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chung-Yen Chou, Po-ken Lin, Shih-Chang Liu, Chia-Shiung Tsai