Patents Issued in May 1, 2018
  • Patent number: 9960186
    Abstract: Disclosed are a back cover and a transparent display apparatus including the same, in which a chip groove, into which a chip included in a chip-on film coupled to a transparent panel is inserted, is disposed in a rear surface. The transparent display apparatus includes a transparent panel and a back cover. The transparent panel may display an image. The back cover may be transparent, and the transparent panel may be disposed on a front of the back cover. A chip groove into which a chip included in a chip-on film coupled to the transparent panel is inserted may be disposed in a rear surface of the back cover.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 1, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Jong Moo Kim, Jin-Hyun Jung
  • Patent number: 9960187
    Abstract: An electrical connection structure providing better optical properties in a display includes an electrical connection unit, an interference layer, and an electrically insulating cover. The interference layer is positioned on a side of the electrical connection unit. The electrically insulating cover is positioned on the other side of the electrical connection unit and formed to cover the electrical connection unit. The electrical connection unit includes a metal layer to reflect light. The interference layer can reflect light falling on a first region close to the electrically insulating cover. A degree of reflectance of the first region of the interference layer is equal to the reflectance of the metal layer.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: May 1, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chin-Yueh Liao, Chia-Lin Liu, Yan-Tang Dai, Hung-Che Lu
  • Patent number: 9960188
    Abstract: A thin film transistor comprises a source over a substrate; a first insulation layer having a source contact through-hole corresponding to a position of the source over the source; an active layer electrically connecting with the source through the source contact through-hole over the etching stop layer; a second insulation layer having a drain contact through-hole exposing a portion of the active layer over the active layer; and a drain electrically connecting with the active layer through the drain contact through-hole over the second insulation layer.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 1, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Li Zhang
  • Patent number: 9960189
    Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method includes forming a gate electrode, a gate insulating layer, a metal oxide semiconductor (MOS) active layer, a source electrode and a drain electrode on a substrate. The MOS active layer includes forming a pattern layer of indium oxide series binary metal oxide including a first pattern directly contacting with the source electrode and the drain electrode. An insulating layer formed over the source electrode and the drain electrode acts as a protection layer, the pattern layer of indium oxide series binary metal oxide is implanted with metal doping ions by using an ion implanting process, and is annealed, so that the indium oxide series binary metal oxide of the third pattern is converted into the indium oxide series multiple metal oxide to form the MOS active layer.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 1, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ce Zhao, Chunsheng Jiang, Guangcai Yuan
  • Patent number: 9960190
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Shinpei Matsuda, Haruyuki Baba, Ryunosuke Honda
  • Patent number: 9960191
    Abstract: A display device includes a plurality of gate lines extending in a first direction on the display area, a plurality of source lines extending in a second direction, a plurality of lead-out lines extending in the second direction and for transmitting gate signals to the plurality of gate lines. A plurality of connecting portions each electrically connects one gate line to one lead-out line. The plurality of connecting portions pass through a first insulating layer at a plurality of jointing points which are selected among a plurality of overlapping points where the plurality of lead-out lines and the plurality of gate lines overlap in a plane area.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 1, 2018
    Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventors: Tetsuya Kawamura, Tetsurou Izawa
  • Patent number: 9960192
    Abstract: A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures in respective pixels on the adhesion layer. Each of the pixel structures on the adhesion layer includes a light emitting diode including an inorganic light emitting layer, and a thin film transistor which is connected to the light emitting diode and switches a state of the light emitting diode.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 1, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Kihyun Kim, Taewoong Kim, Jong-hyun Ahn, Wonho Lee, Minwoo Choi
  • Patent number: 9960193
    Abstract: A display driver integrated circuit and a method of manufacturing the same are provided. The method of manufacturing a display driver integrated circuit (DDI) including a first area, a second area, and an overlapping area in which the first area and the second area overlap each other includes forming a first pattern in the first area using a first reticle; and forming a second pattern in the second area using a second reticle, and ends of the first pattern and the second pattern are connected within the overlapping area and the first area and the second area are asymmetrically set based on the overlapping area such that the overlapping area includes only a metal line.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Park, Siwoo Kim
  • Patent number: 9960194
    Abstract: Disclosed is a display device including a data distribution circuit with enhanced electrical characteristic. The display device includes a plurality of demultiplexing circuits including a gap area which is provided between two transistors, which are adjacent to each other along a first horizontal axis direction, of first to nth transistors and provided in a non-rectilinear shape along a second horizontal axis direction. Here, the gap area may have a zigzag shape along the second horizontal axis direction.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: May 1, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: DongHyun Park, YoungSeop Lee, SeongWook Choi
  • Patent number: 9960195
    Abstract: The present invention provides method for manufacturing a TFT backplane and a structure of a TFT backplane.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 1, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Wenhui Li, Yifan Wang, Chihyu Su, Xiaowen Lv
  • Patent number: 9960196
    Abstract: An array substrate includes a gate line, a common electrode line, a common electrode and a pixel electrode arranged on a base substrate. The common electrode is electrically connected to the common electrode line through a common electrode via-hole, and the common electrode includes a hollowed-out portion and a reserved portion at a region corresponding to the common electrode via-hole. The reserved portion is arranged between the gate line adjacent to the common electrode line and the pixel electrode adjacent to the common electrode line, and electrically connected to the common electrode line through the common electrode via-hole. The reserved portion does not overlap the gate line or the pixel electrode. The hollowed-out portion is at least arranged at a side of the reserved portion adjacent to the gate line and/or pixel electrode and between the reserved portion and the gate line and/or the pixel electrode.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 1, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Zhang, Jiapeng Li, Jing Zhang, Lei Chen, Dongjiang Sun
  • Patent number: 9960197
    Abstract: Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 1, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Weng-Jin Wu
  • Patent number: 9960198
    Abstract: The present technology relates to solid-state image sensor and an imaging system which are capable of providing a solid-state image sensor and an imaging system which are capable of realizing a spectroscopic/imaging device for visible/near-infrared light having a high sensitivity and high wavelength resolution, and of achieving two-dimensional spectrum mapping with high spatial resolution.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 1, 2018
    Assignee: SONY CORPORATION
    Inventor: Sozo Yokogawa
  • Patent number: 9960199
    Abstract: An optical sensor device may include a set of optical sensors. The optical sensor device may include a substrate. The optical sensor device may include a multispectral filter array disposed on the substrate. The multispectral filter array may include a first dielectric mirror disposed on the substrate. The multispectral filter array may include a spacer disposed on the first dielectric mirror. The spacer may include a set of layers. The multispectral filter array may include a second dielectric mirror disposed on the spacer. The second dielectric mirror may be aligned with two or more sensor elements of a set of sensor elements.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 1, 2018
    Assignee: VIAVI Solutions Inc.
    Inventor: Georg J. Ockenfuss
  • Patent number: 9960200
    Abstract: The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Chih-Hui Huang
  • Patent number: 9960201
    Abstract: A pixel of an image sensor includes a well below a gate and containing a dopant at a first concentration, a shallow trench isolation (STI) configured to electrically isolate the well, and a channel stop adjacent to at least one border between the well and the STI and containing a dopant at a second concentration higher than the first concentration.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Ho Lee, Seung Joo Nah, Young Sun Oh, Dong Young Jang
  • Patent number: 9960202
    Abstract: Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: May 1, 2018
    Assignee: Sony Corporation
    Inventors: Rena Suzuki, Hiroki Tojinbara, Ryoto Yoshita, Yoichi Ueda
  • Patent number: 9960203
    Abstract: The present disclosure relates to a radiation sensor. In one implementation, the sensor may include a radiation detector array having a plurality of pixels; at least two readout connectors having a plurality of contacts, each readout connector being configured for receiving a readout module; a routing circuit having conductors configured for routing electrical signals from each of the plurality of pixels to a corresponding contact of one of the readout connectors. The plurality of pixels is grouped in two or more groups of pixels, at least two pixels of a first group of pixels being separated by at least one pixel from another group of pixels. The routing circuit is configured for leading pixels of the first group of pixels to a first readout connector, and pixels from the other group of pixels to a second readout connector.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 1, 2018
    Assignee: Ion Beam Applications S.A.
    Inventors: David Menichelli, Michele Togno, Friedrich Friedl
  • Patent number: 9960204
    Abstract: A method and apparatus for integrating individual III-V MMICs into a micromachined waveguide package is disclosed. MMICs are screened prior to integration, allowing only known-good die to be integrated, leading to increased yield. The method and apparatus are used to implement a micro-integrated Focal Plane Array (mFPA) technology used for sub millimeter wave (SMMW) cameras, although many other applications are possible. MMICs of different technologies may be integrated into the same micromachined package thus achieving the same level of technology integration as in multi-wafer WLP integration.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: May 1, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Chunbo Zhang, Peter Ngo, Gershon Akerling, Kevin M. Leong, Patty Chang-Chien, Kelly J. Hennig, William R. Deal
  • Patent number: 9960205
    Abstract: An optoelectronic device including a semiconductor substrate including first and second opposing faces, a first set of first light-emitting diodes resting on a first portion of the substrate and including conical or frustoconical wire-like semiconductor elements, a first electrode covering each first light-emitting diode, a first conductive portion insulated from the substrate, extending through the substrate and connected to the first electrode; a second set of second light-emitting diodes resting on a second portion of the substrate and including conical or frustoconical wire-like semiconductor elements, a second electrode covering each second light-emitting diode, a second conductive portion insulated from the substrate and connected to the second electrode, and a first conductive element connecting the first conductive portion to the second portion of the substrate on the side of the second face.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 1, 2018
    Assignee: Aledia
    Inventors: Christophe Bouvier, Erwan Dornel
  • Patent number: 9960206
    Abstract: A light-emitting element wafer includes a supporting substrate, a luminescent layer that is formed of a semiconductor and has a first surface and a second surface, the first surface including a first electrode, the second surface including a second electrode, the second surface being arranged between the supporting substrate and the first surface, a junction layer that joins luminescent layer to the supporting substrate and is arranged between the supporting substrate and the second surface, a first inorganic film formed on the first surface, a second inorganic film formed between the junction layer and the second surface, an isolation trench portion that isolates elements and is formed to have a depth such that the isolation trench portion extends from the first inorganic film to the supporting substrate, and a third inorganic film that connects the first inorganic film and the second inorganic film.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 1, 2018
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Daisuke Saito, Hiroki Naito, Takahiro Koyama, Sayaka Aoki, Arata Kobayashi
  • Patent number: 9960207
    Abstract: Structures including a spin torque transfer magnetic tunnel junction (MTJ) stack and methods for fabricating same. A first contact is coupled with a first portion of a free layer of the MTJ stack, and a second contact is coupled with a second portion of the free layer of the MTJ stack. The free layer is laterally arranged between the first contact and the second contact.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Sunit S. Mahajan
  • Patent number: 9960208
    Abstract: An OLED display panel includes: two substrates opposite to each other; a plurality of pixel regions disposed between inner sides of the two substrates and each comprising a blue sub-pixel sub-region, a green sub-pixel sub-region and a red sub-pixel sub-region; and a circularly polarizing plate disposed at an outer side of one of the substrates on a light outgoing side of the display panel; wherein, an opening zone is within a projection area where a projection of each of the pixel regions on the circularly polarizing plate in a thickness direction of the display panel is located, and through the opening zone the corresponding sub-pixel sub-regions are exposed. A method for manufacturing an OLED display panel and a display apparatus having the OLED display panel are also disclosed.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: May 1, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chung-Chun Lee
  • Patent number: 9960209
    Abstract: An OLED display includes pixels, each including a first light emission region having a first area and a first perimeter and a second light emission region disposed neighboring the first light emission region and having a second area and a second perimeter. The first area, the first perimeter, the second area, and the second perimeter respectively satisfy an equation of A1*P2=A2*P1, where A1 is the first area, P1 is the first perimeter, A2 is the second area, and P2 is the second perimeter.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Won-Kyu Kwak, Ji-Eun Lee
  • Patent number: 9960210
    Abstract: The present invention discloses a structure of pixel arrangement and a display device. The structure of pixel arrangement includes a first sub-pixel, and second sub-pixels and third sub-pixels that are provided surrounding the first sub-pixel, the first sub-pixel, portions of the second sub-pixels and portions of the third sub-pixels constituting a virtual rhombus, wherein a center of the first sub-pixel coincides with a center of the virtual rhombus; a center of the second sub-pixel coincides with a first vertex of the virtual rhombus; and a center of the third sub-pixel coincides with a second vertex of the virtual rhombus. Compared with the prior art, the number of sub-pixels required to achieve high resolution display in the present invention is smaller, so that the number of the sub-pixels is decreased.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 1, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lujiang Huangfu, Xiaodan Jin, Yinan Liang
  • Patent number: 9960211
    Abstract: A pixel element structure is disclosed. The pixel element structure includes first, second, and third sub-pixel elements, each including a light-emitting region. At least one of the first, second, and third sub-pixel elements includes a light-transmitting region, where the light-emitting region includes an organic light-emitting diode light-emitting structure, and where the organic light-emitting diode light-emitting structure includes a first substrate, and a nontransparent anode, a pixel defining layer, an organic layer and a cathode, sequentially arranged above the first substrate.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: May 1, 2018
    Assignees: SHANGHAI TIANMA AM-OLED CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Boyan Lv, Liyuan Luo, Dong Qian
  • Patent number: 9960212
    Abstract: An organic light-emitting diode (OLED) display panel includes: an OLED layer; a color filter layer; and a color coordinate tuning layer disposed between the OLED layer and the color filter layer, wherein the OLED layer includes a first light-emitting portion comprising a first light-emitting layer configured to emit a first light and a second light-emitting portion comprising a second light-emitting layer configured to emit a second light. The OLED layer is configured to emit a third light produced by mixing the first light and the second light. The color coordinate tuning layer is configured to output a fourth light different from the third light. The number of all of peaks and shoulders that an EL spectrum of the fourth light has is higher than the number of all of peaks and shoulders that an EL spectrum of the third light has throughout an entire range of a visible wavelength band.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 1, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Moonbae Gee, Hansun Park, Dongwoo Song, Soohyun Kim
  • Patent number: 9960213
    Abstract: A flexible input and output device in which defects due to a crack is reduced. The input and output device includes a first flexible substrate, a second flexible substrate, a first buffer layer, a first crack inhibiting layer, an input device, and a light-emitting element. A first surface of the first flexible substrate faces a second surface of the second flexible substrate. The first buffer layer, the first crack inhibiting layer, and the input device are provided on the first surface side of the first flexible substrate. The first buffer layer includes a region overlapping with the first crack inhibiting layer. The first buffer layer is between the first crack inhibiting layer and the first surface. The input device includes a transistor and a sensor element. The light-emitting element is provided on the second surface side of the second flexible substrate.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoyuki Senda, Masataka Nakada, Takayuki Abe, Koji Kusunoki, Hideaki Shishido
  • Patent number: 9960214
    Abstract: The present invention discloses an OLED display panel, comprising a substrate; a photochromic layer, being formed on the substrate, and comprising photochromic material which changes from transparent to opaque under excitation of light; a transparent anode, formed at one side of the photochromic layer away from the substrate; an emission layer, formed at one side of the transparent anode away from the photochromic layer, and employed to emit light, and the light comprises a wavelength employed to excite the photochromic material; and a semitransparent cathode, formed at one side of the emission layer away from the transparent anode, and employed to pass a portion of the light and reflect the other portion of the light. The OLED display panel of the present invention has the longer micro cavity total optical distance. The present invention further discloses a manufacture method of an OLED display panel.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: May 1, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Youyuan Kuang
  • Patent number: 9960215
    Abstract: An organic electroluminescent display device is provided. The display device has a polarizing film disposed at a light exiting side thereof. The polarizing film has a plurality of polarization units, and adjacent polarization units have different polarization directions.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 1, 2018
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventor: Changdi Chen
  • Patent number: 9960216
    Abstract: An organic light emitting display apparatus includes a substrate; an anode electrode on the substrate; an auxiliary electrode on the substrate; an organic emission layer on the anode electrode; a cathode electrode on the organic emission layer and on the auxiliary electrode; an insulating bank on the auxiliary electrode, the bank overlapping a first portion of the auxiliary electrode and exposing a second portion of the auxiliary electrode; a first partition wall on the auxiliary electrode; a second partition wall on the first partition wall and covering the exposed second portion of the auxiliary electrode in plan view. A separation space is between the second partition wall and the bank, the cathode electrode is electrically connected to the auxiliary electrode through the separation space between the second partition wall and the bank, and the second partition wall is supported by the first partition wall and the bank.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 1, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Joonsuk Lee, Se June Kim
  • Patent number: 9960217
    Abstract: A display panel is provided. The display panel includes a substrate having a pixel region and a peripheral region, a control element overlying the pixel region of the substrate, a first metal layer overlying the substrate in the peripheral region and in the pixel region, a first insulating layer formed on the first metal layer in the peripheral region, wherein the first insulating layer includes at least an opening, and the opening is disposed on the first metal layer, a second metal layer overlying the first insulating layer and electrically connected to the first metal layer, wherein a portion of the second metal layer is disposed in the opening, a second insulating layer overlying the second metal layer, and an electrode layer disposed on the second insulating layer.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 1, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Tsung-Yi Su, Yu-Hung Dai, Chang-Ho Tseng
  • Patent number: 9960218
    Abstract: An organic light-emitting display substrate, a manufacturing method therefor, and an organic light-emitting display device. The organic light-emitting display substrate comprises a base substrate and multiple sub-pixels that are located on the base substrate and that are arranged in an array manner. Each sub-pixel comprises an organic light-emitting layer. At least one blocking element is disposed between two adjacent sub-pixels that emit light of different colors.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 1, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Dongfang Yang
  • Patent number: 9960219
    Abstract: An organic light emitting display device includes a substrate; an anode electrode on the substrate; an auxiliary electrode on the substrate in a same layer as the anode electrode; a partition supporter on the auxiliary electrode; a partition on the partition supporter; an organic emitting layer on the anode electrode and on the partition such that portions separated on the partition are separated from other portions; and a cathode electrode connected with the organic emitting layer and the auxiliary electrode. A lower surface of the partition supporter includes a pair of short sides; and a pair of long sides connecting the pair of short sides and including at least one inclined surface.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 1, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: JaeSung Lee, Jonghyeok Im
  • Patent number: 9960220
    Abstract: An organic light emitting diode (OLED) display, including a flexible substrate bent in a first direction, an OLED arranged on the flexible substrate, a first thin film transistor connected to the OLED and including a first channel area extending in a second direction crossing the first direction, and one or more additional thin film transistors connected to the first thin film transistor and including corresponding additional channel areas extending in the second direction.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: May 1, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Woong Kim, Hyun-Woo Koo, Young-Gug Seol, Young-Ki Hong, Won-Kyu Kwak, Yang-Wan Kim, Han-Sung Bae
  • Patent number: 9960221
    Abstract: An organic light emitting diode display includes: a substrate; a scan line formed over the substrate and transmitting a scan signal; a data line crossing the scan line and transmitting a data voltage; a driving voltage line crossing the scan line and transmitting a driving voltage; a switching transistor connected to the scan line and the data line; a driving transistor connected to the switching transistor; a driving connection member connected to a driving gate electrode of the driving transistor; a storage capacitor including a first storage electrode and a second storage electrode; a pixel electrode electrically connected to the driving transistor; and a contact hole connecting the first storage electrode and the driving connection member. the second storage electrode may include a cut-out by a curved edge at least partially surrounding the contact hole, and the pixel electrode may be formed not to overlap the cut-out.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: May 1, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae Uk Kim
  • Patent number: 9960222
    Abstract: The present disclosure provides an organic light-emitting diode (OLED) array substrate. The OLED array substrate includes a display area with OLEDs arranged in arrays, electrostatic discharge lines, and peripheral electrostatic discharge areas with conductive areas electrically connected to a cathode of the OLEDs and electrically connected to the electrostatic discharge lines through switch modules.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 1, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Cuili Gai, Zhongyuan Wu, Longyan Wang, Xingdong Liu
  • Patent number: 9960223
    Abstract: An active-matrix display device according to the present disclosure includes a plurality of pixels. Each of the pixels includes: a drive transistor disposed on a substrate; and an organic EL element that is caused by the drive transistor to emit light and includes an AM layer disposed above the substrate and a transparent electrode layer disposed above the AM layer. The active-matrix display device further includes: a source line that supplies data to the pixels; and a power supply line that supplies electric power to the pixels. The power supply line is shared by, among the plurality of pixels, two pixels that are adjacent to each other in a second direction that crosses a first direction in which the power supply line is extended. The source line and the AM layer are disposed not to overlap each other in a plan view of the substrate.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: May 1, 2018
    Assignee: JOLED INC.
    Inventors: Kohei Ebisuno, Masafumi Matsui, Hitoshi Tsuge
  • Patent number: 9960224
    Abstract: A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Han Kung Chua, Min Suet Lim, Hoay Tien Teoh
  • Patent number: 9960225
    Abstract: It is an object to improve performance of a power storage device, such as cycle characteristics. A power storage device includes a current collector and a crystalline semiconductor layer including a whisker, which is formed on and in close contact with the current collector. Separation of the crystalline semiconductor layer is suppressed by an increase of adhesion, whereby cycle characteristics in which a specific capacity of a tenth cycle number with respect to a first cycle number is greater than or equal to 90% is realized. In addition, cycle characteristics in which a specific capacity of a hundredth cycle number with respect to a first cycle number is greater than or equal to 70% is realized.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazutaka Kuriki, Michiko Konishi, Asami Tadokoro, Yasunori Yoshida, Kiyofumi Ogino, Toshihiko Takeuchi
  • Patent number: 9960226
    Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9960227
    Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 1, 2018
    Assignee: XILINX, INC.
    Inventors: Michael J. Hart, James Karp
  • Patent number: 9960228
    Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 1, 2018
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Maeyama, Shunichi Nakamura, Atsushi Ogasawara, Ryohei Osawa, Akihiko Shibukawa
  • Patent number: 9960229
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Christian Eckl
  • Patent number: 9960230
    Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
  • Patent number: 9960231
    Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Hyeokjin Bruce Lim, Satyanarayana Sahu, Venugopal Boynapalli
  • Patent number: 9960232
    Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Borna Obradovic, Titash Rakshit, Mark Rodder
  • Patent number: 9960233
    Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan, Jeffrey W. Sleight
  • Patent number: 9960234
    Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: May 1, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kirk Huang, Chun-Li Liu, Ali Salih
  • Patent number: 9960235
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a plurality of base regions of a second conductivity type formed on a first principal surface of the semiconductor substrate via a semiconductor layer of the first conductivity type, and a plurality of source regions of the first conductivity type formed in the base regions. Each base region, in a top-down view from an angle perpendicular to the first principle surface, is of a polygonal shape. Each adjacent two of the base regions in the top-down view have two sides, one from each of the two base regions, that face each other across a portion of the semiconductor layer, the source region being formed at only one of the two sides.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 1, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Hoshi, Yuichi Harada, Akimasa Kinoshita, Yasuhiko Oonishi