Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

Abstract: A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.

Abstract: Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c?0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles.

Abstract: To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive layer; a second insulating adhesive layer; and a conductive particle-containing layer sandwiched by the first insulating adhesive layer and the second insulating adhesive layer and having conductive particles contained in an insulating adhesive, wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, and, the conductive particle-containing layer, a portion thereof below the conductive particles and in contact with the second insulating adhesive layer has a lower degree of cure than other portions thereof.

Abstract: The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers (6, 8) including metal nanoparticles to sandwich metal foil (7) so as to form a joining layer and joining the same type or different types of surface metals (3-4) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.

Abstract: A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

Abstract: A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a diffusion barrier layer that includes sidewall portions, and a metallic material encircled by the sidewall portions of the diffusion barrier layer. The metallic material has a second planar surface level with the first planar surface. An air gap extends from the second planar surface of the metallic material into the metallic material. An edge of the air gap is aligned to an edge of the metallic material.

Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.

Abstract: A heating method includes an oxide film forming step and a heating step. The thickness of an oxide film is set in a first range that includes a first maximal thickness and a second maximal thickness and that is smaller than a second minimal thickness in the relationship with the laser absorption having a periodic profile. The first maximal thickness corresponds to a first maximal value a of the laser absorption. The second maximal thickness corresponds to a second maximal value of the laser absorption. The second minimal thickness corresponds to a second minimal value of the laser absorption, namely the minimal value of the laser absorption that appears between the second maximal value and a third maximal value, or the maximal value of the laser absorption that appears subsequent to the second maximal value.

Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.

Abstract: A semiconductor structure includes a first stacking interposer. The first stacking interposer includes a first interposer having a first surface and a second surface opposite thereto; a plurality of first conductive pillars penetrating through the first interposer from the first surface to the second surface; a plurality of first bumps disposed at a side of the first surface of the first interposer and electrically connected to the first conductive pillars; and a first redistribution layer disposed on the second surface of the first interposer. The first surface has a clearance region where is free of the first bumps. A first chip is disposed over the first redistribution layer. The first chip is aligned with the clearance region of the first surface of the first interposer in a direction perpendicular to the first surface. A plurality of second bumps interconnecting the first redistribution layer with the first chip.

Abstract: A power module includes a base plate, first, second, and third semiconductor chips. At least one of a third edge or fourth edge of the first semiconductor chip is disposed adjacent to a side end of the base plate. Among a half of a distance from a first edge of the first semiconductor chip to one edge of the second semiconductor chip, a half of a distance from a second edge of the first semiconductor chip to one edge of the third semiconductor chip, and a distance from the third edge or fourth edge of the first semiconductor chip disposed adjacent to the side end of the base plate to the side end of the base plate, a length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is formed in the shortest length.

Abstract: Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap.

Abstract: Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. The method may further include applying a conformal protective coating over the package surface conductor. An embodiment of a device formed using such a method includes a package body, the first and second device-to-edge conductors, the package surface conductor on a surface of the package body and extending between the first and second device-to-edge conductors, and the conformal protective coating over the package surface conductor.

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

Abstract: A semiconductor device includes a chip, a plurality of first bumps, and a plurality of second bumps. The chip includes an active surface. The first bumps are disposed on the active surface along a first direction. The second bumps are disposed on the active surface along a second direction parallel to the first direction, wherein one of the second bumps is located between adjacent two of the first bumps, a closest distance from the second bumps to the fan-out region is smaller than a closest distance from the first bumps to the fan-out region, and a first width of one of the first bumps is larger than a second width of one of the second bumps.

Abstract: An optoelectronic device is provided, including light-emitting diodes arranged such that: N diodes of said plurality, where N ?2, are connected in series and are configured to be forward-biased, and at least one diode is connected in parallel to the N diodes and is configured to be reverse-biased and to form a Zener diode, wherein a sum of threshold voltages of the N diodes is less than a breakdown voltage of the Zener diode, and the light-emitting diodes include a stack of semiconductive portions including a first conductivity-type doped portion, a second conductivity-type doped portion opposite the first type, and a first intermediate portion doped according to the first type and being disposed between said first and second portions and having a doping level such that the breakdown voltage is greater than the sum of the threshold voltages of each of the N diodes.

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract: A semiconductor device is disclosed. The device includes a substrate including GaN, a two dimensional electron gas (2DEG) inducing layer on the substrate, and a lateral transistor on the 2DEG inducing layer. The lateral transistor includes source and drain contacts to the 2DEG inducing layer, a gate stack between the source and drain contacts, and a field plate between the gate and the drain contact. The device also includes one or more insulation layers on the 2DEG inducing layer, where the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, and a conductor on the insulation layers, where a first portion of the conductor is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than 200 nm.

Abstract: An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

Abstract: An integrated semiconductor device is provided. According to an embodiment, the integrated semiconductor device includes a semiconductor body having a first surface with a normal direction defining a vertical direction, an opposite surface, a first area including a vertical power field-effect transistor structure, a second area including a three-terminal step-down level-shifter, and a third area including a three-terminal step-up level-shifter. A terminal of the vertical power field-effect transistor structure is electrically connected with one of the three-terminal step-down level-shifter and the three-terminal step-up level-shifter.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: A semiconductor device includes a multilayer structure including an n? i layer, a p anode layer formed on the front surface of the n? i layer, an n? buffer layer formed on the back surface of the n? i layer, an n+ cathode layer and a p collector layer formed on the back surface of the n? buffer layer or on the back surfaces of the n? i layer and the n? buffer layer such that the n+ cathode layer and the p collector layer are adjacent to each other in a plan view or adjacent portions thereof overlap each other in a plan view, a front surface electrode, and a back surface electrode. A vertical position in the multilayer structure of the n+ cathode layer in the multilayer structure differs from that of the p collector layer.

Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.

Abstract: The present disclosure describes a semiconductor device. The device includes a semiconductor substrate, an isolation structure formed in the substrate for isolating a first active region and a second active region, a first transistor formed in the first active region, the first transistor having a high-k gate dielectric layer and a metal gate with a first work function formed over the high-k gate dielectric layer, and a second transistor formed in the second active region, the second transistor having the high-k gate dielectric layer and a metal gate with a second work function formed over the high-k gate dielectric layer. The metal gates are formed from at least a single metal layer having the first work function and the second work function.

Abstract: In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first fin-shaped structure and a bump are formed on the substrate, and an insulating layer is formed on the bump and around the first fin-shaped structure. Next, a part of the first fin-shaped structure is removed, an epitaxial layer is formed on the first fin-shaped structure, part of the epitaxial layer is removed, and part of the insulating layer is removed to form a shallow trench isolation (STI) and a second fin-shaped structure protruding from the STI. Preferably, the second fin-shaped structure includes a top portion and a bottom portion, in which the bottom portion and the bump are made of same material.

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

Abstract: Provided is a technology for further reducing a loss in a semiconductor device including a semiconductor substrate in which an IGBT region and a diode region are provided. This semiconductor device includes a semiconductor substrate in which at least one IGBT region and at least one diode region are provided. The IGBT region and the diode region are adjacent to each other in a predetermined direction in a plan view of the semiconductor substrate. In the plan view of the semiconductor substrate, a first boundary plane where the collector region and the cathode region are adjacent is shifted from a second boundary plane where the IGBT region and the diode region are adjacent on the front surface side of the semiconductor substrate either in a direction from the cathode region toward the collector region or in a direction from the collector region toward the cathode region.

Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.

Abstract: A method for forming a semiconductor device includes providing a substrate having a plurality of memory cells formed therein; forming an insulating layer on the substrate; forming a plurality of openings in the insulating layer and exposing a portion of the memory cells; forming a conductive portion and a metal layer in the openings; removing a portion of the metal layer to form a plurality of first metal portions and a plurality of second metal portions that the first metal portion and the conductive portion form a first connecting structure, and the second metal portion and the conductive portion form a second connecting structure; forming a passivation layer on the first connecting structures; and forming a plurality of first storage nodes and dummy nodes on the substrate and the first storage nodes and the dummy nodes are electrically connected to the second connecting structures and the first connecting structures respectively.

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Abstract: In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.

Abstract: Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.

Abstract: Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.

Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; an electrode layer; a first insulating film; a charge storage film; and a second insulating film. The first insulating film is provided between the electrode layer and the semiconductor layer. The charge storage film is provided between the first insulating film and the electrode layer. The charge storage film includes a charge trapping layer and a floating electrode layer. The floating electrode layer includes doped silicon. The second insulating film is provided between the floating electrode layer and the electrode layer.

Abstract: A method for generating a non-volatile memory device may comprise: applying plasma for a preset time period to an exposed surface of a channel of a field effect transistor such that a plurality of charge-trapping sites are formed at the channel. The channel is comprised of a multi-layer structure of atomically thin two-dimensional sheets.

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body and a column. The stacked body includes a plurality of electrode layers. The column includes a semiconductor channel, a charge storage film, and a doped silicon layer. The semiconductor channel extends in the stacking direction. The semiconductor channel is a polycrystalline. An average grain size of crystals in a polycrystalline is not less than a film thickness of the semiconductor channel. The charge storage film is provided between the semiconductor channel and the electrode layers. The doped silicon layer contains a metal element and an impurity other than a metal element. The doped silicon layer is in contact with a top end of the semiconductor channel.

Abstract: A semiconductor memory device includes a conductive layer; electrode layers stacked on the conductive layer; an insulating body extending through the electrode layers; and a semiconductor layer positioned between the insulating body and the electrode layers. The plurality of electrode layers include a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and the semiconductor layer has a first layer thickness between the insulating body and the first electrode layer, a second layer thickness between the insulating body and the second electrode layer and a third layer thickness between the insulating body and the third electrode layer. The first layer thickness is thinner than the second layer thickness, and the second layer thickness is thinner than the third layer thickness.

Abstract: Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge storage elements can be formed in the memory openings. Inter-level charge leakage in a three-dimensional memory device including a charge trapping layer can be minimized by employing a thin continuous charge trapping material layer within each memory opening. After removal of the sacrificial material layers and formation of backside recesses, discrete charge trapping material portions can be formed by selective growth of a charge trapping material from physically exposed surfaces of each thin continuous charge trapping material layer. The discrete charge trapping material portions can function as primary charge storage regions, and inter-level charge leakage can be minimized by the small thickness of the thin continuous charge trapping material layer.

Abstract: Contact areas for three-dimensional memory devices including multiple vertically stacked tier structures can be reduced by overlapping stepped terraces of the tier structures. Sacrificial via structures laterally surrounded by a respective insulating spacer can be formed through an overlying tier structure in the stepped terrace region thereof. After formation of memory stack structures, the sacrificial via structures can be removed to provide first upper via cavities. An isotropic etch can be performed to extend the first upper via cavities to top surfaces of underlying first electrically conductive layers in an underlying tier structure while forming second upper via cavities extending to second electrically conductive layers in the overlying tier structure.

Abstract: A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

Abstract: A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

Abstract: A base and a manufacturing method thereof and a display device are provided, so that a problem of faultage of an insulating layer when forming the insulating layer on an aluminum electrode of a substrate is solved. The base includes an aluminum electrode in a first setting pattern on a substrate, and an aluminum oxide layer or an aluminum nitride layer (3) in a second setting pattern provided in a same layer with the aluminum electrode. The first setting pattern and the second setting pattern are complementary to each other.