Patents Issued in August 14, 2018
  • Patent number: 10049863
    Abstract: Implementations of the present disclosure relate to a sputtering target for a sputtering chamber used to process a substrate. In one implementation, a sputtering target for a sputtering chamber is provided. The sputtering target comprises a sputtering plate with a backside surface having radially inner, middle and outer regions and an annular-shaped backing plate mounted to the sputtering plate. The backside surface has a plurality of circular grooves which are spaced apart from one another and at least one arcuate channel cutting through the circular grooves and extending from the radially inner region to the radially outer region of sputtering plate. The annular-shaped backing plate defines an open annulus exposing the backside surface of the sputtering plate.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 14, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Brian T. West, Michael S. Cox, Jeonghoon Oh
  • Patent number: 10049864
    Abstract: The invention describes a metal container that comprises a cathode containing an insulated anode with gases at pressures less than a fraction (0.1-0.9) of a mmHg. Metallic normal glow discharge diode and triode devices with large cold cathode area as efficient charge generator to function as a power cell. A metallic glow discharge device comprising a cylindrical cathode and a coaxial insulated anode containing gas at very low pressure utilizing radial electric field. A metallic normal glow discharge diode device containing a planar geometry, with an insulated metallic plate parallel to the broad side of the container forms the anode, while the container acts as the cathode.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: August 14, 2018
    Inventor: Upendra D Desai
  • Patent number: 10049865
    Abstract: The present invention relates to improving the ability of a hyphenated instrument to analyze a sample benefiting from having the first instrument's analysis of the same sample. A fast switching mechanism can be used as the interface between an ion mobility spectrometer (IMS) and a mass spectrometer (MS) such that the obtained IMS spectrum is converted into a timing diagram that controls the vacuum inlet's size dynamically during analysis of a neutral and/or charged chemical and/or biological species such that a smaller pumping system can be used.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 14, 2018
    Assignee: Excellims Corporation
    Inventors: Mark A Osgood, Ching Wu
  • Patent number: 10049866
    Abstract: A method for analyzing an aliphatic compound by mass spectrometry which comprises: (i) ionizing an aliphatic compound in the presence of a heterocyclic modifier; and (ii) mass analyzing the resulting ions to obtain mass spectrometric data.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 14, 2018
    Assignee: MICROMASS UK LIMITED
    Inventors: David Douce, Gareth R. Jones
  • Patent number: 10049867
    Abstract: An apparatus 41 and operation method are provided for an electrostatic trap mass spectrometer with measuring frequency of multiple isochronous ionic oscillations. For improving throughput and space charge capacity, the trap is substantially extended in one Z-direction forming a reproduced two-dimensional field. Multiple geometries are provided for trap Z-extension. The throughput of the analysis is improved by multiplexing electrostatic traps. The frequency analysis is accelerated by the shortening of ion packets and either by Wavelet-fit analysis of the image current signal or by using a time-of-flight detector for sampling a small portion of ions per oscillation. Multiple pulsed converters are suggested for optimal ion injection into electrostatic traps.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 14, 2018
    Assignee: LECO Corporation
    Inventor: Anatoly N. Verenchikov
  • Patent number: 10049868
    Abstract: An apparatus for detecting constituents in a sample includes first and second drift tubes defining first and second drift regions, and a controllable electric field device within a fragmentation region coupled to the first and second drift tubes. The apparatus also includes a first ion shutter positioned between the first drift and fragmentation regions. The apparatus further includes a control system configured to regulate the first ion shutter, thereby facilitating injection of a selected portion of ions from the first drift region into the fragmentation region. The control system is also configured to regulate the controllable device to modify the selected portion of ions to generate predetermined ion fragments within the fragmentation region, thereby facilitating injection of a selected portion of the predetermined fragmented ions into the second drift region. A method of detecting constituents in a sample is facilitated through such an apparatus.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 14, 2018
    Assignee: Rapiscan Systems, Inc.
    Inventors: Gary A. Eiceman, Stephen J. Davila, Stefan R. Lukow, Hartwig Schmidt
  • Patent number: 10049869
    Abstract: Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers. The composite films in one embodiment include at least two elements selected from the group consisting of Al, Si, and Ge, and at least one element selected from the group consisting of O, N, and C. In one embodiment the composite film includes Al, Si and O. In one implementation, a substrate containing an exposed dielectric layer (e.g., a ULK dielectric) and an exposed metal layer is contacted with an aluminum-containing compound (such as trimethylaluminum) and, sequentially, with a silicon-containing compound. Adsorbed compounds are then treated with an oxygen-containing plasma (e.g., plasma formed in a CO2-containing gas) to form a film that contains Al, Si, and O.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 14, 2018
    Assignee: Lam Research Corporation
    Inventors: Kapu Sirish Reddy, Nagraj Shankar, Shankar Swaminathan, Meliha Gozde Rainville, Frank L. Pasquale
  • Patent number: 10049870
    Abstract: To inhibit excessive oxidation and increase oxidation resistance of a polysilicon film on a substrate during recovery process, an oxygen-containing silicon layer present on the substrate is modified into a silicon oxynitride layer or a silicon nitride layer with high nitrogen concentration prior to the recovery process by heating the substrate and supplying active species containing nitrogen radicals and hydrogen radicals for increasing nitrogen content in the silicon oxynitride layer or the silicon nitride layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 14, 2018
    Assignee: Kokusai Electric Corporation
    Inventor: Akito Hirano
  • Patent number: 10049871
    Abstract: The present invention generally relates to nanoscale wires, including anisotropic deposition in nanoscale wires. In one set of embodiments, material may be deposited on certain portions of a nanoscale wire, e.g., anisotropically. For example, material may be deposited on a first facet of a crystalline nanoscale wire but not on a second facet. In some cases, additional materials may be deposited thereon, and/or the portions of the nanoscale wire may be removed, e.g., to produce vacant regions within the nanoscale wire, which may contain gas or other species. Other embodiments of the invention may be directed to articles made thereby, devices containing such nanoscale wires, kits involving such nanoscale wires, or the like.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 14, 2018
    Assignees: President and Fellows of Harvard College, Korea University
    Inventors: Charles M. Lieber, Sun-Kyung Kim, Robert Day, Hong-Gyu Park, Thomas J. Kempa
  • Patent number: 10049872
    Abstract: A method includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Chiao-Tung University
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Patent number: 10049873
    Abstract: The invention provides a preparation method of a low temperature poly-silicon thin film, a preparation method of a low temperature poly-silicon thin film transistor, and a laser crystallization apparatus, and belongs to the technical field of display. The preparation method of a low temperature poly-silicon thin film of the invention comprises: forming an amorphous silicon thin film on a transparent substrate; and performing laser annealing on said amorphous silicon thin film from a side of said amorphous silicon thin film departing from said substrate, and performing laser irradiation from a side of said substrate departing from said amorphous silicon thin film, to form a low temperature poly-silicon thin film.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 14, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaowei Xu, Xiaolong Li
  • Patent number: 10049874
    Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
  • Patent number: 10049875
    Abstract: Provided is a method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising: providing a substrate in a process chamber of a patterning system, the substrate comprising a first structure pattern and an underlying layer, the underlying layer comprising a silicon anti-reflective coating (SiARC) or a silicon oxynitride (SiON) layer, an optical planarization layer, and a target patterning layer; performing an optional CD trimming process of the first structure pattern; performing a series of processes to open the SiARC or SiON layer and performing additional CD trimming if required; and performing a series of processes to open the optical planarization layer, the series of processes generating a final structure pattern, and performing additional CD trimming if required; wherein the planarization layer is one of a group comprising an advance patterning film (APF), an organic dielectric layer (ODL) or a spin-on hardmask (SOH) layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 14, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Angelique Raley, Akiteru Ko
  • Patent number: 10049876
    Abstract: A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • Patent number: 10049877
    Abstract: A method for forming fine patterns is described. A bottom layer, a hard mask layer, a buffer mask layer and a mask layer are sequentially formed on a substrate. The mask layer and the buffer mask layer are patterned to form first columnar bodies. The buffer mask layer is partially removed in the first columnar bodies and a sacrifice dielectric material is filled in the first gap between the first columnar bodies. The sacrifice dielectric material is patterned to form second columnar bodies. A conformal spacer layer is deposited on the second columnar bodies, and the conformal spacer layer forms spaced columnar body between the adjacent second columnar bodies. A second gap is formed between the spaced columnar body and the second columnar body. A core mask layer is formed in the second gaps. The mask layer and the sacrifice dielectric material are removed.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: August 14, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10049878
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 10049879
    Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Romain Esteve, Markus Kahn, Kurt Pekoll, Juergen Steinbrenner, Gerald Unegg
  • Patent number: 10049880
    Abstract: A method of manufacturing a semiconductor device, where the device includes a donor layer that is obtained by changing a crystal defect formed in a first-conduction-type drift layer by proton radiation into a donor and in which the donor layer has an impurity concentration distribution including a first portion with a maximum impurity concentration and a second portion with a concentration gradient in which the impurity concentration is reduced from the first portion to both surfaces of the first-conduction-type drift layer. The method includes performing proton radiation for a first-conduction-type semiconductor substrate which will be the first-conduction-type drift layer to form a crystal defect in the first-conduction-type semiconductor substrate; and performing a heat treatment at a temperature equal to or higher than 300° C. and equal to or lower than 450° for one minute to 300 minutes to change the crystal defect into a donor.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 14, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomonori Mizushima, Yusuke Kobayashi
  • Patent number: 10049881
    Abstract: Embodiments of the invention provide an improved apparatus and methods for nitridation of stacks of materials. In one embodiment, a remote plasma system includes a remote plasma chamber defining a first region for generating a plasma comprising ions and radicals, a process chamber defining a second region for processing a semiconductor device, the process chamber comprising an inlet port formed in a sidewall of the process chamber, the inlet port being in fluid communication with the second region, and a delivery member disposed between the remote plasma chamber and the process chamber and having a passageway in fluid communication with the first region and the inlet port, wherein the delivery member is configured such that a longitudinal axis of the passageway intersects at an angle of about 20 degrees to about 80 degrees with respect to a longitudinal axis of the inlet port.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 14, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Matthew S. Rogers, Roger Curtis, Lara Hawrylchak, Ken Kaung Lai, Bernard L. Hwang, Jeffrey Tobin, Christopher Olsen, Malcolm J. Bevan
  • Patent number: 10049882
    Abstract: A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on the structure using an atomic layer deposition (ALD) method. Forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference. Forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor, and a second gas including nitrogen components into a chamber including the substrate such that the first dielectric layer is formed in situ on the structure having the height difference.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 14, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., DOW SILICONES CORPORATION
    Inventors: Won Woong Chung, Sun hye Hwang, Youn Joung Cho, Jung Sik Choi, Xiaobing Zhou, Brian David Rekken, Byung Keun Hwang, Michael David Telgenhoff
  • Patent number: 10049883
    Abstract: An object is to provide an MRAM dry etching residue removal composition capable of removing dry etching residues while suppressing damage to a substrate containing a specific metal in a step of producing an MRAM, a method of producing a magnetoresistive random access memory using the same, and a cobalt removal composition having excellent cobalt removability. The MRAM dry etching residue removal composition of the present invention contains a strong oxidizing agent and water. In addition, the cobalt removal composition of the present invention contains orthoperiodic acid and water.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 14, 2018
    Assignee: FUJIFILM CORPORATION
    Inventors: Keeyoung Park, Atsushi Mizutani
  • Patent number: 10049884
    Abstract: A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 14, 2018
    Inventor: John Wood
  • Patent number: 10049885
    Abstract: A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hoi-Tou Ng, Kuei-Liang Lu, Ming-Feng Shieh, Ru-Gun Liu
  • Patent number: 10049886
    Abstract: A method embodiment for forming a semiconductor device includes providing a dielectric layer having a damaged surface and repairing the damaged surface of the dielectric layer. Repairing the damaged surface includes exposing the damaged surface of the dielectric layer to a precursor chemical, activating the precursor chemical using light energy, and filtering out a spectrum of the light energy while activating the precursor chemical.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hung Lin, Sheng-Shin Lin, Ying-Chieh Hung, Yu-Ting Huang, Tze-Liang Lee
  • Patent number: 10049887
    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 14, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
  • Patent number: 10049888
    Abstract: Disclosed is a method of regenerating a phosphoric acid solution from a treatment liquid including silicon (Si), hydrogen fluoride (HF), and phosphoric acid, the method including removing the silicon by supplying hydrogen fluoride corresponding to a preset amount or more to the treatment liquid, removing the hydrogen fluoride by heating the treatment liquid to a boiling point of hydrogen fluoride or higher, and adjusting a temperature and a concentration of the phosphoric acid to preset values.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 14, 2018
    Assignee: SEMES CO., LTD.
    Inventors: Seungho Lee, Minhee Cho, Ki-Moon Kang, Tae-Keun Kim
  • Patent number: 10049889
    Abstract: Some embodiments contemplate methods for forming a package structure and a package structure formed thereby. An embodiment method includes depositing a photosensitive dielectric layer on a support structure; forming a first layer on a surface of the photosensitive dielectric layer; exposing the photosensitive dielectric layer to radiation; and after the forming the first layer and the exposing to radiation, developing the photosensitive dielectric layer. The support structure includes an integrated circuit die. The layer has a different removal selectivity than the photosensitive dielectric layer during the developing. According to some embodiments, a thickness uniformity of the photosensitive dielectric layer after developing may be increased, and thickness loss from developing the photosensitive dielectric layer can be reduced.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kou, Sih-Hao Liao
  • Patent number: 10049890
    Abstract: The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed on a bottom surface and sidewall surfaces of a filled trench of the substrate. A first conductive layer is disposed on the first dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A second dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the second dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A third dielectric layer is disposed on the second conductive layer. A third conductive layer is disposed in the filled trench and on the third dielectric layer. A top surface of the third conductive layer is lower than the second surface of the second conductive layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Chih-Jen Chan, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10049891
    Abstract: Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the cobalt, which leaves a residue behind. The methods may include forming a remote plasma of a hydrogen-containing precursor. The methods may also include removing the cobalt residue using plasma effluents of the hydrogen-containing precursor.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 14, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Nitin Ingle
  • Patent number: 10049892
    Abstract: Techniques herein include methods of processing photoresist patterns and photoresist materials for successful use in multi-patterning operations. Techniques include combinations of targeted deposition, curing, and trimming to provide a post-processed resist that effectively enables multi-patterning using photoresist materials to function as mandrels. Photoresist patterns and mandrels are hardened, strengthened, and/or dimensionally adjusted to provide desired dimensions and/or mandrels enabling straight sidewall spacers. Polymer is deposited with tapered profile to compensate for compressive stresses of various conformal or subsequent films to result in a vertical profile despite any compression.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 14, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Nihar Mohanty, Eric Chih-Fang Liu, Elliott Franke
  • Patent number: 10049893
    Abstract: A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: August 14, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Yu-Tzu Peng
  • Patent number: 10049894
    Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Liang Meng, Wei-Hung Lin, Yu-min Liang, Ming-Che Ho, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii
  • Patent number: 10049895
    Abstract: The present teachings disclose various embodiments of a thermal block assembly having low thermal non-uniformity throughout the thermal block assembly. Accordingly, various embodiments of thermal block assemblies having such low thermal non-uniformity provide for desired performance of bioanalysis instrumentation utilizing such thermal block assemblies.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 14, 2018
    Assignee: Life Technologies Corporation
    Inventors: Janusz Wojtowicz, Geoffrey Dahlhoff, Douglas W. Grunewald, Thomas A. Conner
  • Patent number: 10049896
    Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sushumna Iruvanti, Shidong Li, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 10049897
    Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 10049898
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material around the integrated circuit die mounting region. An interconnect structure is over the molding material and the integrated circuit die mounting region. A protection pattern is in a perimeter region of the package around the interconnect structure. The protection pattern includes a first conductive feature that is vertical within the package near a second conductive feature. The first conductive feature has a first width, and the second conductive feature has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu, Chien-Fu Tseng
  • Patent number: 10049899
    Abstract: A substrate cleaning apparatus for removing particles adhered to a substrate includes a cleaning chamber for cleaning a substrate under a vacuum atmosphere, a mounting unit, provided in the cleaning chamber, for mounting the substrate thereon. The substrate cleaning apparatus further includes a nozzle unit for injecting a cleaning gas from an area of a higher pressure than an atmosphere in which the substrate is mounted toward the substrate in the cleaning chamber, generating a gas cluster as an aggregate of atoms or molecules of the cleaning gas by adiabatic expansion and irradiating the gas cluster to the substrate in a direction perpendicular thereto, a gas exhaust port for evacuating the cleaning chamber, and a moving unit for relatively moving the mounting unit and the nozzle unit.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: August 14, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kazuya Dobashi, Kensuke Inai
  • Patent number: 10049900
    Abstract: A substrate treatment method and apparatus including a change controlling unit which changes at least one of a protection liquid application position relative to a liquid droplet nozzle and a protection liquid incident angle relative to the liquid droplet nozzle, the protection liquid application position being a position at which the protection liquid is applied on an upper surface of the substrate, the protection liquid incident angle being an angle at which the protection liquid is incident on the liquid application position; wherein the change controlling unit controls the liquid application position and the incident angle in a first condition when the spraying region is located on an upper surface center portion of the substrate, and controls the liquid application position and the incident angle in a second condition when the spraying region is located on an upper surface peripheral portion of the substrate.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: August 14, 2018
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Kota Sotoku, Takayoshi Tanaka, Masanobu Sato
  • Patent number: 10049901
    Abstract: A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Yen-Chang Chu, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Ru-Liang Lee
  • Patent number: 10049902
    Abstract: A substrate stack holder, a container comprising a plurality of substrate stack holders, and a method for parting a substrate stack. The substrate stack holder includes (a) a holding and separating device for (i) holding a substrate stack during a parting process in which the substrate stack is split into a first substrate stack part and a second substrate stack part, said substrate stack comprised of a first substrate, a second substrate, and a connecting region therebetween, and (ii) separating the first substrate stack part from the second substrate stack part after the parting process; and (b) a fixing device for receiving and fixing the separated first and second substrate stack parts.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: August 14, 2018
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Andreas Fehkuhrer
  • Patent number: 10049903
    Abstract: Methods of manufacturing a heater are provided that generally include forming a laminate having a dielectric layer, a first double-sided adhesive dielectric layer, and a conductive layer. Next, a circuit pattern is created into the conductive layer, and then the circuit pattern is covered with a second double-sided adhesive dielectric layer. The second double-sided adhesive dielectric layer is covered with a sacrificial layer, and then the heater is formed, the heater comprising the dielectric layer, the first double-sided adhesive dielectric layer, the conductive layer, and the second double-sided adhesive dielectric layer. Subsequently, the sacrificial layer is removed.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 14, 2018
    Assignee: Watlow Electric Manufacturing Company
    Inventors: Kevin Ptasienski, Allen Norman Boldt, Janet Lea Smith, Cal Thomas Swanson, Mohammad Nosrati, Kevin Robert Smith
  • Patent number: 10049904
    Abstract: A method and a system for moving a substrate, the system includes a chamber, a chuck, a movement system that is positioned outside the chamber, a controller, an intermediate element, at least one sealing element that is configured to form a dynamic seal between the intermediate element and the chamber housing. The movement system is configured to repeat, for each region of the substrate out of a plurality of regions of the substrate, the steps of: rotating the chuck to position a given portion of the region of the substrate within a field of view that is related to an opening of the chamber housing; and moving the chuck relation to the opening to position additional portions of the region of the substrate within the field of view that is related to the opening.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 14, 2018
    Assignees: Applied Materials, Inc., Applied Materials Israel Ltd.
    Inventors: Ofer Adan, Israel Avneri, Yoram Uziel, Igor Krivts (Krayvitz), Niranjan Ramchandra Khasgiwale
  • Patent number: 10049905
    Abstract: A substrate heat treatment apparatus includes: a placement unit on which a substrate is placed; a heat treatment unit for heating or cooling the substrate on the placement unit; a plurality of temperature sensors positioned correspondingly to a plurality of locations of the substrate on the placement unit; and a control unit. The control unit is configured to control the heat treatment unit based on temperatures detected by the temperature sensors, to calculate a position of a thermal center of gravity of the substrate based on the temperatures detected by the temperature sensors, and to detect heat treatment condition of the substrate based on the position of the thermal center of gravity.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 14, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Koudai Higashi, Shinichiro Misaka
  • Patent number: 10049906
    Abstract: Provided is a substrate processing apparatus, which comprises a processing chamber, a substrate sensing assembly, a rotation shaft and a driving assembly. A portion of the rotation shaft is provided inside the processing chamber and the remaining portion thereof is provided outside the processing chamber. The substrate sensing assembly is provided on the portion of the rotation shaft outside the processing chamber. The driving assembly is fixed at the portion of the rotation shaft inside the processing chamber. The driving assembly drives, when coming into contact with the substrate, the rotation shaft to rotate about its own axis along a first direction, and drives, when the substrate comes into no contact with the driving assembly, the rotation shaft to rotate about its axis along a second direction opposite to the first direction. The treatment liquid does not affect the substrate sensing assembly since it is provided outside the processing chamber.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 14, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Weigang Peng, Wei Zhou, Chengnan Hsieh, Yu Yang, Giseub Lim, Chen Yuan
  • Patent number: 10049907
    Abstract: An automated module for assembly lines to assemble electronic devices includes a plurality of cells. Each cell includes a support structure, a control unit and at least one actuating system, operatively connected to the control unit for receiving commands and transmitting the results obtained as data to and from the control unit. The automated module includes at least one moving device, for moving at least one electronic device among the module's cells; and a supervision unit. The supervision unit interacts with each control unit of each cell, thus sending commands to control each single cell and receiving respective results from the respective control units as data; and to control the moving device for its activation, to move the electronic devices among the cells. The cells are independent and are assembled in a modular manner in the desired sequence, to perform a desired sequence of operations on the electronic device.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: August 14, 2018
    Assignee: BITRON S.P.A.
    Inventors: Federico Perrero, Vincenzo Siciliano, Dario Bisson, Alessandro Arnaboldi, Angelo Viola
  • Patent number: 10049908
    Abstract: In one embodiment of the invention, a substrate support assembly comprises an electrostatic chuck having an electrode embedded therein and having an aperture disposed therethrough, a conductive liner disposed on the surface of the electrostatic chuck within the aperture, a conductive tubing extending from a lower surface of the electrostatic chuck and axially aligned with the aperture, and a conductive coating at least partially within the aperture and at least partially within the conductive tubing, wherein the conductive coating provides a conductive path between the conductive liner and the conductive tubing.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: August 14, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Govinda Raj, Robert T. Hirahara
  • Patent number: 10049909
    Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
  • Patent number: 10049910
    Abstract: An object of the present invention is to prevent a semiconductor substrate from being damaged when the substrate is conveyed by a conveying robot provided in a semiconductor manufacturing apparatus. A diffusion furnace apparatus has a diffusion furnace that processes a semiconductor wafer, a quartz boat that is arranged in the diffusion furnace to store the semiconductor wafer, and a conveying robot that delivers the semiconductor wafer between the quartz boat and a cassette carried in from the outside. Further, the conveying robot includes a column-like sensor support unit provided at a part that is not turned, and a first sensor that detects the presence or absence of the semiconductor wafer held on a plate of the conveying robot and a second sensor that detects the positional displacement of the semiconductor wafer held on the plate are provided at the sensor support unit.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 14, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuji Kirino, Shinji Nakaguma
  • Patent number: 10049911
    Abstract: A method for performing temporally pulsed chemical vapor deposition (CVD) is provided, including: providing a first reactant configured to adsorb on exposed surfaces of a substrate in a self-limiting manner, the first reactant being provided at a partial pressure so that the first reactant diffuses into a gap feature of the substrate; performing a first purge operation, the first purge operation being configured to partially purge the first reactant, so that gas phase first reactant species remain in the gap feature; providing a second reactant to the process chamber, the second reactant being configured to react with the first reactant to form a film product, including reaction of the provided second reactant with the adsorbed first reactant species, and reaction of the provided second reactant with the gas phase first reactant species in the gap feature; performing a second purge operation.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 14, 2018
    Assignee: Lam Research Corporation
    Inventors: Shankar Swaminathan, Frank L. Pasquale
  • Patent number: 10049912
    Abstract: A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Andre Brockmeier, Elmar Falck, Francisco Javier Santos Rodriguez, Holger Schulze