Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a substrate with an oxide film formed on a surface thereof; pre-processing a surface of the oxide film; and forming a nitride film containing carbon on the surface of the oxide film which has been pre-processed, by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; supplying a carbon-containing gas to the substrate; and supplying a nitrogen-containing gas to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; and supplying a gas containing carbon and nitrogen to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas containing carbon to the substrate; and supplying a nitrogen-containing gas to the substrate.

Abstract: Plasma source assemblies comprising a housing with an RF hot electrode and a return electrode are described. The housing includes a gas inlet and a front face defining a flow path. The RF hot electrode includes a first surface oriented substantially parallel to the flow path. The return electrode includes a first surface oriented substantially parallel to the flow path and spaced from the first surface of the RF hot electrode to form a gap. Processing chambers incorporating the plasma source assemblies and methods of using the plasma source assemblies are also described.

Abstract: Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.

Abstract: Apparatuses and methods are provided for manufacturing diamond electronic devices. The method includes at least one of the following acts: positioning a substrate in a plasma enhanced chemical vapor deposition (PECVD) reactor; controlling temperature of the substrate by manipulating microwave power, chamber pressure, and gas flow rates of the PECVD reactor; and growing phosphorus doped diamond layer on the substrate using a pulsed deposition comprising a growth cycle and a cooling cycle.

Abstract: The present invention relates to a method of fabricating a black phosphorus thin film and a black phosphorus thin film thereof and, more particularly, to a method of fabricating a black phosphorus ultrathin film by forming the black phosphorous ultrathin film in a chamber by active oxygen and removing accompanying black phosphorus oxide film water. The black phosphorus ultrathin film has a surface that does not substantially have defects and is uniform in a large area, and has a surface roughness property of 1 nm or less, to represent a high application property to an optoelectronic device and a field effect transistor.

Abstract: The present invention, when forming a pattern on a substrate, forms a film of a block copolymer containing at least two polymers on the substrate, heats the film of the block copolymer under a solvent vapor atmosphere to subject the block copolymer to phase separation, and removes one of the polymers in the film of the phase-separated block copolymer, thereby accelerating fluidization of the polymers of the block copolymer to enable acceleration of the phase separation.

Abstract: A method of fabricating a semiconductor device includes forming a metal film including Cu on a substrate, forming a protective film on the metal film, forming a hard mask including TaOx, where x is 2.0 to 2.5, on the protective film, forming a hard mask pattern by patterning the hard mask, and forming a metal wiring by patterning the metal film, using the hard mask pattern as an etching mask.

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Abstract: A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm?3.

Abstract: A thin film containing a dopant is deposited on a surface of a semiconductor wafer. The semiconductor wafer on which the thin film containing the dopant is deposited is rapidly heated to a first peak temperature by irradiation with light from halogen lamps, so that the dopant is diffused from the thin film into the surface of the semiconductor wafer. The thermal diffusion using the rapid heating achieves the introduction of the necessary and sufficient dopant into the semiconductor wafer without producing defects. The surface of the semiconductor wafer is heated to a second peak temperature by further irradiating the semiconductor wafer with flashes of light from flash lamps, so that the dopant is activated. The flash irradiation which is extremely short in irradiation time achieves a high activation rate without excessive diffusion of the dopant.

Abstract: A semiconductor device has an active region that includes a semiconductor layer. A transistor is formed in and above the active region, wherein the transistor has an implanted halo region that includes a halo dopant species and defines a halo dopant profile in the semiconductor layer. An implanted carbon species is positioned in the semiconductor layer, wherein the implanted carbon species defines a carbon species profile in the semiconductor layer that is substantially the same as the halo dopant profile of the implanted halo region in the semiconductor layer.

Abstract: An ion implantation method for scanning an ion beam reciprocally in an x direction and moving a wafer reciprocally in a y direction to implant ions into the wafer is provided. The method includes: irradiating a first wafer arranged to meet a predetermined plane channeling condition with the ion beam and measuring resistance of the first wafer irradiated with the ion beam; irradiating a second wafer arranged to meet a predetermined axial channeling condition with the ion beam and measuring resistance of the second wafer irradiated with the ion beam; and adjusting an implant angle distribution of the ion beam by using results of measuring the resistance of the first and second wafers.

Abstract: In one aspect, a method of processing a semiconductor substrate is disclosed, which comprises incorporating at least one dopant in a semiconductor substrate so as to generate a doped polyphase surface layer on a light-trapping surface, and optically annealing the surface layer via exposure to a plurality of laser pulses having a pulsewidth in a range of about 1 nanosecond to about 50 nanoseconds so as to enhance crystallinity of said doped surface layer while maintaining high above-bandgap, and in many embodiments sub-bandgap optical absorptance.

Abstract: A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device.

Abstract: Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.

Abstract: Processing methods comprising exposing a substrate to an optional nucleation promoter followed by sequential exposure of a first reactive gas comprising a metal oxyhalide compound and a second reactive gas to form a metal film on the substrate.

Abstract: There is provided a cutting method for cutting a processing-target object by a cutting blade. The cutting method includes a holding step of holding the processing-target object by a holding table and a cutting step of cutting the processing-target object by the cutting blade by causing the cutting blade that rotates to cut into the processing-target object held by the holding table and causing the holding table and the cutting blade to relatively move after the holding step is carried out. In the cutting step, cutting is carried out with detection of whether or not a crack in the processing-target object exists by a crack detecting unit disposed on the rear side relative to the cutting blade in a cutting progression direction in which cutting processing of the processing-target object by the cutting blade progresses.

Abstract: In an embodiment, a miniaturize particulate matter detector includes a filter having a plurality of holes, and a concentration detector correspondingly disposed under the filter. The concentration detector has a detect area used for detecting a concentration of at least one miniaturize particulate matter. A manufacturing method of the filter is also provided.

Abstract: Disclosed is a method of etching a silicon layer by removing an oxide film formed on a workpiece which includes the silicon layer and a mask provided on the silicon layer. The method includes: (a) forming a denatured region by generating plasma of a first processing gas containing hydrogen, nitrogen, and fluorine within a processing container accommodating the workpiece therein to denature an oxide film formed on a surface of the workpiece; (b1) removing the denatured region by generating plasma of a rare gas within the processing container; and (c) etching the silicon layer by generating plasma of a second processing gas within the processing container.

Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes forming, on a substrate, protruding portions with first films on the surfaces thereof, respectively, forming a second film different from the first films so as to fill a depressed portion between the protruding portions and to cover the protruding portions, processing in such a manner that the top surface of the second film on the depressed portion is higher than the top surface of the second film on the protruding portions after forming the second film to cover the protruding portions, and polishing the second film on the depressed and protruding portions to expose the first films.

Abstract: A method of manufacturing a semiconductor device includes forming a reference pattern in an inspection pattern formation region, forming a first mask layer over a semiconductor substrate, while forming a first inspection pattern in the inspection pattern formation region, and measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern. The method further includes implanting ions into the semiconductor substrate using a first mask layer, removing the first mask layer and the first inspection pattern and then forming a second mask layer over the semiconductor substrate, while forming a second inspection pattern in the inspection pattern formation region, and measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern. In plan view, the second inspection pattern is larger than the first inspection pattern and covers the entire region where the first inspection pattern is formed.

Abstract: Embodiments of the present disclosure may relate to a package substrate that may include a layer having a layer surface that is planarized and a via within the layer, where the via includes a via surface that is exposed on the layer surface, and where the via surface is planarized. The package substrate may further include a bond pad on the layer surface, where a first thickness of the bond pad includes a seed layer on the via surface, and where a second thickness of the bond pad includes a plating stack on the seed layer. Other embodiments may be described or claimed.

Abstract: In a substrate processing apparatus, a mounting table and a gas supply part are provided in a processing container to face each other. The processing gas introduced from introduction ports formed in the gas supply part on the opposite side of the gas supply part from the mounting table is supplied to the substrate from gas supply holes formed in an end portion of the gas supply part on the side of the mounting table. The gas supply part includes a central region and one or more outer peripheral regions surrounding the central region. The gas supply holes and the introduction ports are provided for each of the central region and the outer peripheral regions. The processing gas whose gas supply conditions are adjusted for each of the regions is continuously and outwardly supplied in a circumferential direction around the center axis from the introduction ports.

Abstract: Embodiments of a semiconductor processing apparatus are disclosed. The semiconductor processing apparatus includes a micro chamber for tightly accommodating and processing a semiconductor wafer. The micro chamber includes an upper chamber portion defining an upper working surface and a lower chamber portion defining a lower working surface. The upper chamber portion and the lower chamber portion are relatively movable between an open position for loading and removing the semiconductor wafer and a closed position for tightly accommodating the semiconductor wafer. The semiconductor processing apparatus adopts a modified column device, a lower chamber portion and a balance correction device to achieve easy operation and maintenance, better prevention of chemical processing fluid leakage, and corrosion-resistant design.

Abstract: A purge ring for providing a gas to a wafer processing chamber includes an inlet ring wall defining a ring hole space. An outer perimeter of the inlet ring wall is elliptical. An outer perimeter of the ring hole space is circular. The inlet ring wall is a continuous structure surrounding the ring hole space. An inlet baffle formed within the inlet ring wall surrounds at least 180 degrees of the outer perimeter of the ring hole space. An inlet plenum arranged in a first end of the inlet ring wall provides the gas to the ring hole space through the inlet baffle. An exhaust channel is formed within the inlet ring wall in a second end of the inlet ring wall. An exhaust outlet hole arranged in the second end of the inlet ring wall exhausts the gas out of the ring hole space via the exhaust channel.

Abstract: Over a front surface of a silicon semiconductor wafer is deposited a high dielectric constant film with a silicon oxide film, serving as an interface layer, provided between the semiconductor wafer and the high dielectric constant film. After a chamber houses the semiconductor wafer, a chamber's pressure is reduced to be lower than atmospheric pressure. Subsequently, a gaseous mixture of ammonia and nitrogen gas is supplied into the chamber to return the pressure to ordinary pressure, and the front surface is irradiated with a flash light, thereby performing post deposition annealing (PDA) on the high dielectric constant film. Since the pressure is reduced once to be lower than atmospheric pressure and then returned to ordinary pressure, a chamber's oxygen concentration is lowered remarkably during the PDA. This restricts an increase in thickness of the silicon oxide film underlying the high dielectric constant film by oxygen taken in during the PDA.

Abstract: The invention discloses, pickup method, equipment and EMI electromagnetic shielding layer manufacturing method of SiP module. The method for picking up the SiP module comprises the following steps: A nozzle descends to touch the upper surface of the SiP module; the nozzle sucks the SiP module; an air thimble ascends to touch the lower surface of the carrier; the air thimble covers the through hole of the carrier, so as to form the enclosed space for the lower surface of the SiP module, the through hole and the air thimble; compressed air is sprayed into the enclosed space from the hollow structure of the air thimble and acts on the lower surface of the SiP module, so that the bonding between the SiP module and the doubled-sided adhesive tape is loosened; the nozzle ascends and picks up the SiP module.

Abstract: A treatment solution supply method includes: a degassed treatment solution generating step of degassing a treatment solution by a degassing mechanism to generate a degassed treatment solution; a treatment solution storing step of storing the degassed treatment solution in a container; a filter solution-passing step of bringing a downstream side from a filter connected to a downstream side from the container via a treatment solution supply pipe to a negative pressure with respect to a pressure in the container to pass the treatment solution in the container through the filter; and a negative pressure maintaining step of maintaining a state in which the downstream side from the filter is brought to the negative pressure, for a predetermined period, after stopping supply of the treatment solution from the container to the filter.

Abstract: The present invention provides a vacuum processing apparatus that includes gas supply means having a hard interlock of a pair of gas valves. The present invention provides a vacuum processing apparatus including: a gas supply unit that supplies gas, for performing vacuum processing using normally closed type air-driven valves, to a processing chamber where the vacuum processing is performed, the gas supply unit having an interlock function in which, when a first valve of a pair of the air-driven valves is opened, a second valve of the pair is closed, the gas supply unit including an air circuit that controls air for driving the air-driven valves, the air circuit being configured using an electromagnetic valve having a solenoid coil corresponding to each of the pair of the air-driven valves.

Abstract: A method is disclosed evaluating a silicon layer crystallized by irradiation with pulses form an excimer-laser. The crystallization produces periodic features on the crystallized layer dependent on the number of and energy density ED in the pulses to which the layer has been exposed. An area of the layer is illuminated with light. A microscope image of the illuminated area is made from light diffracted from the illuminated are by the periodic features. The microscope image includes corresponding periodic features. The ED is determined from a measure of the contrast of the periodic features in the microscope image.

Abstract: An electrostatic chuck is described with external flow adjustments for improved temperature distribution. In one example, a method for adjusting coolant flow in an electrostatic chuck includes heating a dielectric puck, the dielectric puck being for electrostatically gripping a silicon wafer. Heat is detected at a plurality of locations on a top surface of the dielectric puck, the locations each being thermally coupled to at least one of a plurality of coolant chambers of the electrostatic chuck. A plurality of valves are adjusted to control coolant flow into the coolant chambers based on the detected heat.

Abstract: An assembly used in a process chamber for depositing a film on a wafer including a pedestal assembly having a pedestal movably mounted to a main frame. A lift pad rests upon the pedestal and moves with the pedestal. A raising mechanism separates the pad from the pedestal, and includes a hard stop fixed to the main frame, a roller attached to the pedestal assembly, a slide moveably attached to the pedestal assembly, a lift pad bracket interconnected to the slide and a pad shaft extending from the lift pad, a lever rotatably attached to lift pad bracket, a ferroseal assembly surrounding the pad shaft, and a yoke assembly offsetting a moment to the ferroseal assembly when the lever rotates. When the pedestal assembly moves upwards, the lever rotates when engaging with the upper hard stop and roller, and separates the pad from the pedestal by a process rotation displacement.

Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.

Abstract: A semiconductor substrate arrangement includes a carrier wafer and a plurality of semiconductor substrate pieces fixed to the carrier wafer and distributed laterally over the carrier wafer. The semiconductor substrate pieces of the plurality of semiconductor substrate pieces comprise a hexagonal shape.

Abstract: There is disclosed an improved substrate holding apparatus which can minimize deformation of a spring, which is provided to bias a support post for supporting a substrate, even when a large centrifugal force acts on the spring. The substrate holding apparatus includes: a support post movable in an axial direction thereof; a chuck provided on the support post and configured to hold a periphery of a substrate; a spring biasing the support post in the axial direction; a first structure configured to restrict a movement of an upper portion of the spring in a direction perpendicular to the axial direction of the support post; and a second structure configured to restrict a movement of a lower portion of the spring in a direction perpendicular to the axial direction of the support post.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: Methods of manufacturing a semiconductor device are described. In an embodiment, the method may include providing a substrate having a metal layer disposed thereon, the metal layer having a conductive trace pattern formed therein; depositing a dielectric material over the conductive trace pattern of the metal layer; determining a layout of a plurality of air gaps that will be formed in the dielectric material based on a design rule checking (DRC) procedure and the conductive trace pattern; and forming the plurality of air gaps in the dielectric material based on the layout of the plurality of air gaps.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor chip, conductive paste, and an adhesive layer. The wiring substrate includes an insulating layer and a wiring layer on a surface of the insulating layer. The semiconductor chip includes a circuit-formation surface in which an electrode pad is provided, and is mounted on the wiring substrate with the circuit-formation surface facing toward the wiring layer. The conductive paste electrically connects the wiring layer and the electrode pad. The adhesive layer is over the entirety of the surface of the insulating layer, and covers the wiring layer and the conductive paste. The adhesive layer fills in a gap between the surface of the insulating layer and the circuit-formation surface, to bond the wiring substrate and the semiconductor chip. The adhesive layer extends onto a side surface of the semiconductor chip to form a fillet.

Abstract: An electronic device package and a manufacturing method thereof are provided. The electronic device package includes a flexible substrate, a first wiring structure, a first electronic device and a thermoplastic film having a second wiring structure. The first wiring structure is disposed on the flexible substrate. The first electronic device is disposed on the flexible substrate. The first electronic device and the first wiring structure are separated from each other. The thermoplastic film is welded to the flexible substrate and seals the first electronic device. The second wiring structure electrically connects the first wiring structure to the first electronic device. The electronic device package can be manufactured with a production cost.

Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. The metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer.

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

Abstract: At least one method, apparatus and system disclosed herein involves performing an early-process of source/drain (S/D) contact cut and S/D contact etch steps for manufacturing a finFET device. A gate structure, a source structure, and a drain structure of a transistor are formed. The gate structure comprises a dummy gate region, a gate spacer, and a liner. A source/drain (S/D) contact cut process is performed. An S/D contact etch process is performed. A replacement metal gate (RMG) process is performed subsequent to performing the S/D contact etch process. An S/D contact metallization process is performed.

Abstract: FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.