Patents Issued in November 6, 2018
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Patent number: 10121704Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.Type: GrantFiled: January 4, 2018Date of Patent: November 6, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Yu-Cheng Tung
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Patent number: 10121705Abstract: To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.Type: GrantFiled: August 27, 2014Date of Patent: November 6, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu
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Patent number: 10121706Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.Type: GrantFiled: November 28, 2016Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
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Patent number: 10121707Abstract: A method for making a FET transistor, including the following steps: making, on a crystalline semiconducting layer, a layer of gate dielectric on which a gate conducting layer is arranged, etching the conducting layer such that a remaining portion of this layer fully covers a first semiconducting portion forming an active zone and a second semiconducting portion adjacent to the active zone, implanting atoms and/or dopants in the semiconducting layer, thus amorphizing the semiconductor around the first portion and that of the second portion, etching the remaining portion of the conducting layer and of the dielectric layer according to a gate pattern partially covering the first portion and the second portion, forming the gate and a gate overflow, etching the amorphous semiconductor.Type: GrantFiled: November 17, 2017Date of Patent: November 6, 2018Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Claire Fenouillet-Beranger, Philippe Coronel
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Patent number: 10121708Abstract: A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode. Radiofrequency power is supplied to the electrode to generate a plasma within the plasma generation region. Optical emissions are collected from the plasma using one or more optical emission collection devices, such as optical fibers, charge coupled device cameras, photodiodes, or the like. The collected optical emissions are analyzed to determine whether or not an optical signature of a plasma instability exists in the collected optical emissions. Upon determining that the optical signature of the plasma instability does exist in the collected optical emissions, at least one plasma generation parameter is adjusted to mitigate formation of the plasma instability.Type: GrantFiled: March 18, 2016Date of Patent: November 6, 2018Assignee: Lam Research CorporationInventors: Yukinori Sakiyama, Edward Augustyniak, Douglas Keil
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Patent number: 10121709Abstract: A controller includes a memory that stores a first model corresponding to a first critical dimension of a substrate processed by a substrate processing system and a second model corresponding to a second critical dimension of the substrate. The second model includes a predicted relationship between the first critical dimension and the second critical dimension. A critical dimension prediction module calculates a first prediction of the first critical dimension of the substrate using the first model, provides the first prediction of the first critical dimension as an input to the second model, and calculates and outputs a second prediction of the second critical dimension of the substrate using the second model.Type: GrantFiled: January 24, 2017Date of Patent: November 6, 2018Assignee: LAM RESEARCH CORPORATIONInventor: Ramanapathy Veerasingam
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Patent number: 10121710Abstract: Methods for manufacturing a display device are provided. A representative method includes: providing a thin film transistor (TFT) substrate having a plurality of sub-pixel locations and a plurality of TFTs corresponding to the plurality of sub-pixel locations; providing a carrier substrate supporting a plurality of light emitting diodes (LEDs), wherein each of the plurality of LEDs has a first electrical contact and a second electrical contact; transferring the plurality of LEDs from the carrier substrate to the TFT substrate, with at least two of the plurality of LEDs being disposed at one of the plurality of sub-pixel locations; and fixing positions of the plurality of LEDs with respect to the TFT substrate. The method also may include: determining that a first LED of the plurality of LEDs is defective; and electrically isolating the first electrical contact of first LED from a first electrode of the display device.Type: GrantFiled: January 19, 2017Date of Patent: November 6, 2018Assignee: INNOLUX CORPORATIONInventors: Chia-Hsiung Chang, Ting-Kai Hung, Hsiao-Lang Lin
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Patent number: 10121711Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.Type: GrantFiled: August 3, 2015Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
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Patent number: 10121712Abstract: A method of conducting an in situ reliability test on a cross-section of a device with layered structure at micron-scale and at least two electrodes. The method includes steps of locating an electron transparent cross-sectional portion of the device in a holder and transmitting a direct current bias voltage to the cross-sectional portion of the device through at least two electrodes of the device, and observing and quantifying the microstructural changes of the device cross-section on the holder. A system for conducting an in situ reliability test on a device with a layered structure at a micron-scale and at least two electrodes is also provided.Type: GrantFiled: March 31, 2016Date of Patent: November 6, 2018Assignee: DREXEL UNIVERSITYInventors: Hessam Ghassemi, Andrew C. Lang, Mitra L. Taheri
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Patent number: 10121713Abstract: Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined.Type: GrantFiled: May 8, 2017Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Bipul C. Paul, Hajime Terazawa, Joseph Versaggi
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Patent number: 10121714Abstract: A semiconductor device includes a box-shaped casing including a ceiling wall with a first window, a semiconductor chip having an output electrode and assembled in the casing, a first conductive block disposed in the casing, and a first connection terminal being bent so as to implement an elongated U-shape. The semiconductor device is adapted for electrical connection to a circuit board having a first land. The circuit board is placed on the ceiling wall. The first window is at a position corresponding to the first land. A lower end of the first conductive block is connected to a surface of the output electrode and the first connection terminal contacts to the first conductive block.Type: GrantFiled: May 26, 2017Date of Patent: November 6, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kousuke Komatsu
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Patent number: 10121715Abstract: A semiconductor device fabrication method, including preparing a case having a plurality of connection terminals, and fitting a jig onto the case to protect the connection terminals, tips of the connection terminals protruding from the jig. The method further includes fitting a printed circuit board on the tips of the connection terminals protruding from the jig.Type: GrantFiled: May 10, 2016Date of Patent: November 6, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yo Sakamoto
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Patent number: 10121716Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.Type: GrantFiled: June 27, 2017Date of Patent: November 6, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy
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Patent number: 10121717Abstract: A carbon-coated thermal conductive material includes a coating layer comprising amorphous carbon on a surface of a thermal conductive material, wherein the thermal conductive material comprises a metal oxide, a metal nitride, a metal material, or a carbon-based material having a thermal conductivity of 10 W/mK or greater, the amorphous carbon is derived from carbon contained in an oxazine resin, a ratio of a peak intensity of a G band to a peak intensity of a D band is 1.0 or greater when the amorphous carbon is measured by Raman spectroscopy, an average film thickness of the coating layer is 500 nm or less, and a coefficient of variation (CV value) of a film thickness of the coating layer is 15% or less.Type: GrantFiled: March 27, 2017Date of Patent: November 6, 2018Assignee: SEKISUI CHEMICAL CO., LTD.Inventors: Ren-de Sun, Shoji Nozato, Akira Nakasuga, Masanori Nakamura
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Patent number: 10121718Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.Type: GrantFiled: October 16, 2015Date of Patent: November 6, 2018Assignee: Qorvo US, Inc.Inventors: Dirk Robert Walter Leipold, Julio C. Costa, Baker Scott, George Maxim
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Patent number: 10121719Abstract: Provided is a technique for enhancing heat dissipation properties in dissipating heat generated in an electrode to a heatsink without impairing bonding properties between the electrode and a wire. In a semiconductor device, a portion of an electrode within an inner region defined by a case, at one surface, i.e., the lower surface with respect to a position in which a wire is connected, a resin portion is provided, the resin portion extending from an inner wall of the case to an upper-surface side of the heatsink. Additionally, in the portion of the electrode within the inner region defined by the case, at one surface, i.e., the lower surface with respect to a position in which the wire is not connected, a thermal conductor is provided, the thermal conductor having higher heat conductivity than the resin portion.Type: GrantFiled: March 13, 2017Date of Patent: November 6, 2018Assignee: Mitsubishi Electric CorporationInventor: Yasuo Konishi
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Patent number: 10121720Abstract: A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.Type: GrantFiled: June 8, 2017Date of Patent: November 6, 2018Assignee: STMicroelectronics S.r.l.Inventor: Federico Giovanni Ziglioli
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Patent number: 10121721Abstract: A dummy bump electrode for heat-dissipating is provided on a surface of a semiconductor chip. The semiconductor chip is mounted on a wiring substrate. A lead line is formed on the wiring substrate. The heat-dissipating bump electrode and a lead line are connected to each other through a heat dissipation pattern, thereby efficiency of the heat dissipation is improved.Type: GrantFiled: December 10, 2015Date of Patent: November 6, 2018Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Hiroyoshi Ichikura
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Patent number: 10121722Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.Type: GrantFiled: September 30, 2017Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Chandra M. Jha, Eric J. Li, Zhaozhi Li, Robert M. Nickerson
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Patent number: 10121723Abstract: According to an embodiment of a method, the method includes forming a first thermally conductive layer on an outer surface of a semiconductor package. The first thermally conductive layer formed on the outer surface of the semiconductor package is configured to be mounted to an external heat sink.Type: GrantFiled: April 13, 2017Date of Patent: November 6, 2018Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Kok Tee Lau, Jayaganasan Narayanasamy
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Patent number: 10121724Abstract: A heat diffusion sheet 2 has a configuration in which a composite adhesive film is formed on a surface of a graphite sheet 10 having a thickness of 300 ?m or more and 2,000 ?m or less. This composite adhesive film has a configuration in which (A) an acrylic adhesive layer that has a thickness of 5 ?m or more and 15 ?m or less and does not contain a thermally conductive material, (B) a polyester film having a thickness of 20 ?m or more and 60 ?m or less, and (C) a silicone adhesive layer that has a thickness of 2 ?m or more and 25 ?m or less, does not contain a thermally conductive material, and has a peel strength of 0.005 N/cm or more and 1.0 N/cm or less are sequentially layered on the graphite sheet 10.Type: GrantFiled: February 17, 2015Date of Patent: November 6, 2018Assignee: DEXERIALS CORPORATIONInventors: Minoru Nagashima, Teruo Hiyama
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Patent number: 10121725Abstract: In accordance with the present invention, there are provided heat dispersing articles, assemblies containing same, methods for the preparation thereof, and various uses therefor. In one aspect of the present invention, there are provided heat dispersing articles. In another aspect of the present invention, there are provided methods for producing the above-referenced articles. In yet another aspect of the present invention, there are provided assemblies containing the above-referenced articles. In still another aspect of the present invention, there are provided methods for making the above-referenced assemblies. In yet another aspect, there are provided methods to dissipate the heat generated by portable electronic devices.Type: GrantFiled: November 13, 2017Date of Patent: November 6, 2018Assignee: Henkel IP & Holding GmbHInventors: Yuan Zhao, Mulugeta Berhe, Daniel Maslyk, Scott Timon Allen
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Patent number: 10121726Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.Type: GrantFiled: August 28, 2015Date of Patent: November 6, 2018Assignee: INTEL IP CORPORATIONInventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Alexandra Atzesdorfer, Sonja Koller
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Patent number: 10121727Abstract: The disclosed apparatus may include (1) a cage designed to hold an optical module, (2) a ramp that is secured to the cage and supports a heat sink such that the heat sink is capable of moving along the ramp, and (3) at least one spring having one end coupled to the ramp and another end coupled to the heat sink, wherein (A) prior to insertion of the optical module into the cage, the spring exerts a force at least partially directed along an axis of insertion of the optical module and (B) insertion of the optical module into the cage moves the heat sink along the ramp such that the force exerted by the spring (I) rotates away from the axis of insertion and (II) presses the heat sink against a surface of the optical module. Various other apparatuses, systems, and methods are disclosed.Type: GrantFiled: August 18, 2017Date of Patent: November 6, 2018Assignee: Juniper Networks, Inc.Inventors: Michael E. Lucas, Nikola Ikonomov, John I. Kull
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Patent number: 10121728Abstract: The present invention provides a thin film capacitor including a first electrode layer, a second electrode layer, and a dielectric layer provided between the first electrode layer and the second electrode layer, wherein a ratio (S/S0) of a surface area S of a surface of the first electrode layer on an opposite side to the dielectric layer to a projected area S0 in a thickness direction of the first electrode layer is 1.01 to 5.00.Type: GrantFiled: July 22, 2016Date of Patent: November 6, 2018Assignee: TDK CORPORATIONInventors: Masahiro Yamaki, Hitoshi Saita
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Power electronics assemblies having a semiconductor device with metallized embedded cooling channels
Patent number: 10121729Abstract: A power electronics assembly having a semiconductor device that includes a first device surface opposite a second device surface, a semiconductor substrate layer that extends from the first device surface to a substrate-drift interface, a semiconductor drift layer that extends from the substrate-drift interface towards the second device surface, and a semiconductor fluid channel is positioned within the semiconductor substrate layer of the semiconductor device. Further, the semiconductor fluid channel includes an inner surface. Moreover, a fluid channel metallization layer is positioned along the inner surface of the semiconductor fluid channel.Type: GrantFiled: July 25, 2016Date of Patent: November 6, 2018Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.Inventors: Ercan M. Dede, Kyosuke Miyagi, Yuji Fukuoka -
Patent number: 10121730Abstract: Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling applications. The jet device includes an electromagnetically driven vibrating membrane of conductive material between a top and bottom cavity. A top lid with an opening covers the top cavity, and a permanent magnet is below the bottom cavity. An alternating current signal conducted through the membrane causes the membrane to vibrate in the presence of a magnetic field caused by the permanent magnet. By being manufactured with package forming processes, the jet (1) is manufactured more cost-effectively than by using silicon chip or wafer processing; (2) is easily integrated as part of and with the other layers of a package substrate; and (3) can be driven by a chip mounted on the package. Embodiments also include systems having and processes for forming the jet.Type: GrantFiled: December 19, 2016Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Feras Eid, Jessica Gullbrand, Melissa A. Cowan
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Patent number: 10121731Abstract: A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.Type: GrantFiled: October 11, 2016Date of Patent: November 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Cheon Park, Won Il Lee, Chajea Jo, Taeje Cho
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Patent number: 10121732Abstract: A semiconductor device includes: a base plate including a metallic base plate and an insulating film provided on the metallic base plate; a semiconductor chip provided on the base plate; a control board disposed above the semiconductor chip; and a relay terminal connected to a signal electrode of the semiconductor chip through a signal line wire, extending to the control board, and connected to the control board, wherein the relay terminal is directly fixed to the insulating film of the base plate.Type: GrantFiled: October 16, 2017Date of Patent: November 6, 2018Assignee: Mitsubishi Electric CorporationInventors: Yoshitaka Kimura, Yoshitaka Otsubo
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Patent number: 10121733Abstract: A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.Type: GrantFiled: March 2, 2017Date of Patent: November 6, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yuh-Harng Chien, Chih-Chien Ho, Steven Su
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Patent number: 10121734Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.Type: GrantFiled: January 20, 2016Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventors: Tzung-Han Lee, Yaw-Wen Hu, Neng-Tai Shih, Hsu Chiang, Hsin-Chuan Tsai, Sheng-Hsiung Wu
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Patent number: 10121735Abstract: A semiconductor device includes active fins on a substrate. Gate lines each extend in the second direction on the active fins. A contact plug is positioned on the active fins. A first via is in one of the first contact plugs. A first conductive line overlaps a first via. A first distance from a first active fin on which a first gate line of the gate lines is formed to an end of the first gate line is more than a predetermined distance. A second distance from a second active fin on which the first gate line is formed to the first active fin of the active fins is equal to or less than the predetermined distance. The second active fin is spaced apart from the first contact plugs to not overlap the first contact plugs.Type: GrantFiled: October 26, 2017Date of Patent: November 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon-Ah Nam, Ikuo Nakamatsu, Dong-Hyun Kim, Chul-Hong Park, Yun-Se Oh, Hae-Wang Lee, Ho-Jun Choi
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Patent number: 10121736Abstract: A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.Type: GrantFiled: January 22, 2018Date of Patent: November 6, 2018Assignee: Powertech Technology Inc.Inventors: Kuo-Ting Lin, Chia-Wei Chang
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Patent number: 10121737Abstract: The invention relates to an electronic component, namely a printed circuit board element comprising a first semiconductor component (14) which is arranged on an upper side of an electrically conductive intermediate plate (16) such that a connector pad (18) of the semiconductor component (14) is electrically contacted with the intermediate plate (16) and comprising a second semiconductor component (15) which is arranged on a lower side of the intermediate plate (16). The second semiconductor component (15) comprises a first connector pad (17) and a second connector pad (19), wherein both connector pads (17, 19) are aligned in the direction of the intermediate plate (16) and wherein the first connector pad (17) is contacted with the intermediate plate (16), and wherein the second connector pad (19) is not contacted with the intermediate plate (16). Moreover, the invention relates to a method for producing such a printed circuit board element.Type: GrantFiled: June 27, 2017Date of Patent: November 6, 2018Assignee: SCHWEIZER ELECTRONIC AGInventors: Thomas Gottwald, Christian Roessle
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Patent number: 10121738Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.Type: GrantFiled: January 16, 2017Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Philip J. Ireland
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Patent number: 10121739Abstract: A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed around the first TSV. The second die includes a second TSV coupled to the first TSV and a second substantially helical conductor disposed around the second TSV. The first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.Type: GrantFiled: May 2, 2017Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventor: Kyle K. Kirby
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Patent number: 10121740Abstract: A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.Type: GrantFiled: January 16, 2017Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Daniel C Edelstein, Chih-Chao Yang
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Patent number: 10121741Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.Type: GrantFiled: February 24, 2017Date of Patent: November 6, 2018Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Patent number: 10121742Abstract: A method for forming packaged semiconductor devices comprises providing a first conductive frame structure. The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first sub-assembly, wherein the second conductive frame structure comprises a plurality of interconnected conductive connective structures. The method includes encapsulating the first sub-assembly with an encapsulating layer to provide an encapsulated sub-assembly. The method includes removing joined conductive portions of the first conductive frame structure to form a plurality of conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly. The method includes forming a conductive layer on the conductive flank surfaces. The method includes separating the encapsulated sub-assembly to provide the packaged semiconductor devices each having portions of the conductive flank surfaces covered by the conductive layer.Type: GrantFiled: March 15, 2017Date of Patent: November 6, 2018Assignee: Amkor Technology, Inc.Inventors: Siang Miang Yeo, Mohd Hasrul Bin Zulkifli
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Patent number: 10121743Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.Type: GrantFiled: March 29, 2017Date of Patent: November 6, 2018Assignee: QUALCOMM IncorporatedInventors: Pratyush Kamal, Kambiz Samadi, Jing Xie, Yang Du
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Patent number: 10121744Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.Type: GrantFiled: April 19, 2017Date of Patent: November 6, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yunjung Choi, Kivin Im, Dongbok Lee, Inseak Hwang
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Patent number: 10121745Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance.Type: GrantFiled: June 13, 2017Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventor: Zengtao T. Liu
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Patent number: 10121746Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.Type: GrantFiled: November 16, 2017Date of Patent: November 6, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kazuya Kobayashi, Yuichi Sano, Daisuke Tokuda, Hiroaki Tokuya
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Patent number: 10121747Abstract: According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.Type: GrantFiled: January 22, 2015Date of Patent: November 6, 2018Assignee: Renesas Electronics CorporationInventor: Keisuke Nakayama
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Patent number: 10121748Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.Type: GrantFiled: June 29, 2017Date of Patent: November 6, 2018Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Hiroshi Kudo, Takamasa Takano
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Patent number: 10121749Abstract: A method of fabricating a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.Type: GrantFiled: April 3, 2017Date of Patent: November 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
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Patent number: 10121750Abstract: A sensor chip package assembly and an electronic device having the sensor chip package assembly are disclosed, where the sensor chip package assembly includes: a metal substrate (100) which has a bonding pad region (11) and a placement region (12), the bonding pad region having a plurality of metal bonding pads (13); a sensor chip (200) which is located on an upper surface of the metal substrate, and the sensor chip having a plurality of sensor chip bonding pads (21); an electrical connection assembly (300) which electrically connects a metal bonding pad and a sensor chip bonding pad; and a packaging material cover (400) which covers the metal substrate, the sensor chip and the electrical connection assembly, where any two adjacent metal bonding pads are spaced in an insulated manner by the packaging material cover.Type: GrantFiled: June 1, 2017Date of Patent: November 6, 2018Assignee: Shenzhen Goodix Technology Co., Ltd.Inventors: Yuping Liu, Wei Long
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Patent number: 10121751Abstract: A semiconductor module comprises an integrated circuit device, the IC device embedded in a compound material, wherein the compound material at least partially extends lateral to the IC device. The semiconductor module further comprises interconnect structures arranged lateral to the IC device to provide at least one external electrical contact; a patch antenna structure integrated in the semiconductor module and electrically connected to the IC device and a layer interfacing the IC device and the compound, wherein the layer comprises first and second planar metal structures coupled to the IC device, wherein the first planar metal structure is electrically connected to the IC device and the interconnect structures and wherein the second planar metal structure is electrically connected to the IC device and the patch antenna structure.Type: GrantFiled: April 25, 2016Date of Patent: November 6, 2018Assignee: Infineon Technologies AGInventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
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Patent number: 10121752Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.Type: GrantFiled: February 25, 2015Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Srinivas V. Pietambaram, Kyu Oh Lee
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Patent number: 10121753Abstract: A solder pad includes a surface. A tin layer is arranged on the surface. At least one out of a bismuth layer, an antimony layer and a nickel layer is arranged on the tin layer.Type: GrantFiled: July 6, 2017Date of Patent: November 6, 2018Assignee: Infineon Technologies AGInventors: Jens Oetjen, Stefan Macheiner