Abstract: A TFT substrate and a manufacturing method thereof are provided. The TFT substrate includes a plurality of vias formed in a second insulation layer that is formed on a second metal layer that forms peripheral signal wiring traces of the TFT substrate so as to line up in an extension direction of each of the peripheral signal wiring traces and a third metal layer that is formed on the second insulation layer at a location corresponding to each of the peripheral signal wiring traces such that the third metal layer is connected, through the vias, with each of the peripheral signal wiring traces to thereby reduce the electrical resistance of each of the peripheral signal wiring traces and thus lowering down power consumption of control ICs and improving capability of the TFT substrate for resisting electrostatic discharge.

Abstract: A semiconductor structure is disclosed. The semiconductor substrate includes: a front surface and a back surface; and a heterogeneous radiation-sensing region in the semiconductor substrate, the heterogeneous radiation-sensing region including a top surface, a bottom surface and sidewalls, the top surface being adjacent to the front surface of the semiconductor substrate, the sidewalls being perpendicular to the front surface of the semiconductor substrate, and the bottom surface being parallel to the front surface of the semiconductor substrate. An associated manufacturing method is also disclosed.

Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a plurality of isolation structures disposed between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures electrically isolate individual photodiodes in the plurality of photodiodes. A plurality of transistors are disposed proximate to the plurality of photodiodes and include a reset transistor, an amplifier transistor, and a row select transistor. An active region and a gate electrode of at least one transistor in the plurality of transistors are vertically aligned with an isolation structure in the plurality of isolation structures.

Abstract: Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.

Abstract: A device includes first patterns, second patterns, and a second sample pattern on a semiconductor substrate. The second patterns are horizontally spaced apart at an equal interval from the second sample pattern. The second sample pattern includes first and second sidewall facing each other, a first point on the first sidewall, and a second point on the second sidewall. The second sample pattern and the most adjacent first pattern in relation to the second sample pattern are spaced apart from each other at a first horizontal distance in a direction parallel to a line connecting the first point and the second point. The first horizontal distance is greater than a second horizontal distance in the direction between one second pattern of the second patterns and a most adjacent first pattern in relation to the one second pattern.

Abstract: A backside-illuminated color image sensor with crosstalk-suppressing color filter array includes (a) a silicon layer including an array of photodiodes and (b) a color filter layer on the light-receiving surface of the silicon layer, wherein the color filter layer includes (i) an array of color filters cooperating with the array of photodiodes to form a respective array of color pixels and (ii) a light barrier grid disposed between the color filters to suppress transmission of light between adjacent ones of the color filters. The light barrier is spatially non-uniform across the color filter layer to account for variation of chief ray angle across the array of color filters.

Abstract: There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members.

Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.

Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.

Abstract: To detect light from light pulses at the operating wavelength of a light source in a lidar system, a thin-film notch filter is directly deposited on a photodetector or a lens via vacuum deposition or monolithic epoxy. The thin-film notch filter may include an anti-reflective coating such as a pattern-coated dichroic filter having an optical transmission of 90% or greater at in-band wavelengths and less than 5% at out-of-band wavelengths. To deposit the filter onto the photodetector without disrupting electronic connections between the photodetector and an application-specific integrated circuit, the area surrounding the electrodes on the photodetector is kept open using photolithography.

Abstract: Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device.

Abstract: A photo detector can include: a light emitting device configured to emit light; a driving circuit configured to drive the light emitting device; a photo-electric conversion circuit configured to generate an optical current signal according to an optical signal; an isolation circuit configured to transmit the optical current signal in an isolated manner; an ambient light filter configured to filter a current component of the optical current signal corresponding to an ambient light, and to generate a clean optical current signal; a current amplification circuit configured to amplify the clean optical current signal, and to generate an amplified optical current signal; (vii) an analog-to-digital converter configured to convert the amplified optical current signal to a digital signal; and a control circuit configured to output an optical detection signal according to the digital signal.

Abstract: An imaging device includes a plurality of pixels. Each of the pixels includes a photoelectric conversion unit provided in a first semiconductor region of a first conductivity type, a transfer transistor including a second semiconductor region of a second conductivity type to which charge generated in the photoelectric conversion unit is transferred, a third semiconductor region of the first conductivity type provided in a portion deeper than the second semiconductor region and having a higher impurity concentration than the first semiconductor region, and a counter doped region provided around the second semiconductor region. A part of the third semiconductor region and a part the counter doped region are overlapped with a gate electrode of the transfer transistor in a plan view. An overlap of the counter doped region with respect to the gate electrode is larger than an overlap of the third semiconductor region with respect to the gate electrode.

Abstract: A flat panel detector is provided having a circular active area. The flat panel detector is built using complementary metal-oxide-semiconductor (CMOS) tiles. In one implementation, the flat panel detector having a circular active area can be used as a replacement for a conventional image intensifier, including an image intensifier used in a fluoroscopy system.

Abstract: A digital quantum dot radiographic detection system described herein includes: a scintillation subsystem 202 and a semiconductor light detection subsystem 200, 200? (including a plurality of quantum dot image sensors 200a, 200b). In a first preferred digital quantum dot radiographic detection system, the plurality of quantum dot image sensors 200 is in substantially direct contact with the scintillation subsystem 202. In a second preferred digital quantum dot radiographic detection system, the scintillation subsystem has a plurality of discrete scintillation packets 212a, 212b, at least one of the discrete scintillation packets communicating with at least one of the quantum dot image sensors. The quantum dot image sensors 200 may be associated with semiconductor substrate 210 made from materials such as silicon (and variations thereof) or graphene.

Abstract: Disclosed herein is a phototransistor (PT) comprising an emitter, a collector and a floating base; wherein the floating base, a p-n junction between the emitter and base (E-B junction) and a p-n junction between the base and the collector (B-C junction) are collectively in direct physical contact only with and completely encapsulated only by the emitter, the collector, and a section of a dielectric. Under an operating condition of the PT, a DC current density averaged over the E-B junction or a DC current density averaged over the B-C junction may be at least 100 times of a DC current density averaged over an opto-electronically active region of the PT. A sum of a capacitance of the E-B junction and a capacitance of the B-C junction may be less than 1 fF.

Abstract: A method of processing an image sensor system, comprising steps of placing a first cover member on top of an image sensor; coating the image sensor and the first cover member with a dark coating agent; removing the first cover member from the image sensor; placing a second cover member on top of the image sensor; affixing the image sensor on to a permanent mount to form an electrical coupling between the image sensor and the permanent mount; removing the second cover member from the image sensor; wherein the first cover member completely covers a top portion of the image sensor; and wherein the second cover member includes an internal rib configured to form a contact seal with the image sensor.

Abstract: Presented herein is a device including an image sensor having a plurality of pixels disposed in a substrate and configured to sense light through a back side of the substrate and an RDL disposed on a front side of the substrate and having a plurality of conductive elements disposed in one or more dielectric layers. A sensor shield is disposed over the back side of the substrate and extending over the image sensor. At least one via contacts the sensor shield and extends from the sensor shield through at least a portion of the RDL and contacts at least one of the plurality of conductive elements.

Abstract: A light-emitting device may include an active layer. The light-emitting device may include a first semiconductor layer of a first conductivity type. The first semiconductor layer may be in physical contact with the active layer. The light-emitting device may also include a second semiconductor layer of a second conductivity type. The second semiconductor layer may be in physical contact with the active layer and opposite the first conductive layer. The light-emitting device may further include a first electrode in physical contact with a first side of the first semiconductor layer. The light-emitting device may additionally include a second electrode in physical contact with a second side of the first semiconductor layer. The second side of the first semiconductor layer may be different from the first side of the first semiconductor layer. The light-emitting device may also include a third electrode in physical contact with the second semiconductor layer.

Abstract: An LED chip for use in an LED chip array forming a continuous array of LEDs. The LED chip comprises an array of LEDs on a substrate. LEDs in a row of the array are longitudinally offset from corresponding LEDs in another row. Adjacent LEDs in each row of the array are separated by a longitudinal pitch. At least part of an end face of the substrate is angled with respect to a transverse axis of the LED chip such that the LED chip is positionable adjacent another LED chip to maintain the longitudinal pitch between adjacent LEDs on different chips.

Abstract: Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random-access memory (STT-MRAM) systems, and methods of fabrication.

Abstract: Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.

Abstract: Provided is a display device including first to third pixels and first to fourth cap layers. The first cap layer is located over and overlaps with the first to third light-emitting elements and extends from the first pixel to the third pixel through the second pixel. The second and third cap layers are located over the first cap layer and respectively overlap with the second and third light-emitting elements. The fourth cap layer is located over the first to fourth cap layers. The first to third pixels are arranged in this order. The first to third light-emitting elements are configured so that an emission wavelength of the second light-emitting element is shorter than an emission wavelength of the third light-emitting element and longer than an emission wavelength of the first light-emitting element. A thickness of the third cap layer is larger than a thickness of the second cap layer.

Abstract: The invention provides an OLED display panel and manufacturing method thereof, by disposing a red shielding color-resist block on the IGZO TFT to completely cover the active layer, able to reduce the influence of the high energy blue light incident from the top of the IGZO TFT on the active layer so as to prevent the leakage current and to ensure the TFT characteristics to maintain normal operation of the IGZO TFT. Moreover, the red shielding color-resist block covering the active layer only blocks the high-energy blue light influencing the active layer of the IGZO TFT while allows light of other bands to pass through; thus, the aperture ratio of the OLED display panel is not affected.

Abstract: An electronic device may have a display. The display may have an active region in which display pixels are used to display images. The display may have one or more openings and may be mounted in a housing associated with the electronic device. An electronic component may be mounted in alignment with the openings in the display. The electronic component may include a camera, a light sensor, a light-based proximity sensor, status indicator lights, a light-based touch sensor array, a secondary display that has display pixels that may be viewed through the openings, antenna structures, a speaker, a microphone, or other acoustic, electromagnetic, or light-based component. One or more openings in the display may form a window through which a user of the device may view an external object. Display pixels in the window region may be used in forming a heads-up display.

Abstract: A touch display device includes an organic light emitting diode display panel and a touch panel. The organic light emitting diode display panel includes an organic light emitting diode array having a plurality of pixel regions and a non-pixel region surrounding the pixel regions. Each of the pixel regions has an organic light emitting diode unit thereon, and a metal wire is located in the non-pixel region. The touch panel includes a transparent substrate, a sensing electrode layer and a light-shading pattern. The sensing electrode layer and the light-shading pattern are disposed on the transparent substrate, and overlapped each other. An orthogonal projection of the light-shading pattern onto the organic light emitting diode array is in the non-pixel region, and overlap the metal wire.

Abstract: An organic light-emitting diode includes at least two segments arranged adjacent to one another, a scattering layer that at least partially scatters the light generated in each of the segments, and at least one separating region located in the scattering layer, wherein the separating region has a transmittance for light generated in the segments of at most 20%, the separating region, when viewed in a plan view, is arranged in a transitional region between adjacent segments such that within the scattering layer propagation of light between the segments is suppressed, the segments include organic layer sequences each located between a first electrode and a second electrode, the segments are distant from one another in a direction parallel to the main directions of extension, and the scattering layer directly adjoins the first electrode which is light-transmitting and directly adjoins a transparent layer on a side remote from the first electrode.

Abstract: The present disclosure discloses a flexible base substrate, a display substrate and methods of manufacturing the same, and a display device. A groove is provided in a surface of the flexible base substrate, the surface of the flexible base substrate having the groove is provided with a water-oxygen barrier film, and the thickness of the water-oxygen barrier film is smaller than the depth of the groove.

Abstract: To provide a display device including a pixel electrode formed on an insulating surface; a bank covering an end portion of the pixel electrode and having an opening formed therein in which the upper surface of the pixel electrode is exposed; an organic layer containing a light emitting layer and formed covering the opening; and an opposed electrode formed on the organic layer and the bank. The bank has a first layer formed on an end portion of the pixel electrode and the insulating surface, and a second layer formed on the first layer. The refractive index of the material forming the first layer is less than the refractive index of the material forming the second layer.

Abstract: The display device including a pixel circuit has a first line, a transistor, a light emitting element, and a second line. The transistor is located between the second line and an electrode of the light emitting element. Either the first line or the second line is wired in a region that overlaps a light emitting region of the light emitting element in a lamination direction of layers. The second line intersects the first line outside of the light emitting region and overlaps a non-light emitting region of the light emitting element.

Abstract: Disclosed is an organic light emitting device, (OLED) comprising a substrate on which a driving transistor is formed, a bank formed on the substrate providing a boundary for a pixel region, a first electrode formed on the substrate and electrically connected with the driving transistor, the first electrode comprising a first and second cross sectional area both oriented in a direction perpendicular to a vertical direction of the substrate, the first area adjacent to the bank, the second area surrounded by the first area, an organic layer formed on the first electrode within the boundary provided by the bank, and a second electrode formed on the organic layer, wherein during operation of the OLED a first electric field between the first area of the first electrode and the second electrode is greater than a second electric field between the second area of the first electrode and the second electrode.

Abstract: The present disclosure relates to a display device including a light emitting element display. The present disclosure suggests a flat panel display comprising: a substrate; a driving element disposed on a first surface of the substrate; an organic light emitting diode disposed on a second surface of the substrate; a through-hole penetrating the substrate from the front surface to the rear surface; and a connecting electrode filling the through-hole for linking the driving element to the organic light emitting diode.

Abstract: A display device including a TFT substrate and a display layer is provided. The TFT substrate includes a substrate, a gate layer, a semiconductor layer, a gate dielectric layer, a first electrode layer, a first passivation layer, a second passivation layer, and a second electrode layer. A via penetrates the first passivation layer and the second passivation layer to expose a portion of the first electrode layer, and the via has a sidewall. The second electrode layer is electrically connected to the first electrode layer through the via, the first passivation layer has a first edge on the sidewall of the via, the second passivation layer has a second edge on the sidewall of the via, and the first edge and the second edge are separated by a distance in the range of 500-2000 ?.

Abstract: The disclosure discloses an active matrix organic light emitting diode panel and a method for manufacturing the same. The active matrix organic light emitting diode panel includes: a substrate, an organic film formed on the substrate, and a plurality of red, green and blue organic light emitting diodes formed on the organic film. A first recess or a first protrusion is formed in the organic film in a region corresponding to the blue organic light emitting diode. The blue organic light emitting diode is formed on the first recess or first protrusion, and a contact area of the blue organic light emitting diode with the organic film is S r ? ? 0 Lifetime b ? ? 0 Lifetime r ? ? 0 n times as great as a contact area of the red organic light emitting film with the organic film, wherein n is a value ranging from 1.4 to 1.6.

Abstract: There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

Abstract: A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a substrate including a separation area and a plurality of pixel formed over the substrate. The separation area is formed between adjacent pixels, and a plurality of through holes are respectively defined by a plurality of surrounding inner surfaces of the separation area, and wherein each of the inner surfaces passes through the substrate. The display device also includes an encapsulation layer formed over the substrate and covering the inner surfaces of the separation area.

Abstract: A display may have an array of pixels formed from thin-film transistor circuitry. The thin-film transistor circuitry may include thin-film layers of dielectric, semiconductor, and metal on a dielectric substrate. Test structures may be formed around the periphery of the substrate to facilitate testing of the thin-film circuitry during manufacturing. The test structures may include test pads that are coupled to the thin-film circuitry by test lines extending from the thin-film circuitry. Following testing, the outermost portions of the display and the test pads on these display portions may be removed by cutting the substrate along a substrate cut line. The test lines may be formed from parallel lines that are shorted together, semiconductor layers, multiple layers of conductive material, and other structures that resist corrosion along the cut line.

Abstract: A display apparatus includes a substrate; a plurality of display units on the substrate, each including a thin film transistor including at least one inorganic layer, a passivation layer on the thin film transistor, and a display device electrically connected to the thin film transistor; and a plurality of encapsulation layers respectively encapsulating the plurality of display units. The substrate includes a plurality of islands spaced apart, a plurality of connection units connecting the plurality of islands, and a plurality of through holes penetrating through the substrate between the plurality of connection units. The plurality of display units are on the plurality of islands, respectively. The at least one inorganic layer and the passivation layer extend on the plurality of connection units. The passivation layer includes a trench exposing the at least one inorganic layer. The encapsulation layer contacts the at least one inorganic layer exposed via the trench.

Abstract: An inductor layout comprising a first inductor and a second inductor. The first and second inductors are electrically and magnetically independent inductors concentrically arranged on an integrated circuit. At least one of the first and second inductors is a multi-loop inductor with a first axis of symmetry.

Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

Abstract: A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

Abstract: Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.

Abstract: A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract: Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper channel material layer on the substrate, and a gate electrode that covers the upper channel material layer and the energy barrier forming layer. The gate electrode includes a side gate electrode portion that faces a side surface of the energy barrier forming layer. The side gate electrode may be configured to cause an electric field to be applied directly on the energy barrier forming layer via the side surface of the energy barrier forming layer, thereby enabling adjustment of the energy barrier between the energy barrier forming layer and the upper channel material layer. The electronic device may further include a lower channel material layer that is provided on the substrate and does not contact the upper channel material layer.

Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.