Abstract: A thermally-assisted magnetic recording head includes a main pole, a plasmon generator and a heat sink. The main pole includes a first narrow portion and a first wide portion. The plasmon generator includes a second narrow portion and a second wide portion. The first narrow portion has a first side surface and a second side surface. The second narrow portion has a third side surface and a fourth side surface. The heat sink includes a first portion adjacent to the first side surface and the third side surface, and a second portion adjacent to the second side surface and the fourth side surface.

Abstract: A microactuator for a suspension is described. The microactuator includes a multi-layer PZT device having a first face and an opposite second face. Each layer of the multi-layer PZT device is configured to operate in its d15 mode when actuated by an actuation voltage. The layers are configured as a stack such that each layer is configured to act in the same direction when actuated such that the first face moves in shear relative to the second face.

Abstract: A flexure chain blank sheet includes a plurality of frame units. Each of the frame units includes a frame portion, and a plurality of flexure elements arranged within the frame portion. The frame portion includes lengthwise frames extending in a longitudinal direction of the flexure elements, and lateral frames extending in a width direction of the flexure elements. A slit that extends along the lateral frames, a connection portion, and recesses are formed between adjacent frame units. An opening width of the recesses is greater than an opening width of the slit. The connection portion includes a portion-to-be-cut which is to be cut by a cutter. The recesses allow insertion of the cutter.

Abstract: Provided is a magnetic tape device in which a magnetic tape transportation speed is equal to or lower than 18 m/sec, Ra measured regarding a surface of a magnetic layer of a magnetic tape is equal to or smaller than 2.0 nm, a C-H derived C concentration calculated from a C-H peak area ratio of C1s spectra obtained by X-ray photoelectron spectroscopic analysis performed on the surface of the magnetic layer at a photoelectron take-off angle of 10 degrees is 45 to 65 atom %, and ?SFD (=SFD25° C.?SFD?190° C.) in a longitudinal direction of the magnetic tape is equal to or smaller than 0.50, with the SFD25° C. being SFD measured in a longitudinal direction of the magnetic tape at a temperature of 25° C., and the SFD?190° C. being SFD measured at a temperature of ?190° C.

Abstract: A method of making magnetic graphene comprising transferring or growing a graphene film on a substrate, functionalizing the graphene film, hydrogenating the graphene film and forming fully hydrogenated graphene, manipulating the extent of the hydrogen content, and forming areas of magnetic graphene and non-magnetic graphene. A ferromagnetic graphene film comprising film that has a thickness of less than two atom layers thick.

Abstract: A carbon film forming method, that introduces a raw material gas including carbon into a film forming chamber, ionizes the gas by using an ion source, accelerates the ionized gas, and radiates the ionized gas to a surface of a substrate to form a carbon film on the surface of the substrate, includes forming the carbon film while rotating a first magnet, which is provided on the opposite side of the substrate across a region in which the raw material gas is ionized so as to be eccentric and/or inclined with respect to a central axis connecting the center of the ion source and a position corresponding to the center of the substrate held by the holder, in a circumferential direction.

Abstract: A method of forming a near field transducer (NFT) layer, the method including depositing a film of a primary element, the film having a film thickness and a film expanse; and implanting at least one secondary element into the primary element, wherein the NFT layer includes the film of the primary element doped with the at least one secondary element.

Abstract: According to one embodiment, physical position information on errors on a recording medium is acquired, physical position relationship between the errors on the recording medium is calculated based on the position information, and a failure mode related to the errors is determined based on the position relationship.

Abstract: An optical medium reproduction apparatus for optically reproducing an optical medium, including: a detection unit for splitting a cross section of a beam returned from the optical medium into a plurality of regions and for forming respective detection signals; a multiple input adaptive equalizer having a plurality of adaptive equalizer units, wherein the respective detection signals are inputted into the adaptive equalizer units, and the outputs of the adaptive equalizer units are computed to form equalization signals; a binarization unit for binarizing the equalization signals to provide binary data; and an equalization error computing unit for determining an equalization error from equalization target signals provided based on the binary data from the binarization unit and the equalization signals, and providing the adaptive equalizer units with the equalization error as control signals for adaptive equalization.

Abstract: A playback device includes a playback controller that sets a scene with a higher level of importance at a lower playback speed and sets a scene with a lower level of importance at a higher playback speed based on a level of importance of each scene of video data, and an image data processor that converts the video data into a playback speed set by the playback controller for each scene, wherein the playback controller plays back the video data within a preset playback time. Further, the playback method plays back video data within a preset playback time by playing back a scene with a higher level of importance at a lower playback speed and playing back a scene with a lower level of importance at a higher playback speed based on a level of importance of each scene.

Abstract: A method for producing an audio-visual slideshow for a video sequence having an audio soundtrack and a corresponding video track including a time sequence of image frames, comprising: segmenting the audio soundtrack into a plurality of audio segments; subdividing the audio segments into a sequence of audio frames; determining a corresponding audio classification for each audio frame; automatically selecting a subset of the audio segments responsive to the audio classification for the corresponding audio frames; for each of the selected audio segments automatically analyzing the corresponding image frames to select one or more key image frames; merging the selected audio segments to form an audio summary; forming an audio-visual slideshow by combining the selected key frames with the audio summary, wherein the selected key frames are displayed synchronously with their corresponding audio segment; and storing the audio-visual slideshow in a processor-accessible storage memory.

Abstract: The present invention provides a method and a system for overlaying an image in a video stream. The method comprising steps of: acquiring an image element signature including at least one image element from the video stream; determining whether the image element signature matches an image to be overlaid; and overlaying the image when the image element signature is determined to match the image to be overlaid.

Abstract: The present invention concerns a synchronization method for synchronizing at least two systems for rendering multimedia streams, the method comprising: the detection of a pulse of a same signal of fixed frequency by each rendering system and by a main clock system, the generation of a main clock signal and a dependent clock signal, the estimating of a main local date of reception of the subsequent pulse and a dependent local date of reception of the subsequent pulse, the calculation of the difference between the main local date and the dependent local date, the iteration of the preceding steps until a first condition concerning the calculated differences is met, the receiving of a multimedia stream, by each of the rendering systems, the sending of a rendering date, and the calculation of an effective date for the rendering of the multimedia stream.

Abstract: To allow a better coordination between an image creation artist such as a movie director of photography and the final viewer, via a receiving-side display and its built-in image processing, a method of adding image defining information to an input image signal (I) comprises receiving descriptive data (D) that includes at least luminance value information on the one hand, and a regime descriptor (rd) on the other hand; and encoding into an output description data signal (DDO), relatable to an output image signal (O) based upon an input image signal (I), of the descriptive data (D) in a technical format standardized to be intended for use by a receiving-side display to control its image processing for changing the color properties of its rendered images.

Abstract: To allow a better coordination between an image creation artist such as a movie director of photography and the final viewer, via a receiving-side display and its built-in image processing, a method of adding image defining information to an input image signal (I) comprises showing the input image (I) to a human operator; receiving via a user interface (303, 308) descriptive data (D) from the human operator, the descriptive data (D) including at least luminance value information on the one hand, and a regime descriptor (rd) on the other hand; and encoding into an output description data signal (DDO), relatable to an output image signal (O) based upon the input image signal (I), of the descriptive data (D) in a technical format standardized to be intended for use by a receiving-side display to control its image processing for changing the color properties of its rendered images.

Abstract: An extraction device includes a processor that executes a procedure. The procedure includes: extracting a point as an end of the turn at bat from footage of a baseball game in which a point representing a start of a turn at bat has been associated with information indicating respective specified outcomes of the turn at bat, the extracted point being subsequent to a cut including a final pitch scene in the turn at bat and being prior to which cuts have transitioned a number of times, the number of times being determined according to an outcome of the turn at bat.

Abstract: An apparatus comprises a spindle to rotate a magnetic recording medium and a magnetic field generator to expose a track of the medium to a DC magnetic field. The magnetic field generator is configured to saturate the track during an erase mode and reverse the DC magnetic field impinging the track during a writing mode. A laser arrangement heats the track during the erase mode and, during the writing mode, heats the track while the track is exposed to the reversed DC magnetic field so as to write a magnetic pattern thereon. A reader reads the magnetic pattern and generates a read signal. A processor is coupled to the reader and configured to determine an anisotropy parameter using the read signal. The apparatus can further comprise a Kerr sensor that generates a Kerr signal using the magnetic pattern.

Abstract: Aspects of this disclosure are directed to methods, apparatuses and approaches involving the use of a moisture absorbing material (e.g., desiccant) to control moisture. As may be implemented consistent with one or more embodiments, moisture is removed from an environmental control module that includes a desiccant material contained within a package. Liquid is deposited inside the package and sealed with the desiccant in the package.

Abstract: A data storage device involves inner surfaces of sidewalls of a second cover overlapping with and adhesively bonded with the outer surfaces of sidewalls of an enclosure base having an uppermost top surface, where the second cover or an underlying first cover are removably adhered to the uppermost top surface of the base. The removable adhesive bond may comprise a pressure-sensitive adhesive, which can provide for reworkability during the manufacturing and testing process. The second cover-to-base sidewall bond may form a hermetic seal between the second cover and the base. Hence, a thinner base sidewall adjacent to the recording disks is enabled, leaving more space available for larger-diameter recording disks within a standard form factor, hermetically-sealed storage device, which may be filled with a lighter-than-air gas.

Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

Abstract: A semiconductor memory device includes a peripheral circuit including first and second circuit blocks that are respectively disposed in second and third regions adjacent to each other in a first direction with a first region interposed therebetween, first power lines disposed in a first metal layer and connected to the first unit circuit block, second power lines disposed in the first metal layer and connected to the second unit circuit block, and bridge power lines disposed in a second metal layer in the first region and extending in a second direction intersecting with the first direction. The first power lines extend from the second region to the first region and are meshed with the bridge power lines. The second power lines extend from the third region to the first region and are meshed the bridge power lines.

Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: According to one embodiment, a memory arrangement is described a memory including a memory cell and a sense amplifier coupled to the memory cell having a node whose potential depends on the difference between a current through the memory cell and a reference current, a detection circuit configured to generate a signal representing whether the current through the memory cell is above or below the reference current based on the potential of the node and a limitation circuit configured to receive the signal and to limit the change of the potential of the node caused by the difference between the current through the memory cell and the reference current in response to the signal.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: An apparatus includes a memory and a circuit. The memory may be configured to store a plurality of context variables. The circuit may be configured to (i) generate a select signal that identifies a prediction of a plurality of next states in each of a plurality of next cycles that follow a current cycle of an arithmetic decode of an input signal, (ii) generate a prefetch signal in the current cycle in response to the select signal, (iii) prefetch in parallel from the memory two or more of the context variables suitable to use in the next states in two or more of the next cycles based on the prefetch signal and (iv) generate an output signal by decoding the input signal based on the two or more of the context variables.

Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A plurality of read lines are in a read line layer, and a plurality of write lines are in a write line layer. A plurality of spin accumulation lines are in a spin accumulation line layer disposed between a read line layer and a write line layer. Spin accumulation lines may horizontally cross read lines and write lines. A plurality of vertical magnetoresistive random access memory (MRAM) cells may include polarizers and magnetic tunnel junctions. A vertical MRAM cell may include a polarizer coupled between a spin accumulation line and a write line. A vertical MRAM cell may further include a magnetic tunnel junction coupled between a spin accumulation line and a read line, such that the magnetic tunnel junction and the polarizer are vertically aligned.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

Abstract: A skyrmion generation method capable of reducing power consumption in generating skyrmions is provided. In the skyrmion generation method, an electric field is applied to an insulating magnetic body having a chiral crystal structure locally using an electric field generation unit while a magnetic field is applied from a magnetic field generation unit to the magnetic body. As a result, a skyrmion is generated in the magnetic body. The magnetic body preferably has a thin film shape with a thickness in a range of 2 to 300 nm at least partially, and the magnetic field generation unit preferably applies the magnetic field to a surface of the magnetic body substantially perpendicularly.

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract: A semiconductor integrated circuit is described. A. transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about ½ of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.

Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: A data reception chip coupled to an external memory comprising a first input-output pin to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage and includes a plurality of first resistors and a first selection unit. The first resistors are connected in series with one another and dividing a first operation voltage to generate a plurality of first divided voltages. The first selection unit selects one of the first divided voltages as the first reference voltage according to a first control signal.

Abstract: A semiconductor memory is disclosed that includes a first data line, a first coupling line, and a second coupling line. The first coupling line is configured to capacitively couple the first coupling line with the first data line. The second coupling line is configured to capacitively couple the second coupling line with the first data line. The first data line and the first coupling line are formed in a first conductive layer, and the second coupling line is formed in a second conductive layer that is different from the first conductive layer.

Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Abstract: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.

Abstract: A resistive processing unit (RPU) circuit for use in a neural network application includes at least one floating gate storage device, the floating gate storage device including a floating gate, a control gate and an inject/erase gate. The RPU circuit further includes a feedback circuit connected with the floating gate storage device. The feedback circuit is configured to maintain a substantially constant floating gate potential of the floating gate storage device during an update mode of operation of the RPU circuit, and is disabled during a readout mode of operation of the RPU circuit.

Abstract: Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.

Abstract: An apparatus includes a first plane of memory cells including an associated first buffer, a second plane of memory cells including an associated second buffer. The apparatus also includes a controller configured to transfer data corresponding to a first memory state the first buffer and transfer data corresponding to a second memory state to the second buffer. The apparatus also includes state machine configured to apply program pulses to the first and second planes of memory cells. The apparatus also includes read/write circuitry configured to independently confirm that the first and second planes of memory cells have reached the first and second memory states.

Abstract: Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.

Abstract: A method for controlling a nonvolatile memory device includes requesting a plurality of first sampling values from the nonvolatile memory device, each of the first sampling values representing the number of memory cells having a threshold voltage between a first sampling read voltage and a second sampling read voltage. The first sampling values are processed through a non-linear filtering operation to estimate the number of memory cells having the threshold voltage between the first sampling read voltage and the second sampling read voltage.

Abstract: A nonvolatile memory device includes a memory cell array that stores data, and control logic. The control logic is configured to control a read operation, a program operation, or an erase operation on the data. The control logic is configured to detect a first power noise based on one of voltage sources to be provided to the memory cell array and a first reference voltage and detect a second power noise based on the one voltage source of the voltage sources and each of the first reference voltage and a second reference voltage. The control logic is configured to determine whether to perform at least one of an operation period of the read operation, an operation period of the program operation, or an operation period of the erase operation, based on whether at least one of the first and second power noises is detected.

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

Abstract: A memory system is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.