Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.

Abstract: Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions. The first RESURF region extends from a source end toward a drain end of the LDMOS device. The first RESURF region is adjacent to a forms a metallurgical junction with the drift region. The second RESURF layer extends from the drain end toward the source end of the LDMOS device. The second RESURF layer has an end that is longitudinally between the body contact and the source end of the first RESURF layer. A distance between the end of the second RESURF layer and the body contact is greater than a vertical distance between the end of the second RESURF layer and the body contact. A maximum electric field between the second RESURF layer and the body contact can be advantageously reduced with this geometry.

Abstract: A semiconductor structure and a method a method of forming a vertical FET (Field-Effect Transistor), includes growing a bottom source-drain layer of a second type on a substrate of a first type, growing a channel layer on the bottom source-drain layer, forming a first fin from the channel layer with mask on top of the first fin. A width of the mask is wider than a final first fin width.

Abstract: A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Abstract: A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate.

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

Abstract: A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to ?60° C., preferably with a dew point of lower than or equal to ?75° C. without exposing the first substrate after the heat treatment to the air; and then, the first substrate is bonded to a second substrate that serves as an opposite substrate.

Abstract: The present disclosure proposes a dual-gate thin film transistor and manufacturing method thereof and an array substrate. A manufacturing method includes: forming a first gate electrode, a gate insulating layer, a semiconductor layer, and an etch stop layer on a first substrate sequentially; forming a drain electrode, an independent electrode, and a source electrode on the exposed semiconductor layer; forming an insulating passivation layer on surfaces of the exposed etch stop layer, the drain electrode, the source electrode, and the independent electrode; and forming a second gate electrode on the insulating passivation layer in an area corresponding to the first gate electrode. The present disclosure can resolve the leakage current problem caused by the effective channel length between the source electrode and the drain electrode to improve the electrical properties of the dual-gate thin film transistor and improve its stability. The present disclosure can simplifies processes and reduce cost.

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

Abstract: The present invention provides a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor according to the present invention is such that by forming a first photoresist layer on an active layer and using a mask associated with the active layer to pattern the first photoresist layer so as to form the first photoresist pattern, the first photoresist pattern so formed provides protection of the active layer against corrosion caused by acidic etchant solution in the subsequently conducted etching operation of source and drain electrodes so as to function as an etching stopper layer and further, a major portion of the first photoresist pattern can be removed in a photolithographic process of the source and drain electrodes so that only a minor portion is left in the finally-formed thin-film transistor and does not affect the properties of the thin-film transistor.

Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Abstract: In an example, a memory cell may have an access gate, a control gate coupled to the access gate, a first dielectric stack below an upper surface of a semiconductor, above the access gate, and between a first portion of the control gate and the semiconductor, and a second dielectric stack below the access gate and the first dielectric stack and between a second portion of the control gate and the semiconductor. Each of the first and second dielectric stacks may store a charge.

Abstract: A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is formed between the pull up electrode and the substrate. A movable gate has a first position and a second position. The movable gate is located in the gap between the pull up electrode and the substrate. The movable gate is in contact with the pull up electrode when the movable gate is in a first position and is in contact with the oxide to form a gate region when the movable gate is in the second position. The movable gate, in conjunction with the source region and the drain region and when the movable gate is in the second position, form a transistor that can be utilized as a non-volatile memory element.

Abstract: An apparatus and method that controls the power produced by a string of solar cells, enabling the string to operate at its maximum power point when connected to a bus that operates at an externally controlled voltage. The apparatus and method can also be used to increase or decrease the output power of a string to any desired operating point.

Abstract: A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.

Abstract: A back contact type solar battery which provides a reduced electric power loss, free positioning of a bus bar, and a simple manufacturing process. The solar battery includes: semiconductor substrate; first conductivity type region formed on back surface side located on the opposite side of acceptance surface side of the semiconductor substrate; second conductivity type region formed on the back surface side of the semiconductor substrate; first conductivity type collecting electrode linearly formed on the first conductivity type region; and second conductivity type collecting electrode linearly formed on the second conductivity type region. The first and second conductivity type regions are alternately arranged. Each of the first and second conductivity type collecting electrodes has discontinuous places. The discontinuous places of each conductivity type are substantially aligned on straight line in arrangement direction in which the first and second conductivity type regions are alternately arranged.

Abstract: A multilayered structure may include a doped buffer layer on a transparent conductive oxide layer.

Abstract: A method (200) and deposition zone apparatus (300) for fabricating thin-film optoelectronic devices (100), the method comprising: providing a potassium-nondiffusing substrate (110), forming a back-contact layer (120); forming at least one absorber layer (130) made of an ABC chalcogenide material, adding at least two different alkali metals, and forming at least one front-contact layer (150) wherein one of said at least two different alkali metals is potassium and where, following forming said front-contact layer, in the interval of layers (470) from back-contact layer (120), exclusive, to front-contact layer (150), inclusive, the comprised amounts resulting from adding at least two different alkali metals are, for potassium, in the range of 500 to 10000 ppm and, for the other of said at least two different alkali metals, in the range of 5 to 2000 ppm and at most ½ and at least 1/2000 of the comprised amount of potassium.

Abstract: The present disclosure provides a solar cell array for deployment and use in a space environment, and methods of making same. The array includes a plurality of solar cells having an emissivity coating on the baskside of each, with each coated solar cell being attached to a supporting member.

Abstract: The present invention relates to a glass, in particular a glass for the joining of glass panes for the production of vacuum insulating glasses at processing temperatures ?420° C., to the corresponding composite glass, and to the corresponding glass paste. Moreover, the present invention relates to a vacuum insulating glass produced using the glass paste according to the invention, to the production process thereof, and to the use of the inventive glass and/or composite glass, and glass paste. The glass according to the invention is characterized in that it comprises the following components, in units of mol-%: V2O5 5-58 mol-%, TeO2 40-90 mol-%, and at least one oxide selected from ZnO 38-52 mol-%, or Al2O3 1-25 mol %, or MoO3 1-10 mol-%, or WO3 1-10 mol-%, or a combination thereof.

Abstract: A bifacial solar cell includes a substrate; a first conductive type region having a conductive type different from a conductive type of the substrate; a first insulating layer formed on the first conductive type region; a plurality of first electrodes contacting the first conductive type region through the first insulating layer and extended in a first direction; a plurality of first current collectors extended in a second direction crossing the first direction, wherein the plurality of first current collectors are electrically and physically connected to the plurality of first electrodes; a second conductive type region having a conductive type the same as the conductive type of the substrate, and having an impurity concentration that is higher than an impurity concentration of the substrate; a second insulating layer formed on the second conductive type region; a plurality of second electrodes contacting the second conductive type region through the second insulating layer and extended in the first directio

Abstract: A graphene display is provided. The graphene display includes a first graphene light-emitting unit and a second graphene light-emitting unit which are stacked and overlapped, and a metal shield layer disposed between the first graphene light-emitting unit and the second graphene light-emitting unit. The graphene display is simple in structure, and the colors of the emitted light at the two sides will not change because of the electric field of the gate electrode pattern so as to have more stable color and color reproduction.

Abstract: A method of manufacturing a light emitting element includes: providing a wafer including a substrate and a semiconductor layered body formed at an upper surface of the substrate; irradiating the wafer with laser light by performing first and second patterns of scanning; and separating the substrate from the semiconductor layered body. In the first pattern of scanning, the wafer is irradiated with the laser light outwardly from an inner side of the wafer or inwardly from an outer side of the wafer, so that a region irradiated with the laser light enlarges. In the second pattern of scanning, the wafer is irradiated with the laser light so that the laser light intersects with a circumferential edge of the wafer at a plurality of portions.

Abstract: A light emitting diode including an n-doped InXnGa(1-Xn)N layer and a p-doped InXpGa(1-Xp)N layer, and an active area arranged between the InXnGa(1-Xn)N layer and the InXpGa(1-Xp)N layer including: a first InN layer with a thickness eInN106; a second InN layer with a thickness eInN108; a separating layer arranged between the InN layers and including InXbGa(1-Xb)N and a thickness <3 nm; an InX1Ga(1-X1)N layer arranged between the InXnGa(1-Xn)N layer and the first InN layer; an InX2Ga(1-X2)N layer arranged between the InXpGa(1-Xp)N layer and the second InN layer; wherein the indium compositions Xn, Xp, Xb, X1 and X2 are between 0 and about 0.25, and wherein the thicknesses eInN106 and eInN108 are such that eInN106<eInN108.

Abstract: A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising AlxInyGa1-x-yN layers, at least one GaN based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer. The AlxInyGa1-x-yN layers stacked on the light emitting layer, where 0<x<1, 0?y<1, and 0<x+y<1, and the GaN based layer interposed between two of the AlxInyGa1-x-yN layers, and the ohmic contact layer is disposed on the AlxInyGa1-x-yN layers.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract: A semiconductor light-emitting device includes a first conductive semiconductor layer on a substrate, a superlattice layer including a plurality of first quantum barrier layers and a plurality of first quantum well layers, the plurality of first quantum barrier layers and the plurality of first quantum well layers being alternately stacked on the first conductive semiconductor layer, an active layer on the superlattice layer, and a second conductive semiconductor layer on the active layer, wherein a Si doping concentration of at least one of the plurality of first quantum well layers is equal to or greater than 1.0×1016/cm3 and less than or equal to 1.0×1018/cm3. Thus, the semiconductor light-emitting device may have increased light output and reliability.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; a surrounding exposed region formed on peripheries of the semiconductor stack, exposing a surface of the first semiconductor layer; a conductive layer formed on the second semiconductor layer, including a first conductive region extending toward and contacting the surface of the first semiconductor layer in the surrounding exposed region; an electrode layer formed on the surrounding exposed region, surrounding the semiconductor stack, contacting the conductive layer and including an electrode pad not overlapping the semiconductor stack; an outside insulating layer covering a portion of the conductive layer and the electrode layer, including a first opening exposing the other portion of the conductive layer; a bonding layer covering the outside insulating layer and electrically connecting to the other portion of the conductive layer through the firs

Abstract: An optoelectronic device including semiconductor elements, each semiconductor element resting on a carrier through an aperture formed in a portion at least one first part of which is insulating and covers at least partially the carrier, the height of the aperture being larger than or equal to 100 nm and smaller than or equal to 3000 nm and the ratio of the height to the smallest diameter of the aperture being higher than or equal to 0.5 and lower than or equal to 10.

Abstract: An optoelectronic semiconductor device includes a semiconductor body having a semiconductor region and an active region, wherein the semiconductor region has a covering layer forming a radiation passage surface of the semiconductor body on a side facing away from the active region, the semiconductor region has a current-spreading layer arranged between the covering layer and the active region; the semiconductor device has a contact for the electrical contacting of the semiconductor region; the contact adjoins the current-spreading layer in a terminal area; the contact adjoins the covering layer in a barrier region; and the barrier region runs parallel to the active region and is arranged closer to the active region than the radiation passage surface.

Abstract: LED structures passivated with a III-N passivation material including Al. The III-N passivation material may reduce nonradiative recombination, reducing leakage current of an LED structure, and/or improve luminous efficacy. An LED structure may include III-N materials in a multiple quantum well (MQW) structure, and the III-N passivation material including Al may have a wider bandgap than any of the materials in the MQW structure. The III-N passivation material may be AlN, which can be deposited as a binary compound at low temperatures to maintain quality of the MQW structure. The III-N passivation material can be selectively deposited on a sidewall of at least the MQW structure. The III-N passivation material can be unselectively deposited over an LED structure and then etched to form a III-N spacer along a sidewall of at least the MQW structure. Energy efficient RGB micro(?) LED emissive displays may include passivated LED structures.

Abstract: A light-emitting element includes a semiconductor light-emitting stack including a first semiconductor layer, an active layer, and a second semiconductor layer; a first conductive layer disposed on the second semiconductor layer and electrically connecting the second semiconductor layer; a second conductive layer disposed on the second semiconductor layer and electrically connecting the first semiconductor layer; and a cushion part disposed on the semiconductor light-emitting stack; wherein in a top view, the cushion part is disposed in a center region of the light-emitting element.

Abstract: A package includes a resin molded body, a first lead electrode, a second lead electrode, and a recess portion. The recess portion is provided on a first side of the resin molded body and a light-emitting element is to be provided in the recess portion. The recess portion includes a bottom portion, a top portion, and a side wall. The bottom portion includes an element mount region and a wire connection region. An upper surface of the first lead electrode is exposed from the resin molded body in the element mount region and the element mount region has an outer peripheral shape in accordance with an outer peripheral shape of the light-emitting element when viewed in a height direction. The wire connection region is provided adjacent to the element mount region and is smaller than the element mount region.

Abstract: In one embodiment, a solid cylindrical tablet is pre-formed for a reflective cup containing an LED die, such as a blue LED die. The tablet comprises uniformly-mixed phosphor particles and transparent/translucent particles of a high TC material, such as quartz, in a hardened silicone binder, where the index of refraction of the high TC material is matched to that of the silicone to minimize internal reflection. Tablets can be made virtually identical in composition and size. The bulk of the tablet will be the high TC material. After the tablet is placed in the cup, the LED module is heated, preferably in a vacuum, to melt the silicone so that the mixture flows around the LED die and fills the voids to encapsulate the LED die. The silicone is then cooled to harden.

Abstract: A method for producing a fluorescent material is provided. The method includes preparing fluorescent material particles that contain an alkaline earth metal aluminate having a composition represented by (Sr1?x,Eux)4Al14O25, where x satisfies 0.05?x?0.4, and a part of Sr may be substituted by at least one element selected from the group consisting of Mg, Ca, Ba, and Zn; causing the prepared fluorescent material particles to come into contact with a liquid medium containing water; removing at least a portion of the contacted liquid medium to obtain purified fluorescent material particles; causing a phosphate compound to adhere to surfaces of the purified fluorescent material particles to obtain fluorescent material particles to which the phosphate compound is adhered; and heat treating the fluorescent material particles to which the phosphate compound is adhered at 500° C. to 700° C.

Abstract: The invention provides a lighting unit comprising a light source, configured to generate light source light and a luminescent material, configured to convert at least part of the light source light into luminescent material light, wherein the light source comprises a light emitting diode (LED) and wherein the luminescent material comprises a phosphor comprising M2AX6 doped with tetravalent manganese, wherein M comprises monovalent cations, at least comprising potassium and rubidium, wherein A comprises a tetravalent cation, at least comprising silicon, wherein X comprises a monovalent anion, at least comprising fluorine, and wherein M2AX6 has the hexagonal phase.

Abstract: A packaging method of high color gamut white light quantum dot (QD) light emitting diodes (LEDs). The method includes: a. add an organic solvent to red light QD phosphor powder and blue light QD phosphor powder, respectively; b. perform ultrasonic processing for the solutions; c. prepare a mixed QD solution; d. add mixed packaging glue to the mixed QD solution; e. remove the organic solvent; f. add green light rare earth phosphor powder; g. drip the mixed phosphor glue into an LED stent fixed with ultraviolet chips, and bake and solidify the LED stent to obtain LED beads. The method produces high gamut white light LEDs and greatly improves the color gamut value of LED backlight beads, which reaches above NTSC 92%. With an organic solvent as a connecting bridge, QDs and the packaging glue are mixed uniformly, QD phosphor powder failure resulted from agglomeration is avoided, and quality of high color gamut white light LED beads is significantly improved.

Abstract: A light-emitting apparatus includes a first relay line and a second relay line. The first and second relay lines are disposed between a first region and a second region of a substrate. Further, the first and second relay lines extend at least partially parallel to each other in a second direction that crosses a first direction in which the first region and the second region are aligned. The first relay line electrically connects a first light-emitting element group disposed in the first region and a third light-emitting element group disposed in the second region. The second relay line electrically connects a second light-emitting element group disposed in the first region and a fourth light-emitting element group disposed in the second region.

Abstract: Vacuum lamination methods for forming conformally coated articles having a preformed lamination layer conformally coated to or on an object such as an LED array are provided. These vacuum lamination methods utilize a single heating step to heat a middle portion of the preformed lamination layer to a flowable condition prior to the preformed lamination layer being conformally coated over the article, such as the array of light emitting diodes disposed on an inner portion of a first side of a submount wafer.

Abstract: A method of manufacturing a light-emitting device includes flip-chip mounting a plurality of light-emitting elements on a substrate separately from each other. A light-transmissive member is bonded on the plurality of light-emitting elements. The light-transmissive member includes a matrix and a manganese-activated fluoride fluorescent material that functions as a wavelength conversion member. A lateral surface of the light-transmissive member is exposed between at least one pair of the plurality of light-emitting elements that are adjacent with each other. A light-reflective covering member is provided on the substrate to cover the lateral surface and a top surface of the light-transmissive member. A portion of the light-reflective covering member that is located on a top surface of the light-reflective covering member is removed to expose the light-transmissive member. The substrate and the light-reflective covering member are cut to yield individual pieces of light-emitting devices.

Abstract: A light emitting device includes a package having a recess which includes a bottom surface and an inner peripheral surface around a periphery of the bottom surface. The package includes a first lead to define a first part of the bottom surface, a second lead to define a second part of the bottom surface, and a resin body to provide the inner peripheral surface and a remaining part of the bottom surface. The bottom surface includes a light emitting element mounting region in the first part and a groove surrounding the light emitting element mounting region. A light emitting element is mounted on the light emitting element mounting region. A light-transmissive resin is provided in the recess to be in at least a part of a groove surface. A light reflecting resin is provided between the inner peripheral surface of the recess and the light-transmissive resin.

Abstract: The present embodiment discloses a package structure for ultraviolet LED, which comprises a substrate, an ultraviolet light-emitting diode (LED), and an optical device. The wavelength of the light emitted by the ultraviolet LED is between 200 and 400 nm. The optical device includes amorphous silicon dioxide, and thus enabling the transmittivity of ultraviolet light greater than 80%. In addition, by including a reflective ring and a metal film, the material aging problem of the sealing material can be prevented by blocking direct ultraviolet-light illumination. The package structure according to the present invention overcomes the limitation on planar packaging, so that the applications of backend processes can be extended.

Abstract: A light-emitting device includes a base, a light-emitting element, and reflecting elements. The light-emitting element is mounted on the base. The reflecting elements are arranged around the light-emitting element to reflect light emitted by the light-emitting element. Each of the reflecting elements includes a core and a dielectric multilayer film. The dielectric multilayer film covers the core and has a thickness to reflect a wavelength of the light emitted by the light-emitting element.

Abstract: An optoelectronic component includes an optoelectronic semiconductor chip configured to emit electromagnetic radiation including a wavelength from a first spectral range, a wavelength-converting element configured to convert electromagnetic radiation including a wavelength from the first spectral range into electromagnetic radiation including a wavelength from a second spectral range, and a reflective element including a first reflectivity in the first spectral range and a second reflectivity in the second spectral range, wherein the first spectral range is below 1100 nm, and the second spectral range is above 1200 nm.