Patents Issued in December 11, 2018
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Patent number: 10153265Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.Type: GrantFiled: August 21, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
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Patent number: 10153266Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.Type: GrantFiled: September 22, 2016Date of Patent: December 11, 2018Assignee: Infineon Technologies AGInventors: Thomas Fischer, Carsten Ahrens, Damian Sojka, Andre Schmenn
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Patent number: 10153267Abstract: An ESD-protective-function-equipped composite electronic component is provided that includes multiple Zener diodes formed from first and second semiconductor layers. Moreover, the second semiconductor layers are disposed on an insulating substrate and in the same plane. The electronic component includes electrodes extending from each of the Zener diodes and one or more thin-film circuit element connected in series between a pair of the electrodes.Type: GrantFiled: January 11, 2017Date of Patent: December 11, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masanobu Nomura, Yutaka Takeshima
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Patent number: 10153268Abstract: Glass substrates comprising an A-side upon which silicon thin film transistor devices can be fabricated and a B-side having a substantially homogeneous organic film thereon are described. The organic film includes a moiety that reduces voltage generation by contact electrification or triboelectrification. Methods of manufacturing the glass substrates and example devices incorporating the glass substrates are also described.Type: GrantFiled: August 7, 2015Date of Patent: December 11, 2018Assignee: Corning IncorporatedInventors: James Patrick Hamilton, Robert George Manley, Jonathan Michael Mis, Wanda Janina Walczak
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Patent number: 10153269Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm?3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.Type: GrantFiled: August 17, 2017Date of Patent: December 11, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Andrew D. Strachan, Alexei Sadovnikov, Gang Xue, Dening Wang
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Patent number: 10153270Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.Type: GrantFiled: January 19, 2015Date of Patent: December 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Lim Kang, Hyun-Jo Kim, Jong-Mil Youn, Soo-Hun Hong
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Patent number: 10153271Abstract: An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and a surface portion of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.Type: GrantFiled: January 3, 2017Date of Patent: December 11, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Yong Li
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Patent number: 10153272Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.Type: GrantFiled: January 6, 2016Date of Patent: December 11, 2018Assignee: SK hynix Inc.Inventor: Jong Su Kim
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Patent number: 10153273Abstract: A semiconductor device is provided that comprises a base structure, a first channel layer overlying the base structure, a second channel layer overlying the first channel layer, and first, second, and third ohmic contacts overlying the second channel layer. The semiconductor device further comprises a metal-semiconductor heterodimension field effect transistor that is formed between the first and second ohmic contacts, the metal-semiconductor heterodimension field effect transistor including a first gate formed through the first and second channel layers. The semiconductor device yet further comprises a high electron mobility transistor formed between the second and third ohmic contacts, the high electron mobility transistor including a second gate formed through the second channel layer without extending through the first channel layer.Type: GrantFiled: December 5, 2017Date of Patent: December 11, 2018Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Roger S. Tsai, Weidong Liu, Yeong-Chang Chou
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Patent number: 10153274Abstract: A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor. An electrode is formed on an element isolation region between the n+-type semiconductor region and the p+-type semiconductor region, and at least apart of the electrode is buried in a trench which is formed in the element isolation region. The electrode is electrically connected to the n+-type semiconductor region.Type: GrantFiled: May 1, 2017Date of Patent: December 11, 2018Assignee: Renesas Electronics CorporationInventor: Sadayuki Ohnishi
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Patent number: 10153275Abstract: A method of operating an IGBT is described. The IGBT has gate, emitter and collector terminals, and IGBT cells, switchable diode cells, and non-switchable diode cells integrated in a semiconductor substrate, wherein each of the IGBT cells and switchable diode cells includes an operable switchable channel region. The IGBT is operated in a reverse conductive mode in which the IGBT cells are in a non-conductive mode and the switchable diode cells and the non-switchable diode cells are in a bipolar mode. The IGBT is brought from the reverse conductive mode to a transit mode in which at least some of the non-switchable diode cells are still in the bipolar mode, the IGBT cells are in the non-conductive mode, and the switchable diode cells are in a unipolar mode, by applying a gate voltage having an absolute value larger than a gate threshold voltage to the gate terminal.Type: GrantFiled: February 27, 2018Date of Patent: December 11, 2018Assignee: Infineon Technologies AGInventors: Johannes Georg Laven, Roman Baburske
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Patent number: 10153276Abstract: In an embodiment, a semiconductor device includes a silicon carbide layer comprising a lateral diode, and a Group III nitride based semiconductor device arranged on the silicon carbide layer.Type: GrantFiled: December 17, 2014Date of Patent: December 11, 2018Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Khalil Hosseini, Frank Kahlmann
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Patent number: 10153277Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.Type: GrantFiled: December 23, 2016Date of Patent: December 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-suk Tak, Tae-jong Lee, Gi-gwan Park, Ji-myoung Lee
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Patent number: 10153278Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack, spacers and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface. The at least one gate stack is disposed over the substrate, disposed on the insulators and over the channel portions of the fins. The spacers are disposed on the side surfaces of the flank portions of the fins. The epitaxy material portions are located above the top surfaces of the flank portions of the fins.Type: GrantFiled: September 28, 2017Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Lin Hsieh, I-Chih Chen, Chih-Mu Huang, Ching-Pin Lin, Ru-Shang Hsiao, Ting-Chun Kuan
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Patent number: 10153279Abstract: A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and ?V1 when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source VDD and a control low power source VNEG. The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or ?V1 if IN is high when EN is high. Only single type VT transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.Type: GrantFiled: February 14, 2017Date of Patent: December 11, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Fei Xu, Bai Yen Nguyen, Jinling Wang, Benjamin Shui Chor Lau
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Patent number: 10153280Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.Type: GrantFiled: January 25, 2017Date of Patent: December 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
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Patent number: 10153281Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.Type: GrantFiled: July 31, 2017Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Michael Amiel Shore
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Patent number: 10153282Abstract: An apparatus for transporting or storing at least one semiconductor wafer in an ultra-high vacuum is provided. A portable vacuum transfer pod is provided comprising an internal wafer storage chamber for storing one or more wafers and a wafer support for supporting at least one wafer within the internal wafer storage chamber. A passively capable vacuum pump capable of passive vacuum pumping is in fluid connection with the internal wafer storage chamber and is mechanically connected to the portable vacuum transfer pod. A shut off valve for opening and closing the fluid connection is between the passively capable vacuum pump and the internal wafer storage chamber.Type: GrantFiled: August 11, 2017Date of Patent: December 11, 2018Assignee: Lam Research CorporationInventors: Theodoros Panagopoulos, Richard Gould, Edmundo Reyes, John Boniface, Ivan Berry, Alexander Dulkin, Bart van Schravendijk
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Patent number: 10153283Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.Type: GrantFiled: February 15, 2017Date of Patent: December 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Gun Kim, Chanmi Lee, Joonkyu Rhee, Ji-Hye Lee, Taeseop Choi
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Patent number: 10153284Abstract: A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.Type: GrantFiled: June 28, 2018Date of Patent: December 11, 2018Assignee: SK Hynix Inc.Inventors: Dong-Kyun Kang, Ho-Jin Cho
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Patent number: 10153285Abstract: A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a contact plug in the dielectric layer. The method also includes partially removing the contact plug to form a recess over the contact plug. The method further includes forming a capacitor element in the recess.Type: GrantFiled: September 5, 2017Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Geng-Shuoh Chang, Yung-Tsun Liu, Chun-Sheng Wu, Chun-Li Lin, Yi-Fang Li
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Patent number: 10153286Abstract: A Static Random Access Memory (SRAM) cell includes a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate as a second source/drain region. A first isolated active region is in the SRAM cell and acts as the bottom plate of the first pull-down transistor and the bottom plate of the first pass-gate transistor. A second isolated active region is in the SRAM cell and acts as the bottom plate of the second pull-down transistor and the bottom plate of the second pass-gate transistor.Type: GrantFiled: May 24, 2017Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon Jhy Liaw
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Patent number: 10153287Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.Type: GrantFiled: October 26, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
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Patent number: 10153288Abstract: A non-volatile memory having a double metal layout is provided that includes a first fuse fabricated on a first conductive layer of the integrated circuit, a second fuse fabricated on a second conductive layer of the integrated circuit, and a transistor fabricated on front-end-of-the-line (FEOL) structure of the integrated circuit. A first memory cell of the non-volatile memory is provided by a first memory circuit comprising the first fuse and the transistor, and a second memory cell of the non-volatile memory is provided by a second memory circuit comprising the second fuse and the transistor.Type: GrantFiled: February 2, 2017Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Meng-Sheng Chang, Bai-Mei Chang, Shao-Yu Chou, Liang Chuan Chang
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Patent number: 10153289Abstract: A non-volatile memory including a substrate, a charge storage structure, two metal gate structures, a first dielectric layer, a second dielectric layer, a first doped region and a second doped region is provided. The charge storage structure is disposed on the substrate. The metal gate structures are disposed on the substrate at two sides of the charge storage structure. The first dielectric layer is disposed between the charge storage structure and the metal gate structures. The second dielectric layer is disposed between the charge storage structure and the substrate. The first doped region and the second doped region are disposed in the substrate at sides of the metal gate structures away from the charge storage structure.Type: GrantFiled: February 25, 2016Date of Patent: December 11, 2018Assignee: United Microelectronics Corp.Inventors: Ji-Ye Li, Duan-Quan Liao
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Patent number: 10153290Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.Type: GrantFiled: September 15, 2015Date of Patent: December 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Felix Ying-Kit Tsui, Huang-Wen Tseng
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Patent number: 10153291Abstract: A method fabricates a lateral non-volatile storage cell. The lateral non-volatile storage cell includes a first transistor including a first transistor body formed on a dielectric layer. The first transistor includes a source region and drain region on opposite sides of the first transistor body. A second transistor is laterally adjacent to the first transistor and includes a second transistor body, parallel with the first transistor body, formed on the dielectric layer. A first layer of gate oxide of a first thickness is formed over the first transistor body, and a second layer of gate oxide of a second thickness is formed over a portion of the second transistor body. The first thickness and the second thickness are different. A floating gate is formed over the first layer of gate oxide, the second layer of gate oxide, and the dielectric layer.Type: GrantFiled: November 9, 2017Date of Patent: December 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. DeForge, John J. Ellis-Monaghan, Terence B. Hook, Kirk D. Peterson
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Patent number: 10153292Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: GrantFiled: February 28, 2018Date of Patent: December 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, Hanmei Choi
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Patent number: 10153293Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.Type: GrantFiled: July 25, 2017Date of Patent: December 11, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tamotsu Ogata
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Patent number: 10153294Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.Type: GrantFiled: September 29, 2017Date of Patent: December 11, 2018Assignee: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Patent number: 10153295Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.Type: GrantFiled: June 5, 2017Date of Patent: December 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Seop Lee, Seokcheon Baek, Jinhyun Shin
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Patent number: 10153296Abstract: A memory device includes a substrate and a stacked body arranged along a first direction. The stacked body includes electrode films. A configuration of an end portion in a second direction of the stacked body is a staircase configuration. Steps corresponding to the electrode films are formed in the staircase configuration. A first distance between a first step and an end edge of the stacked body in the second direction is shorter than a second distance between a second step and the end edge in the second direction. The first step is positioned at an end portion in a third direction of the stacked body. The second step is positioned at a central portion in the third direction of the stacked body. The first and second steps correspond to two of the electrode films positioned at the same level when counting along the first direction from the substrate side.Type: GrantFiled: July 14, 2017Date of Patent: December 11, 2018Assignee: Toshiba Memory CorporationInventors: Naoyuki Iida, Hideki Inokuma, Naoki Yamamoto, Yoshihiro Yanai
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Patent number: 10153297Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.Type: GrantFiled: November 30, 2017Date of Patent: December 11, 2018Assignee: SK Hynix Inc.Inventor: Kwang-Seok Oh
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Patent number: 10153298Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.Type: GrantFiled: February 9, 2018Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventors: Jie Sun, Fatma Arzum Simsek-Ege
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Patent number: 10153299Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.Type: GrantFiled: January 4, 2017Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Chandra Mouli, Gurtej S. Sandhu
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Patent number: 10153300Abstract: A semiconductor device comprises a substrate and a high-electron-mobility transistor (HEMT). The substrate is formed with a recess. At least a portion of the HEMT is disposed in the recess. A method for manufacturing the semiconductor device is also disclosed. A radio frequency (RF) front-end module that employs the semiconductor device is also disclosed.Type: GrantFiled: February 5, 2016Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jun-De Jin, Kuan-Chi Tsai
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Patent number: 10153301Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: GrantFiled: July 10, 2017Date of Patent: December 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
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Patent number: 10153302Abstract: A method for manufacturing a pixel structure is provided. A patterned semiconductor material layer, an insulation material layer, and a gate electrode material layer are formed in sequence on a substrate to form a stacked structure. A patterned photoresist layer is formed on the stacked structure by using a photomask. A portion of the stacked structure is removed to pattern the patterned semiconductor material layer into a patterned semiconductor layer by using the patterned photoresist layer as a mask. Another portion of the stacked structure is etched by using a portion of the patterned photoresist layer as a mask until a portion of the semiconductor layer in the stacked structure is exposed. Then, an exposed portion of the semiconductor layer is modified to increase a conductivity of the exposed portion of the semiconductor layer. Finally, the patterned photoresist layer is removed. A pixel structure manufactured by the method is provided.Type: GrantFiled: August 18, 2015Date of Patent: December 11, 2018Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Hsi-Ming Chang, Yen-Yu Huang
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Patent number: 10153303Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.Type: GrantFiled: May 5, 2016Date of Patent: December 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsushi Umezaki, Hajime Kimura
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Patent number: 10153304Abstract: The present disclosure relates to a TFT includes an active layer formed on a substrate, wherein the active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The first semiconductor layer is made by Indium gallium zinc oxide (IGZO) having an atomic ratio In/(Ga+Zn) smaller than 50%, and the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) greater than 55%. The present disclosure also includes an array substrate having the TFT and the manufacturing method thereof. The array substrate may be adopted in LCD or OLED. The TFT adopts two layers of IGZO semiconductor materials to be the semiconductor of the active layer. Not only the demand toward the TFT characteristics may be satisfied, but also the carrier mobility rate of the IGZO active layer may be enhanced.Type: GrantFiled: July 20, 2016Date of Patent: December 11, 2018Assignee: Wuhan China Star Optoelectronics Technology Co., LtdInventor: Fang Qin
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Patent number: 10153305Abstract: The present invention provides an array substrate, a manufacturing method thereof and a display device, relates to the field of display technology. The array substrate comprises: a substrate; a gate metal layer comprising gate lines; a source and drain metal layer comprising data lines, the gate lines and the data lines intersecting with each other to define a plurality of sub-pixel areas; a pixel electrode layer provided on the substrate, which comprises a plurality of pixel electrodes which are in one-to-one correspondence with the plurality of sub-pixel areas; a common electrode layer provided on the substrate, which is provided with a plurality of cutting hole at positions corresponding to spaces between the pixel electrodes; a first insulating layer provided between the pixel electrode layer and the common electrode layer; and a second insulating layer provided between the gate metal layer and the source and drain metal layer.Type: GrantFiled: October 24, 2014Date of Patent: December 11, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventor: Zheng Wang
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Patent number: 10153306Abstract: A radio-frequency (RF) device includes a semiconductor substrate, a first field-effect transistor (FET) disposed on the substrate, the first FET having a first plurality of drain fingers, and a second FET connected in series with the first FET along a first dimension, the second FET having a second plurality of drain fingers that extent in a second dimension that is orthogonal with respect to the first dimension.Type: GrantFiled: February 27, 2017Date of Patent: December 11, 2018Assignee: Skyworks Solutions, Inc.Inventors: Tzung-Yin Lee, Aniruddha B. Joshi, David Scott Whitefield, Maureen Rosenberg Brongo
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Patent number: 10153307Abstract: A semiconductor device is provided in which ESD is less likely to occur in a manufacturing process thereof. In manufacture of a semiconductor device including a long lead wiring A, during steps with direct exposure to a plasma atmosphere, a plurality of island-shaped wirings is formed for the wiring A and then electrically connected to one another in series. Specifically, a plurality of island-shaped wirings is formed, covered with an insulating layer, and electrically connected to one another in series by a wiring formed over the insulating layer. The island-shaped wiring and the wiring formed over the insulating layer are electrically connected to each other through an opening formed in the insulating layer.Type: GrantFiled: October 19, 2015Date of Patent: December 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 10153308Abstract: The present disclosure provides a method for manufacturing a thin film transistor comprising: forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed; forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, making the second regions of the oxide semiconductor layer being doped by aluminum ions to form conductor regions; etching the remaining aluminum layer after the annealing treatment; renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions, and oxidizing the conductor regions; stacking an insulating layer, and forming a source electrode and a drain electrode on the insulating layer.Type: GrantFiled: July 26, 2017Date of Patent: December 11, 2018Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Jinming Li
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Patent number: 10153309Abstract: A manufacturing method of a display panel disclosed by the invention includes: providing a substrate, the substrate having a first metal layer disposed thereon, the substrate including a first display region and a first peripheral region, the first metal layer covering the first display region and the first peripheral region; laying a photoresist layer on the first metal layer to form a first half-finished plate; exposing and developing the first half-finished plate to form a second half-finished plate with first and second preset patterns; etching and stripping the second half-finished plate to form a first preset metal wire group on the first display region and form a second preset metal wire group on the first peripheral region. The invention can significantly reduce the occurrence of electrostatic discharge phenomenon during the manufacturing process of a display panel and thus the yield of the display panel can be greatly improved.Type: GrantFiled: August 14, 2015Date of Patent: December 11, 2018Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Yuanfu Liu
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Patent number: 10153310Abstract: A photon detection device includes a single photon avalanche diode (SPAD) disposed in a semiconductor layer. A guard ring structure is disposed in the semiconductor layer surrounding the SPAD to isolate the SPAD. A well region is disposed in the semiconductor layer surrounding the guard ring structure and disposed along an outside perimeter of the photon detection device. A contact region is disposed in the well region only in a corner region of the outside perimeter such that there is no contact region disposed along side regions of the outside perimeter. A distance between an inside edge of the guard ring structure and the contact region in the corner region of the outside perimeter is greater than a distance between the inside edge of the guard ring structure and the side regions of the outside perimeter such that an electric field distribution is uniform around the photon detection device.Type: GrantFiled: July 18, 2016Date of Patent: December 11, 2018Assignee: OmniVision Technologies, Inc.Inventors: Bowei Zhang, Vincent Venezia, Gang Chen, Dyson H. Tai, Duli Mao
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Patent number: 10153311Abstract: An image sensor includes: a pixel chip provided with a plurality of pixels, a plurality of first transfer lines, and a plurality of capacitors; a circuit chip provided with a plurality of column reading circuits, a plurality of column scanning circuits, a second transfer line, and a constant current source; and a connection portion stacked and provided between the pixel chip and the circuit chip and configured to connect a capacitor, which is arranged in the pixel chip and has a trench structure, and a first transistor arranged in the circuit chip to each other via an electrode. The capacitor is configured to form a transfer capacity removing a noise included in an imaging signal and connect the pixel chip and the circuit chip to each other via the electrode and the connection portion.Type: GrantFiled: August 4, 2017Date of Patent: December 11, 2018Assignee: OLYMPUS CORPORATIONInventors: Satoru Adachi, Nana Akahane, Noriyuki Fujimori
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Patent number: 10153312Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.Type: GrantFiled: October 23, 2017Date of Patent: December 11, 2018Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: François Roy, Helene Wehbe-Alause, Olivier Noblanc
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Patent number: 10153313Abstract: A unit pixel formed on a substrate and configured to convert incident light to an electrical signal to constitute an image sensor provided. A unit pixel includes a source having a source voltage supplied thereto and having a silicide layer for metal contact formed thereabove, a drain spaced apart from the source and having a silicide layer for metal contact formed thereabove, a channel formed between the source and the drain and having a current flowed therethrough, an insulating layer formed above the channel, a light receiving part placed in a light receiving region of the surface of the image sensor and having changes in electrical properties caused by incident light therein; and a floating gate formed above the insulating layer so as to be placed between the source and the drain, configured to be electrically connected with the light receiving part, and configured to control an amount of current flowing through the channel by an electric field generated by the changes in electrical properties.Type: GrantFiled: December 12, 2014Date of Patent: December 11, 2018Inventor: Kwangsue Park
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Patent number: 10153314Abstract: The present technology relates to a semiconductor apparatus, a solid-state image pickup device, an image pickup apparatus, and an electronic apparatus capable of improving impedance characteristics while preventing an occurrence of a flare and an interference due to a bonding jig, and achieving downsizing an apparatus. By aligning the heights of a cover glass and a semiconductor device, a distance between the cover glass and the semiconductor device is set to be minimum, and thus it is possible to suppress an occurrence of a flare due to incident light reflected on a side surface of the semiconductor device, and improve the impedance characteristics of the semiconductor device and the semiconductor image pickup device. Further, the interference of the jig used for the semiconductor device is reduced. The present technology can be applied to a CMOS image sensor.Type: GrantFiled: December 2, 2015Date of Patent: December 11, 2018Assignee: SONY CORPORATIONInventor: Satoru Wakiyama