Abstract: A photosensitive imaging apparatus and a method of forming such an apparatus are disclosed. The apparatus includes: a first semiconductor substrate, including a photosensitive semiconductor layer including an array of photodetectors; and a second semiconductor substrate, stacked with the first semiconductor substrate and including a pixel-circuitry semiconductor layer including an array of in-pixel amplifier circuitries. Each in-pixel amplifier circuitry includes at least one first pixel MOS transistor. Each first pixel MOS transistor has an active region disposed between the gate layer thereof and the first semiconductor substrate. The photosensitive imaging apparatus allows an effective reduction in noises produced during light reception of the in-pixel amplifier circuitries and an increased light utilization of the photodetectors.

Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region adjacent to the radiation-sensing region. The image-sensor device further includes a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.

Abstract: Among other things, an integral image sensor includes a sensor surface having a surface area at which light-sensitive pixels are arranged in rows and columns. The surface area includes two or more light-sensitive subareas each of the subareas having been configured to have been diced from a wafer along two orthogonal dimensions to form a discrete image sensor. The two or more light-sensitive subareas are arranged along one of the two orthogonal dimensions. The sensor surface of the integral image sensor is flat and continuous across the two or more subareas.

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor integrated chip. The method may be performed by forming an image sensing element within a substrate, and forming an absorption enhancement structure over a back-side of the substrate. The absorption enhancement structure is selectively etched to concurrently define a plurality of grid structure openings and a ground structure opening within the absorption enhancement structure. A grid structure is formed within the plurality of grid structure openings and a ground structure is formed within the ground structure opening. The grid structure extends from over the absorption enhancement structure to a location within the absorption enhancement structure.

Abstract: A semiconductor device includes: a visible light sensing layer, having a first surface and a second surface opposite to the first surface; an infrared ray sensing layer, having a first surface and a second surface opposite to the first surface, and the first surface of the visible light sensing layer attached to the second surface of the infrared ray sensing layer; and a circuitry layer, having a first surface and a second surface opposite to the first surface, and the first surface of the infrared ray sensing layer attached to the second surface of the circuitry layer.

Abstract: The present invention is directed towards a moisture resistant radiation detector core assembly which was constructed by first assembling the photon-electron conversion layer, integrated circuit and the connection elements between and then encapsulating the whole assembly. This provides improved moisture barrier properties, since the encapsulation also covers the connection elements and does not have to be opened to apply the electrical connections, as is done for known radiation detector core assemblies.

Abstract: An organic light emitting display device includes a substrate in which an active area and a bending area are defined, a thin film transistor on the substrate in the active area, a first wiring line on the substrate in the bending area, a first planarization layer which is on the thin film transistor in the active area and on the first wiring line in the bending area, a second wiring line on the first planarization layer in the bending area, a second planarization layer which is on the first planarization layer in the active area and on the first planarization layer and the second wiring line in the bending area, an organic light emitting element on the second planarization layer in the active area, and a micro-cover layer on the second planarization layer in the bending area.

Abstract: A production method for a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer that is located in a surface portion of the semiconductor wafer and that includes a constituent element of the cluster ions in solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The first step is performed such that a portion of the modified layer in terms of a thickness direction becomes an amorphous layer and an average depth of an amorphous layer surface at a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.

Abstract: A CCD with an internal heterostructure well to store the photogenerated carriers is realized by using barrier and absorber semiconductors with a type-II band alignment in nBn or pBp photodetectors to form a specific barrier configured to confine the depletion region and a well to trap and store the photogenerated minority carriers. Depending on the spectral regime, (InAs/InAsSb)/(InAs/AlGaSb) superlattices can be used in the infrared, Si/Ge or AlP/GaP in the visible portion of optical spectrum, and GaN/ZnO in the UV portion. The resulting device not only leverages the advantages of the conventional CCD (such as in-pixel signal integration to suppress the noise), but also boasts an advantageously low operational voltage, thereby ensuring the low power consumption and low band-to-band tunneling current/noise (in particular, for use as an infrared photodetector).

Abstract: A method of surface mounting micro-devices includes adhering a first plurality of micro-devices on a donor substrate to a transfer surface with an adhesive layer, removing the first plurality of micro-devices from donor substrate while the first plurality of micro-devices remain adhered to the transfer surface, positioning the transfer surface relative to a destination substrate so that a subset of the plurality of micro-devices on the transfer surface abut a plurality of receiving positions on the destination substrate, the subset including one or more micro-devices but less than all of micro-devices of the plurality of micro-devices, selectively neutralizing one or more of regions of the adhesive layer on the transfer surface corresponding to the subset of micro-device to light to detach the subset of micro-devices from the adhesive layer, and separating the transfer surface from the destination substrate such that the subset of micro-devices remain on the destination substrate.

Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.

Abstract: A semiconductor device includes first isolation lines positioned above a substrate and extending in a first direction. Second isolation lines are positioned above the first isolation lines and extend in a second direction, perpendicular to the first direction, to have a right angle on a plane parallel to an upper surface of the substrate. A first conductive line is disposed between the first isolation lines. The first conductive line is spaced apart from the substrate. A second conductive line is disposed between the second isolation lines. First data storage patterns are disposed between the first isolation lines. The first data storage patterns are positioned above the first conductive line. Second data storage patterns are disposed between the second isolation lines. The second data storage patterns are positioned above the second conductive line. A third conductive line is positioned above the second isolation lines and extends in the first direction.

Abstract: The present invention is to provide an Organic Light-Emitting Diode (OLED) display panel and a package method thereof. The method includes forming simultaneously a supporter and a hydrophobic wall on an outer position of and enclosing the OLED device by screen printing, wherein the hydrophobic wall is on an outer position of the supporter; and bonding the cover plate and the OLED substrate. The present invention can effectively protect the OLED device from outer moisture and oxygen to improve package effect and increase life of the OLED device. The supporter and the hydrophobic wall are formed simultaneously by screen printing so the method is simple and the manufacturing efficiency is improved.

Abstract: The present disclosure discloses a method of manufacturing a display panel. The method includes: providing a first substrate, and forming a release layer on the first substrate; forming a thin film transistor driving layer on the first substrate; forming a display element on the first substrate, wherein a part of the display element forms above the release layer and another part of the display element forms above the thin film transistor driving layer; separating the release layer and the first substrate with a laser; removing the release layer and the display element above the release layer, and forming a hollow portion on the first substrate; packaging the display element to form a display panel, wherein the display panel at least includes a first packaging portion; and providing a through hole passing through the display panel at a region on the display panel corresponding to the hollow portion.

Abstract: An organic EL device includes a substrate; an organic EL element that is disposed on the substrate; a sealing part that is formed to cover the organic EL element; a color filter that includes coloring layers formed on the sealing part; and a dimension evaluation pattern for evaluating dimensional accuracy of the color filter.

Abstract: A display device may include: a display area; a peripheral area disposed outside the display area and in which at least a part of a black matrix is disposed; and a plurality of pixel columns including: a first pixel column configured to display a first color, the first pixel column including a first boundary slope defined by a boundary line between the first pixel column and the black matrix; and a second pixel column disposed adjacent to the first pixel column, the second pixel column configured to display a second color different from the first color and including a second boundary slope defined by a boundary line between the second pixel column and the black matrix, wherein the first boundary slope may have a positive value, and the second boundary slope has a negative value.

Abstract: To provide a display device with low power consumption. The display device includes a plurality of pixels each having a light-emitting element having a structure in which light emitted from a light-emitting layer is resonated between a reflective electrode and a light-transmitting electrode, wherein no color filter layers are provided or color filter layers with high transmittance are provided in pixels for light with relatively short wavelengths (e.g., pixels for blue and/or green), and a color filter layer is selectively provided in pixels for light with a long wavelength (e.g., pixels for red), and thereby maintaining color reproducibility and consuming less power.

Abstract: A method for manufacturing an OLED backplate and a method for manufacturing an OLED panel are provided. In the method for manufacturing the OLED backplate of the present disclosure, a protective photoresist layer is manufactured on a pixel defined layer in which the top surface thereof has a hydrophobic property and the side surfaces thereof have a hydrophilic property before an electrode layer is treated by an oxygen plasma to remove photoresist residues, thereby the top surface of the pixel defined layer covered by the protective photoresist layer is not affected by the oxygen plasma in the proceeding of an oxygen plasma treatment, and still has the hydrophobic property. Therefore, the properties of the top surface of the pixel defined layer having the hydrophobic property and the side surfaces of the pixel defined layer having the hydrophilic property are kept while the photoresist residues on the electrode layer is removed, and thus an OLED device can be easily manufactured by an ink-jet printing process.

Abstract: A display apparatus includes a substrate having a plurality of pixel areas, and a pixel circuit including a storage capacitor and a plurality of thin film transistors (TFTs) which are disposed in each pixel area. At least one of the plurality of TFTs includes a semiconductor layer disposed on the substrate and including a first ion impurity, a source area and a drain area, which are spaced apart from each other, have a first depth from a surface of the semiconductor layer, and include a second ion impurity, a gate electrode disposed on the semiconductor layer between the source area and the drain area, and a bias wiring electrically connected to the semiconductor layer and disposed adjacent to at least one of the source area and the drain area.

Abstract: Provided are a manufacturing method of a transistor on color filter type organic light emitting display and a transistor on color filter type organic light emitting display. In the manufacturing method of a transistor on color filter type organic light emitting display, after preparing the color filter layer, by coating the zinc oxide solution mixed with lithium on the gate insulation layer in a spin coating manner to form a zinc oxide coating layer mixed with lithium and then, by annealing the zinc oxide coating layer mixed with lithium and patterning the zinc oxide coating layer mixed with lithium to form a channel layer, the process temperature can be as low as 200 Celsius degrees to satisfy the temperature condition of manufacturing the transistor on color filter type organic light emitting display and the operation is easy without using the expensive vacuum equipment.

Abstract: A semiconductor device including a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer includes a first source region, a first drain region, a second source region, and a second drain region connected to a channel region. The first gate electrode is disposed below the semiconductor layer. The first gate electrode is insulated from the semiconductor layer. The first gate electrode at least partially overlaps the shared channel region. The second gate electrode is disposed above the semiconductor layer. The second gate electrode is insulated by a second gate insulating layer. The second gate electrode at least partially overlaps the channel region.

Abstract: A flexible display device comprises a substrate having a flat portion and a curved portion, wherein a pixel array is provided in the flat portion and a pad portion connected to the pixel array is provided in the curved portion; and an encapsulation layer provided on the substrate to cover the pixel array, wherein the encapsulation layer comprises a terminal portion; an Integrated Circuit (IC) portion having at least one driving IC; and a lead portion having leads which connect the terminal portion and the driving IC portion, and wherein the curved portion of the substrate is bent so that the pad portion and the terminal portion are in contact with each other.

Abstract: A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.

Abstract: A semiconductor device includes a common doping region located within a semiconductor substrate of the semiconductor device. The common doping region includes a first portion. A maximal doping concentration within the first portion is higher than 1·1015 cm?3. The common doping region includes a second portion. A minimal doping concentration within the second portion is lower than 50% of the maximal doping concentration within the first portion of the common doping region. The common doping region includes a third portion. A minimal doping concentration within the third portion is more than 30% higher than the minimal doping concentration within the second portion. The second portion of the common doping region is located vertically between the first portion of the common doping region and the third portion of the common doping region.

Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.

Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

Abstract: A semiconductor device includes a substrate; an active layer disposed over the substrate and having a source region and a drain region; a contact region disposed over the substrate; a gate structure disposed over the active layer, wherein the gate structure includes a middle portion and a lateral portion connecting to the middle portion, and the lateral portion has a snake shape.

Abstract: A method for producing a tunnel field-effect transistor (TFET) having a source region, a channel region, and a drain region includes arranging an epitaxial layer on a silicon substrate; applying a gate arrangement having a gate electrode to the epitaxial layer, a gate dielectric being arranged between the gate electrode and the silicon substrate; forming a doped pocket region below the gate dielectric adjacent to the source region; forming a selectively silicidated region in the source region, the selectively silicidated region extending as far as to below a gate; and forming a counter-doped region doped in an opposite way to the pocket region adjacent to the pocket region in the source region by diffusion of dopants out of the silicidated region, as a result of which a tunnel junction parallel to the electric field lines of the gate electrode is achieved.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

Abstract: To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target. In that case, partial pressure of water in a deposition chamber before or in the deposition is set to be lower than or equal to 10?3 Pa, preferably lower than or equal to 10?4 Pa, more preferably lower than or equal to 10?5 Pa. Thus, a dense oxide semiconductor film is obtained. The density of the oxide semiconductor film is higher than 6.0 g/cm3 and lower than 6.375 g/cm3.

Abstract: A semiconductor device includes a first nitride semiconductor layer containing Ga, a second nitride semiconductor layer provided on the first nitride semiconductor layer containing Ga, a first electrode and a second electrode provided on or above the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode provided between the first electrode and the second electrode, a conductive layer provided on or above the second electrode, of which a first distance to the second electrode is smaller than a second distance between the second electrode and the gate electrode, and which is electrically connected to the first electrode or the gate electrode, a first aluminum oxide layer provided between the gate electrode and the second electrode and provided between the second nitride semiconductor layer and the conductive layer, a silicon oxide layer, and a second aluminum oxide layer.

Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.

Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

Abstract: The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom surface in a short direction. A thickness of the gate insulating film covering the peripheral part is thicker than a thickness of the gate insulating film covering the center part.

Abstract: In a method of manufacturing a semiconductor device, a first contact hole is formed in one or more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive layer is formed in the first contact hole. A first metal layer is formed on the adhesive layer in the first contact hole. A silicide layer is formed on an upper surface of the first metal layer. The silicide layer includes a same metal element as the first metal layer.

Abstract: A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region.

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

Abstract: The present invention provides a TFT substrate manufacturing method, which includes first forming a graphene semiconductor active layer on a metal foil, then sequentially forming an inorganic insulation layer and an organic base on the graphene semiconductor active layer, followed by turning up-side down to set the metal foil on a topmost layer, then forming a photoresist layer, through a patterning operation, on the metal foil and subjecting the metal foil to etching to form a source electrode and a drain electrode, then sequentially forming an organic insulation layer and a gate electrode conductor layer on the photoresist layer and the graphene semiconductor active layer, and finally, applying a photoresist peeling agent to remove the photoresist layer with portions of the organic insulation layer and the gate electrode conductor layer located thereon removed therewith so as to obtain patterned gate insulation layer and gate electrode.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a fin structure, a metal gate and a first polysilicon strip. The fin structure is on the substrate. The metal gate is over the fin structure and is substantially perpendicular to the fin structure. The first polysilicon strip is at a first edge of the fin structure and is substantially parallel to the metal gate.

Abstract: A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.

Abstract: A method for manufacturing a super junction power MOSFET includes forming a first trench in a substrate, forming a first oxide layer over the substrate and in the bottom and along sidewalls of the trench, depositing electrically conductive material in the trench, masking a first portion of the electrically conductive material, forming a recessed portion of the electrically conductive material, forming an oxide portion over and in contact with the recessed portion of the electrically conductive material, removing a part of the oxide portion by masking, removing the first oxide layer on the sidewalls while another part of the oxide portion remains in contact with the recessed portion of the electrically conductive material, forming a gate dielectric along exposed sidewalls of the trench, and depositing additional electrically conductive material over the other part of the oxide portion in the trench.

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

Abstract: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.

Abstract: A method for manufacturing a transistor having high electron mobility, encompassing a substrate having a heterostructure, in particular an AlGaN/GaN heterostructure, having the steps of: generation of a gate electrode by patterning a semiconductor layer that is applied onto the heterostructure, the semiconductor layer encompassing, in particular, polysilicon; application of a passivating layer onto the semiconductor layer; formation of drain regions and source regions by generation of first vertical openings that extend at least into the heterostructure; generation of ohmic contacts in the drain regions and in the source regions by partly filling the first vertical openings with a first metal at least to the height of the passivating layer; and application of a second metal layer onto the ohmic contacts, the second metal layer projecting beyond the passivating layer.

Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.