Abstract: A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. A hole or a groove is formed in the layer to be etched by performing dry etching on the layer to be etched using the patterned mask layer. The mask layer includes a first region and a second region. The first region includes boron and the second region includes boron such that a density of boron in the second region is different from a density of boron in the first region, or the first region includes carbon and the second region includes carbon such that a density of carbon in the second region is different from a density of carbon in the first region.

Abstract: The present invention pertains to a patterning method. By taking advantage of the etching loading effect due to different pattern densities in the memory cell region and the peripheral region, the first hard mask is not masked when anisotropically etching the first hard mask within the memory cell region.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

Abstract: A semiconductor device comprises a first semiconductor wafer including a cavity formed in the first semiconductor die. A second semiconductor die is bonded to the first semiconductor die over the cavity. A first transistor includes a portion of the first transistor formed over the cavity.

Abstract: A method of manufacturing a semiconductor device includes: forming a light absorbing layer on a front surface of a semiconductor substrate or in the semiconductor substrate; forming a high concentration layer, in which an impurity concentration is increased, by implanting impurities into the semiconductor substrate; and heating the high concentration layer so as to activate the impurities in the high concentration layer. The formation of the light absorbing layer and the formation of the high concentration layer are performed such that the light absorbing layer and the high concentration layer at least partially overlap each other. The high concentration layer is heated by irradiating the high concentration layer with light from a front surface side of the semiconductor substrate in the heating of the high concentration layer.

Abstract: In a method of controlling a threshold of a transistor, a gate insulating film is formed in a channel region of a metal-oxide-semiconductor (MOS) transistor on a main surface of a semiconductor substrate. A first electrode layer is formed on the gate insulating film and a second electrode layer containing a work function adjusting metal is formed on the first electrode layer. Thereafter, an oxidation treatment or nitridation treatment using a microwave plasma processing apparatus is performed to inactivate the work function adjusting metal, thereby executing a threshold control of the MOS transistor.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first fin structure which includes first semiconductor patterns and second semiconductor patterns stacked alternately on a substrate and extends in a first direction, forming an exposed first wire pattern group which includes the second semiconductor patterns by removing the first semiconductor patterns, heat-treating the exposed first wire pattern group, and forming a first gate electrode which surrounds the first wire pattern group and extends in a second direction different from the first direction.

Abstract: A method of forming patterns, patterns formed according to the method, and a semiconductor device including the patterns, the method including forming an etching subject layer on a substrate, forming a first layer on the etching subject layer such that the first layer has a projecting pattern, forming a second layer such that the second layer completely covers the projecting pattern of the first layer, partially removing the second layer such that a top of the projecting pattern is exposed and a patterned second layer remains at a side of the projecting pattern, removing the first layer such that a top of the etching subject layer is exposed, and etching the etching subject layer using the patterned second layer as an etching mask, wherein one of the first layer and the second layer is a carbon-containing layer and the other is a silicon-containing layer, and the silicon-containing layer is formed by coating a silicon-containing composition and heat-treating the same.

Abstract: A method of etching a silicon oxide film on a substrate, includes generating reaction products containing moisture by modifying the silicon oxide film by supplying a mixed gas containing a gas containing a halogen element and a basic gas onto the surface of the silicon oxide film and making chemical reaction of the silicon oxide film with the mixed gas, generating different reaction products by modifying the silicon oxide film by supplying the gas containing a halogen element onto an interface between the silicon oxide film and the reaction products and making a chemical reaction on the silicon oxide film with the gas containing a halogen element by using the moisture contained in the reaction products, and heating and removing the reaction products and the different reaction products.

Abstract: The present invention relates to a process for selectively removing a block on one side using a wet etching process in connection with self-assembly block copolymer thin films that have etching-resisting properties different from each other. The present invention can form a vertical nanopore structure having a high aspect ratio, even in the case of a thick film which has a vertically oriented cylinder self-assembly structure and which has one or more periods, by overcoming the limit of the prior art, which cannot implement a vertical pore structure through wet etching.

Abstract: A method of manufacturing a semiconductor device according to an embodiment includes forming a first interlayer film on a first layer, the first interlayer film containing a first molecule and a second molecule, and the first molecule and the second molecule being chemically bonded with each other. The method of manufacturing a semiconductor device includes phase-separating the first interlayer film. The method of manufacturing a semiconductor device includes forming a second layer on the phase-separated first interlayer film. The first molecule has a first affinity with the first layer and a second affinity with the second layer, the first affinity being larger than the second affinity. The second molecule has a third affinity with the second layer and a fourth affinity with the first layer, the third affinity being larger than the fourth affinity.

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Abstract: According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a film to be processed on a substrate. The method includes forming a first resist pattern on the film, the first resist pattern having a first stepped structure including a plurality of steps. The method includes forming a second resist pattern on the first resist pattern by use of a template for nanoimprint. The second resist pattern has a second stepped structure, which is arranged corresponding to the first stepped structure and is formed such that a step-up surface extends perpendicularly to a flat surface. The method includes processing the film through the second resist pattern and the first resist pattern.

Abstract: A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another.

Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Abstract: Disclosed is a substrate treating apparatus including the following units: a supplying unit which supplies a process liquid including a sublimable substance in a melt state on a pattern-formed surface of a substrate W; a solidifying unit which solidifies the process liquid on the pattern-formed surface to produce a solidified body; and a sublimating unit which sublimates the solidified body to remove the solidified body from the pattern-formed surface. In this apparatus, the sublimable substance includes a fluorinated carbon compound.

Abstract: A substrate processing apparatus that performs processing by immersing a substrate into a processing liquid obtained by mixing phosphoric acid with a diluent includes a concentration sensing means for sensing the concentration of the processing liquid by measuring the absorbance characteristics of the processing liquid. The concentration sensing means includes a light-transmitting section that introduces the processing liquid into the inside to let the processing liquid pass therethrough, a light-emitting section that radiates light having a predetermined wavelength to the light-transmitting section, a light-receiving section that receives the light therefrom via the light-transmitting section, a first lens that condenses the light emitted from the light-emitting section to the light-transmitting section, a second lens that condenses the light that has passed through the light-transmitting section to the light-receiving section, and a cooling mechanism that cools at least one of these.

Abstract: A method for the joining of ceramic pieces into an assembly adapted to be used in semiconductor processing. The joined pieces are adapted to withstand the environments within a process chamber during substrate processing, chamber cleaning processes, and the oxygenated atmosphere which may be seen within the shaft of a heater or electrostatic chuck. The ceramic pieces may be aluminum nitride and the pieces may be brazed with aluminum. The joint material is adapted to withstand both the environments within a process chamber during substrate processing, and the oxygenated atmosphere which may be seen within the shaft of a heater or electrostatic chuck. The joint is adapted to provide a hermetic seal across the joint. The joined pieces are adapted to be separated at a later time should rework or replacement of one of the pieces be desired.

Abstract: A plurality of support pins that support a semiconductor wafer are located upright on a top surface of a susceptor. A condenser lens is located on a bottom surface of the susceptor opposite to the support pins with respect to the susceptor. The condenser lens is located such that its optical axis coincides with the central axis of the corresponding support pin. Of light emitted from halogen lamps from below, light entering the condenser lens is condensed at a contact portion between the corresponding support pin and the semiconductor wafer, so that the vicinity of the contact portion rises in temperature. The vicinity of the contact portion of the semiconductor wafer in contact with the support pin in which the temperature tends to drop is relatively intensely heated in order to suppress the temperature drop, and an in-plane temperature distribution of the semiconductor wafer during light irradiation can thus be made uniform.

Abstract: Embodiments of the present disclosure generally provide apparatus and methods for monitoring one or more process parameters, such as temperature of substrate support, at various locations. One embodiment of the present disclosure provides a sensor column for measuring one or more parameters in a processing chamber. The sensor column includes a tip for contacting a chamber component being measured, a protective tube having an inner volume extending from a first end and second end, wherein the tip is attached to the first end of the protective tube and seals the protective tube at the first end, and a sensor disposed near the tip. The inner volume of the protective tube houses connectors of the sensor, and the tip is positioned in the processing chamber through an opening of the processing chamber during operation.

Abstract: Provided is an indicator that can easily detect whether treatment with at least one member of plasma, ozone, ultraviolet rays, and radical-containing gas is uniformly performed on an entire substrate in an electronic device manufacturing apparatus; also provided is a method for designing and/or managing an electronic device manufacturing apparatus using the indicator. The indicator is used in an electronic device manufacturing apparatus, wherein (1) the indicator detects at least one member selected from the group consisting of plasma, ozone, ultraviolet rays, and radical-containing gas, (2) the indicator has a shape that is the same as that of a substrate used in the electronic device manufacturing apparatus, (3) the indicator contains a color-changing layer, and (4) the color-changing layer is formed by an ink composition whose color changes or disappears by reaction with at least one member selected from the group consisting of plasma, ozone, ultraviolet rays, and radical-containing gas.

Abstract: Embodiments method and apparatus for transferring a substrate are provided herein. In some embodiments, a substrate cassette includes a body having an upper portion and a lower portion, the upper portion and the lower portion defining an interior volume when the upper portion is coupled to the lower portion; a locking mechanism moveable between a locked position, in which the upper and lower portions are coupled, and an unlocked position, in which the lower portion can be separated from the upper portion; and a load distribution plate coupled to an upper surface of the upper portion along an edge of the upper portion to distribute a load applied to the load distribution plate.

Abstract: The present invention provides a micro transfer printing method, which uses pick-up projections provided on a transfer head to suck and hold micro components arranged on a carrier plate, followed by reversing the transfer head and the carrier plate to make the transfer head positioned under the carrier plate, and then separates the transfer head and the carrier plate from each other to allow the micro components that are sucked and held by the pick-up projections to be carried by and supported on the transfer head, and then moves the transfer head that carries thereon the micro components to a location above a receiving substrate and turning the transfer head up side down to allow the micro components that are held on the pick-up projections to be positioned on the receiving substrate.

Abstract: Without a lateral transfer mechanism in a local vehicle, the buffering capacity of a temporary storage apparatus is increased. The temporary storage apparatus stores carriers temporarily between overhead travelling vehicles and load ports. A travelling rail for the local vehicle is provided to allow the local vehicle to run below the travelling rail for the overhead vehicles and over the load ports. A slidable buffer slidable between a position under the travelling rail for the local vehicle and a position shifted laterally and a controller for controlling the local vehicle and the slidable buffer are provided, and the local vehicle waits at a position separated from an area over the load ports.

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

Abstract: A substrate carrier system is provided. The substrate carrier system includes a substrate carrier body, an electrode assembly, a support base, and a controller. The substrate carrier body has a substrate supporting surface, and an electrode assembly is disposed in the substrate carrier body. The electrode assembly includes a plurality of laterally spaced apart electrode sets. Each electrode set includes a first electrode interleaved with a second electrode. The support base supports the substrate carrier body. The controller is configured to: select a first group of the electrode sets and a second group of the electrode sets from the plurality of the electrode sets; operate the first group of the electrode sets in a first chucking mode; simultaneously operate the second group of the electrode sets in a second chucking mode; and selectively switch at least one electrode set from the first group to the second group.

Abstract: An electrostatic chuck device according to the present invention includes: an electrostatic chuck portion having a placement surface on which a plate-like sample is placed; a base portion for temperature adjustment disposed in opposition to the side of the electrostatic chuck portion on the opposite side from the placement surface; a bonding portion for bonding the electrostatic chuck portion and the base portion for temperature adjustment together; and an annular focus ring surrounding the periphery of the placement surface, in which the volume of a space surrounded by the electrostatic chuck portion, the focus ring, the bonding portion, and a dam portion of the base portion for temperature adjustment is greater than the amount of volume expansion of the bonding portion at the working temperature.

Abstract: An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.

Abstract: Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and extending along a second direction. Lines of the second set cross lines of the first set at cross-point locations. Memory structures are within the cross-point locations. Each memory structure includes a top electrode material, a bottom electrode material and a programmable material. Rails of insulative material extend parallel to the lines of the second set and alternate with the lines of the second set along the first direction. The programmable material has first regions within the memory structures and second regions over the rails of insulative material. A planarized surface extends across the lines of the second set and across the second regions of the programmable material. Some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

Abstract: A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming an etch stop layer over the source/drain features, and depositing a dielectric layer on the etch stop layer. The method further includes performing a first atomic layer etching (ALE) process having a first operating parameter value on the dielectric layer to form a first part of an opening, and performing a second ALE process having a second operating parameter value to extend the opening to expose the source/drain features. The first operating parameter value is different from the second operating parameter value.

Abstract: Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.

Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.

Abstract: Systems and methods may be provided for generating reduced-height circuit packages such as infrared detector packages. An alignment and dicing system may include an infrared camera that captures images of alignment marks of a wafer assembly through a lid wafer of the wafer assembly, a light source that illuminates the alignment marks through the lid wafer, and dicing equipment that dices the wafer assembly based on infrared images captured using the infrared camera. The light source may illuminate the alignment marks through the lid wafer by providing light such as infrared light to the wafer assembly through optics of the infrared camera. The infrared camera may capture images of alignment marks formed on a detector wafer of the wafer assembly or on an interior or lower surface of the lid wafer through the lid wafer. The dicing equipment may be aligned with the wafer assembly based on the captured images.

Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.

Abstract: According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. The method also includes detecting a second distance between a second portion of the substrate a second substrate information detection unit, the second portion different from the first portion. Distance information is calculated between the substrate and a processing lens, which is located farther from the second substrate information detection unit than from the first substrate information detection unit, based on the detected first distance and the detected second distance, and he substrate is irradiated with laser light from the processing lens based on the distance information.

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

Abstract: High-frequency thin film chip attenuators can include a substrate having a first side and a second side, a first portion coupled to the first side of the substrate, and a second portion coupled to the second side of the substrate. The first portion can include a ground section, an input contact section, and an output contact section. The second portion can include a ground section, an input section, an output section, and a plurality of resistive sections providing electrical communication between the input section, the output section, and the ground section. The resistive sections can be arranged in an attenuation configuration to attenuate a signal received at the input section and output via the output section. A plurality of through-holes extending through the substrate can provide electrical communication between sections on the first side of the substrate and associated sections on the second side of the substrate.

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure, a second final gate structure and an insulating gate separation structure positioned between the first and second final gate structures. In this example, the insulating gate separation structure comprises an upper portion and a lower portion. The lower portion has a first lateral width in a first direction that is substantially uniform throughout a vertical height of the lower portion. The upper portion has a substantially uniform second lateral width in the first direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a shallow trench isolation (STI) around the first fin-shaped structure; forming a first oxide layer on the first fin-shaped structure; and then forming a second oxide layer on the first oxide layer and the STI.

Abstract: At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.