Abstract: A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer.

Abstract: The present invention is directed to photovoltaic and photogalvanic devices and methods of generating electrical energy and power or detecting light therefrom, based on a novel nano-enhanced bulk photovoltaic effect using non-centrosymmetric crystals, including ferroelectric and piezoelectric materials, where the non-centrosymmetry is the equilibrium state or it is static or dynamically induced. In certain embodiments, the device comprises a layer of non-centrosymmetric crystalline materials, and a plurality of electrodes disposed in an array upon or penetrating into at least one surface of the crystalline material, the electrodes being optimally spaced to capture the ballistic carriers generated upon irradiation of the crystalline material.

Abstract: A method for the preparation of CIGS-type core-shell nanoparticles produces core-shell nanoparticles that may include a quaternary or ternary metal chalcogenide core. The core may be substantially surrounded by a binary metal chalcogenide shell. A core-shell nanoparticle may be deposited on a PV cell contact (e.g., a molybdenum electrode) via solution-phase deposition. The deposited particles may then be melted or fused into a thin absorber film for use in a photovoltaic device.

Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.

Abstract: Solar power generation system has at least one solar-array module. The solar cells in a solar-array module are interconnected in a crisscross matrix network configuration. The solar cells are a pre-sorted by the class of tolerance level of output power, such that the solar cells in each of the rows of solar cells are arranged in a steadily ascending (or steadily descending) order of the maximum power values that the solar cells are capable to provide, wherein the maximum power value of a solar cell in a particular row is higher or equal to the maximum power values of the previous (next, for steadily descending order) solar cells in the same row.

Abstract: Disclosed is a solar cell panel including a plurality of solar cells including a first solar cell and a second solar cell, and a wiring portion extending in a second direction crossing the first direction and electrically connecting the plurality of solar cells. Each of the plurality of solar cells includes a plurality of first electrodes and a plurality of second electrodes extending in a first direction. The wiring portion includes a first wiring connected to the plurality of first electrodes of the first solar cell, the first wiring includes a plurality of first partial wirings in the second direction in the first solar cell, and the plurality of first partial wirings are different members from each other and are electrically connected to each other by a first connection portion on the first solar cell.

Abstract: A photodetection element is a photodetection element having an incidence surface for light on a back surface of a semiconductor layer, and includes a periodic nano-concave/convex structure provided on a front surface of the semiconductor layer and having convex portions and concave portions constituting a longitudinal resonator and a transverse resonator for the light incident from the incidence surface, the periodic nano-concave/convex structure converting the light into surface plasmons, and a metal film provided to cover the periodic nano-concave/convex structure, a height and an arrangement pitch of the convex portions in the periodic nano-concave/convex structure are set such that a resonance wavelength of the longitudinal resonator and a resonance wavelength of the transverse resonator match, and a thickness of the metal film is equal to or greater than 20 nm.

Abstract: A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.

Abstract: An optoelectronic apparatus is provided having a carrier device that has at least one optoelectronic transmitter and/or at least one optoelectronic receiver at an upper side; having a lens element that is provided above the carrier device and that has at least one lens section for the at least one optoelectronic transmitter and/or for the at least one optoelectronic receiver; and having a holding device that at least partly surrounds the carrier device and the lens element. The lens element has a mechanical coding section that projects out of the holding device and that enables at least one coding element for identifying the optoelectronic apparatus.

Abstract: A proximity detector device may include a first interconnect layer including a first dielectric layer, and first electrically conductive traces carried thereby, an IC layer above the first interconnect layer and having an image sensor IC, and a light source IC laterally spaced from the image sensor IC. The proximity detector device may include a second interconnect layer above the IC layer and having a second dielectric layer, and second electrically conductive traces carried thereby. The second interconnect layer may have first and second openings therein respectively aligned with the image sensor IC and the light source IC. Each of the image sensor IC and the light source IC may be coupled to the first and second electrically conductive traces. The proximity detector device may include a lens assembly above the second interconnect layer and having first and second lenses respectively aligned with the first and second openings.

Abstract: A method and system for drying paste for a solar cell are disclosed. The method includes the following steps: delivering a solar cell to a position below a laser; detecting position information of the solar cell; and starting the laser to emit a laser beam for drying the solar cell according to the position information.

Abstract: The present disclosure provides an apparatus for manufacture of at least two solar cell arrangements. The apparatus includes a separation device configured for separating a first solar cell into two or more first solar cell solar cell pieces, and at least one positioning device configured for positioning at least one first solar cell piece of the two or more first solar cell pieces on a support device for forming a first solar cell arrangement of the at least two solar cell arrangements and for positioning at least one other first solar cell piece of the two or more first solar cell pieces on the support device for forming a second solar cell arrangement of the at least two solar cell arrangements.

Abstract: A method for soldering hetero-junction with intrinsic thin layer solar cells together to form a string, includes soldering solar cells, and judging whether a temperature in a soldering chamber is within a preset temperature range every preset time; if the temperature is within the preset temperature range, continuing to solder; and if the temperature is beyond the preset temperature range, regulating the temperature in the soldering chamber to be within the preset temperature range, and continuing to solder the solar cells.

Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, method of manufacturing a micro-light emitting diode (LED) display panel includes positioning a display backplane substrate in a tank or container, the display backplane substrate having microgrooves therein. The method also includes adding a fluid to the tank or container, the fluid including a suspension of light-emitting diode (LED) pixel elements therein. The method also includes moving the fluid over the display backplane substrate. The method also includes assembling LED pixel elements from the fluid into corresponding ones of the microgrooves.

Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, a method of manufacturing a micro-light emitting diode (LED) display panel includes positioning a carrier plate above a display backplane substrate, the carrier plate having a plurality of light-emitting diode (LED) pixel elements thereon, and the display backplane substrate having a plurality of metal bumps thereon. The method also includes moving the carrier plate toward the display backplane substrate to couple at least a portion of the plurality of LED pixel elements to corresponding ones of the plurality of metal bumps, applying pressure to the carrier plate to transfer and bond the portion of the plurality of LED pixel elements to the corresponding ones of the plurality of metal bumps, and, subsequently, separating the carrier plate from the display backplane substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniform semiconductor nanowire and nanosheet light emitting diodes and methods of manufacture. The structure includes a buffer layer; at least one dielectric layer on the buffer layer, the at least one dielectric layer having a plurality of openings exposing the buffer layer; and a plurality of uniformly sized and shaped nanowires or nanosheets formed in the openings and extending above the at least one dielectric layer.

Abstract: A light emitting device can include a substrate including first and second surfaces, the substrate having a thickness of less than 350 micrometers; a reflective layer on the second surface of the substrate; a light emitting structure on the first surface of the substrate and including first and second semiconductor layers with an active layer therebetween, the second semiconductor layer includes an aluminum-gallium-nitride layer, and the active layer includes aluminum and indium and has a multiple quantum well layer; a transparent conductive layer disposed on the second semiconductor layer and including an indium-tin-oxide; a first electrode on the first semiconductor layer and including multiple layers; a second electrode on the transparent conductive layer and including multiple layers; first and second pads on the first and second electrodes, respectively, in which the second pad includes the same material as the first pad and has a thickness of more than 500 nanometers.

Abstract: Patterned substrates and optoelectronic devices (UV laser diode, UV LED, and sensors grown on silicon substrate) formed on these patterned substrates are described. The method of making patterned substrates are described. Examples of making laser diodes on these patterned substrates described in detail. The PSs can be fabricated by either combination of e-beam lithography and wet-chemical etching or combination of e-beam lithography and dry etching or through Nanoimprint transfer of master mold patterns to various wafers followed by etching.

Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a first color nanowire LED, a second color nanowire LED, the second color different than the first color, and a pair of third color nanowire LEDs, the third color different than the first and second colors. A continuous insulating material layer ius laterally surrounding the first color nanowire LED, the second color nanowire LED, and the pair of third color nanowire LEDs.

Abstract: An LED panel is disclosed. The LED panel includes LED chips and a mount substrate on which the LED chips are mounted by flip bonding. Each of the LED chips includes a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells. Each of the LED chips includes a plurality of color cells formed corresponding to the plurality of light emitting cells on the sapphire substrate to change or maintain the color of light from the corresponding light emitting cells and a plurality of light collecting portions formed corresponding to the plurality of light emitting cells and the plurality of color cells on the bottom surface of the substrate and adapted to collect light from the corresponding light emitting cells on the corresponding color cells.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.

Abstract: Disclosed in an embodiment is a light emitting device comprising: a substrate; a light emitting structure, which includes a first semiconductor layer, an active layer, a second semiconductor layer, and a first groove penetrating through the second semiconductor layer and the active layer and disposed up until a partial region of the first semiconductor layer; a reflective electrode layer covering a lower part of the second semiconductor layer and a sidewalls of the first groove; a first ohmic electrode disposed inside the first groove and electrically connected to the first semiconductor layer; and a first insulation layer for electrically insulating the first ohmic electrode and the reflective electrode layer.

Abstract: A light emitting device includes a semiconductor layer, and a light emitting layer disposed in the semiconductor layer and having a composition ratio of Ga(1-x)InxN. x is greater than 0.14 but less than 0.16 to emit a green light from the light emitting layer, or greater than 0.22 but less than 0.26 to emit a blue light from the light emitting layer.

Abstract: An LED module for increasing effective wavelengths output includes a light emission unit configured to be supplied with electric energy to generate light; and a frame unit where an installation space for installing the light emission unit is formed, and that absorbs electromagnetic waves being generated in the light emission unit. During operation, harmful electromagnetic waves other than the effective waves beneficial to human body may be absorbed. Accordingly, even when the human body is exposed to the LED module for a long period of time, the side effects caused by the electromagnetic waves can be minimized.

Abstract: A light-emitting device and method of producing a white appearance for a light-emitting device in an off-state are disclosed. The device includes a supporting member, an organic light emitting diode (OLED) disposed on the supporting member and a color conversion layer disposed on the OLED. The color conversion layer comprises phosphor and has a non-white appearance under ambient light when the device is in an off-state. The device further includes one or more whitening layers that have a plurality of whitening particles configured to reduce the absorption of ambient light by the color conversion layer and produce a white appearance for the device in the off-state under ambient light.

Abstract: Provided is a light-emitting device including a mount board, an LED element mounted on the mount board, and a translucent or transparent sealing resin being filled onto the mount board to seal the LED element. The sealing resin contains first and second particulate phosphors excited by emitted light from the LED element, and a nanoscale filler having an average particle size in the range of 1 nm to 100 nm. The specific gravity of the first particulate phosphor is smaller than that of the second particulate phosphor. The sealing resin includes a dispersion layer of the first particulate phosphor covering areas obliquely above and beside the LED element, and a deposition layer of the second particulate phosphor on upper surfaces of the mount board and the LED element. The first particulate phosphor is dispersed in the dispersion layer among aggregates formed by particles of the nanoscale filler.

Abstract: The invention relates to an optoelectronic component (100) comprising a semiconductor chip (1) configured for emitting radiation, a conversion element (2) comprising quantum dots (5) and configured for wavelength conversion of radiation, wherein the conversion element (2) comprises a layer structure (7) having a plurality of inorganic barrier layers (31, 32, 33, 34), wherein the inorganic barrier layers (31, 32, 33, 34) are spatially separated from one another at least regionally by a hybrid polymer (4), wherein the hybrid polymer (4) comprises organic and inorganic regions that are covalently bonded to one another, wherein the quantum dots (5) are embedded in the hybrid polymer (4) and/or at least in one of the barrier layers (31, 32, 33, 34).

Abstract: An electronic device package includes a substrate, an electronic device, and a first packaging layer. The electronic device and the first packaging layer are disposed on the substrate and the electronic device is located between the substrate and the first packaging layer. The first packaging layer includes a first oxynitride layer and a second oxynitride layer, wherein the second oxynitride layer is located between the first oxynitride layer and the electronic device. A composition of the first oxynitride layer includes SiNx1Oy1, a composition of the second oxynitride layer includes SiNx2Oy2, and x1>x2.

Abstract: A light emitting diode package includes: at least one light emitting diode chip; a housing on which the at least one light emitting diode chip is mounted, the housing being open at at least one surface thereof to allow light emitted from the at least one light emitting diode chip to be discharged through the open surface of the housing; and a plurality of pads disposed on a second surface of the housing different from a first surface of the housing through which light is discharged, the plurality of pads being electrically connected to the at least one light emitting diode chip, wherein the housing has a plurality of grooves formed on a third surface thereof adjacent to the second surface.

Abstract: An LED structure includes a substrate, an LED chip disposed on the substrate, a wavelength conversion layer disposed above a light-emitting surface of the LED chip, and a cut-on optical filter disposed on a central region of the wavelength conversion layer.

Abstract: Solid state lighting (SSL) devices and methods of manufacturing SSL devices are disclosed herein. In one embodiment, an SSL device comprises a support having a surface and a solid state emitter (SSE) at the surface of the support. The SSE can emit a first light propagating along a plurality of first vectors. The SSL device can further include a converter material over at least a portion of the SSE. The converter material can emit a second light propagating along a plurality of second vectors. Additionally, the SSL device can include a lens over the SSE and the converter material. The lens can include a plurality of diffusion features that change the direction of the first light and the second light such that the first and second lights blend together as they exit the lens. The SSL device can emit a substantially uniform color of light.

Abstract: The invention comprises a solid state infrared source and method of use thereof comprising: (1) an electrically conductive film, comprising a semi-transparent material, the semi-transparent material comprising a transmission property of at least forty percent, wherein at least forty percent of internal infrared emissions from the electrically conductive film transmit to an outer surface of the electrically conductive film, wherein the infrared emissions comprise a peak intensity between 3.9 and 6 micrometers; (2) a first silicon nitride layer; and (3) a second silicon nitride layer, the electrically conductive film positioned between the first silicon nitride layer and the second silicon nitride layer, where applying an electric current of less than one Watt through the electrically conductive film raises a temperature of the electrically conductive film to in excess of eight hundred degrees centigrade in less than twenty milliseconds resultant in the infrared emissions.

Abstract: A light emitting element is disclosed. The light emitting element includes: an LED chip including a light emitting semiconductor stack and first and second electrode pads disposed under the light emitting semiconductor stack and spaced apart from each other; a substrate mounted with the LED chip and including a first electrode corresponding to the first electrode pad and a second electrode corresponding to the second electrode pad; a first solder portion connecting the first electrode pad and the first electrode; and a second solder portion connecting the second electrode pad and the second electrode. The first solder portion and the second solder portion are formed without escaping from the mounting area of the LED chip on the substrate by heating a solder material to its melting point or above with an IR laser.

Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Abstract: A thermoelectric conversion module which is obtained by connecting a plurality of thermoelectric conversion elements via a pair of wiring substrates facing each other in such a state that the thermoelectric conversion elements are combined with each other between the wiring substrates: each of the wiring substrates is obtained by forming an electrode layer on one surface of a ceramic substrate, the electrode layer being connected to the thermoelectric conversion elements and being formed of aluminum or an aluminum alloy: at least the electrode layer that is arranged on the high-temperature side is provided with a silver base layer, in which a glass layer and a silver layer are laminated in the surface; and the silver layer of the silver base layer is bonded to the thermoelectric conversion elements.

Abstract: A method and system for using a method of pre-equilibrium ballistic charge carrier refraction comprises fabricating one or more solid-state electric generators. The solid-state electric generators include one or more of a chemically energized solid-state electric generator and a thermionic solid-state electric generator. A first material having a first charge carrier effective mass is used in a solid-state junction. A second material having a second charge carrier effective mass greater than the first charge carrier effective mass is used in the solid-state junction. A charge carrier effective mass ratio between the second effective mass and the first effective mass is greater than or equal to two.

Abstract: Micro-scale thermoelectric devices having high thermal resistance and efficiency for use in cooling and energy harvesting applications and relating fabricating methods are disclosed. The thermoelectric devices include first substrates substantially parallel with second substrates. Scaffold members are deposited between the first and second substrate. The scaffold members include a plurality of cavities having sidewalls. The scaffold members may be formed from the second substrate. The sidewalls are substantially vertical with respect to the second substrate. The sidewalls may be substantially parallel. Thermoelectric materials are deposited on the sidewalls.

Abstract: A method for forming a unique, environmentally-friendly micron scale autonomous electrical power source is provided in a configuration that generates renewable energy for use in electronic systems, electronic devices and electronic system components. The configuration includes a first conductor with a facing surface conditioned to have a low work function, a second conductor with a facing surface having a comparatively higher work function, and a dielectric layer, not more than 200 nm thick, sandwiched between the respective facing surfaces of the first conductor and the second conductor. The autonomous electrical power source formed according to the disclosed method is configured to harvest minimal thermal energy from any source in an environment above absolute zero.

Abstract: The present invention is a room temperature superconductor comprising of a wire, which comprises of an insulator core and a metal coating. The metal coating is disposed around the insulator core, and the metal is coating deposited on the core. When a pulsed current is passed through the wire, while the wire is vibrated, room temperature superconductivity is induced.

Abstract: The present disclosure provides a piezoelectric sensor, a pressure detecting device, their manufacturing methods and a detection method. The piezoelectric sensor comprises a thin film transistor located on a substrate and comprising an active layer, and a piezoelectric layer that is in contact with the active layer of the thin film transistor.

Abstract: Described herein is the use of large phase transformational strain in relaxor ferroelectric single crystals for broadband sound generation. The technique exploits the thermo-optical triggering and thus an opto-acoustic effect of ferroelectric phase transformation piezocrystals under mechanical bias conditions.

Abstract: A dielectric polymer, methods of making the dielectric polymer, and uses thereof (e.g. piezoelectric sensors and/or actuators) are described. The dielectric polymer includes a polymeric matrix (e.g. a copolymers of styrene and acrylonitrile SAN, or a terpolymer of the former with methyl methacrylate MMA-SAN) derived from at least one polymerizable vinyl monomer and an ionic liquid that includes an organic cation and a balancing anion (e.g. 1-butyl-3-methylimidazolium hexafluorophosphate BMMMPF6). The ionic liquid is compatible with the at least one polymerizable vinyl monomer and the concentration of the ionic liquid in the dielectric polymeric composition ranges from 0.5 wt. % to less than 30 wt. %.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A magnetic artificial honeycomb lattice comprising a multiplicity of connecting elements separated by hexagonal cylindrical pores, wherein: (a) the hexagonal cylindrical pores: (i) have widths that are substantially uniform and an average width that is in a range of about 15 nm to about 20 nm; and (ii) are substantially equispaced and have an average center-to-center distance that is in a range of about 25 nm to about 35 nm; and (b) the connecting elements comprise a magnetic material layer, and the connecting elements have: (i) lengths that are substantially uniform and an average length that is in a range of about 10 nm to about 15 nm; (ii) widths that are substantially uniform and an average width that is in a range of about 4 nm to about 8 nm; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness that is in a range of about 2 nm to about 8 nm; and (c) the magnetic artificial honeycomb lattice has a surface area, disregarding the presence of th

Abstract: A spin-current magnetization rotational element includes: a ferromagnetic metal layer; and a spin-orbit torque wiring that extends in a first direction intersecting a stacking direction of the ferromagnetic metal layer and is bonded to the ferromagnetic metal layer. A direction of a spin injected into the ferromagnetic metal layer from the spin-orbit torque wiring intersects a magnetization direction of the ferromagnetic metal layer. The ferromagnetic metal layer has shape anisotropy and has a demagnetizing field distribution caused by the shape anisotropy. The demagnetizing field distribution generates an easy magnetization rotational direction in which the magnetization of the ferromagnetic metal layer is most easily reversed. The easy magnetization rotational direction intersects the first direction in a plan view seen from the stacking direction.

Abstract: In one embodiment, a SOT device provides current-induced perpendicular magnetization switching in a single magnetic layer, such as a L10-ordered magnetic alloy layer of FePt alloy, CoPt alloy, FePd alloy or another atomically layered magnetic alloy. The SOT may originate from the large spin orbit coupling in these alloys. Depending on the implementation, the SOT device may take the form of a SOT-MRAM, a spin memristor, a current-assisted magnetic recording media, or other type of device.

Abstract: In one embodiment, a SOT device is provided that replaces a traditional NM layer adjacent to a magnetic layer with a NM layer that is compatible with CMOS technology. The NM layer may include a CMOS-compatible composite (e.g., CuPt) alloy, a TI (e.g., Bi2Se3, BixSe1-x, Bi1-xSbx, etc.) or a TI/non-magnetic metal (e.g., Bi2Se3/Ag, BixSe1-x/Ag, Bi1-xSbx/Ag, etc.) interface, that provides efficient spin current generation. Spin current may be generated in various manners, including extrinsic SHE, TSS or Rashba effect.

Abstract: There is disclosed an information storage element including a first layer including a ferromagnetic layer with a magnetization direction perpendicular to a film face; an insulation layer coupled to the first layer; and a second layer coupled to the insulation layer opposite the first layer, the second layer including a fixed magnetization so as to be capable of serving as a reference of the first layer. The first layer is capable of storing information according to a magnetization state of a magnetic material, and the magnetization state is configured to be changed by a spin injection. A magnitude of an effective diamagnetic field which the first layer receives is smaller than a saturated magnetization amount of the first layer.

Abstract: An embodiment includes a programmable metallization cell (PMC) memory comprising: a top electrode and a bottom electrode; a metal layer between the top and bottom electrodes; and a solid electrolyte (SE) layer between the metal layer and the bottom electrode; wherein (a) the metal layer includes an alloy of first and second metals, and (b) metal ions from the first metal form a conductive path in the SE layer when the top electrode is positively biased and disband the conductive path when the top electrode is negatively biased. Other embodiments are described herein.

Abstract: A method for producing a memory cell includes providing a non-conductive substrate, mounting a first conductor track made of conductive material on the non-conductive substrate, mounting a porous dielectric with or without redox-active molecules in a form of points on the first conductor track, and mounting a second conductor track orthogonally to the first conductor track, wherein the first and second conductor tracks have an electrode function at their intersection point, and wherein the porous dielectric is arranged between the electrodes. The method further includes mounting a passivation layer on the substrate, the first conductor track, the dielectric, and the second conductor track, so that the conductor track remains contactable. The first and the second conductor track form a memory at their intersection point with the dielectric arranged between them, in which the redox reaction of the redox-active molecules is configured to be driven by a voltage.