Abstract: A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.

Abstract: A device including a capacitor includes an isolation structure, a first control gate, a first selective gate and a first dielectric layer. The isolation structure is disposed in a substrate. The first control gate and the first selective gate are disposed directly above the isolation structure. The first dielectric layer is vertically sandwiched by the first control gate and the first selective gate, thereby constituting the capacitor. The present invention also provides a method of forming the device including the capacitor.

Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

Abstract: A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator (SOI) substrate is disclosed. The split gate memory cell includes a split gate disposed on a surface substrate of the SOI substrate between source/drain (S/D) regions. The split gate includes a storage gate with a control gate (CG) over a floating gate (FG), and a select gate (SG). A back gate is provided on the bulk substrate below a buried oxide (BOX). The back gate may be doped with the same polarity type dopants as the S/D regions. The back gate is coupled to the CG to increase CG coupling ratio, improving programming performance. Alternatively, the back gate may be doped with the opposite polarity type dopants as the S/D regions. The back gate is coupled to a negative bias during program and erase operations.

Abstract: Provided are a semiconductor storage element, a semiconductor device, an electronic device, and a manufacturing method of a semiconductor storage element that enable higher-speed operations. The semiconductor storage element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type that is provided below the first semiconductor layer; a gate electrode provided on the first semiconductor layer; a gate insulator film provided between the first semiconductor layer and the gate electrode; a drain region of the second conductivity type that is provided in the first semiconductor layer on one side of the gate electrode; a source region of the second conductivity type that is provided in the first semiconductor layer on another side facing the one side across the gate electrode; and a bit line configured to electrically connect with both of the source region and the first semiconductor layer.

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Abstract: A semiconductor device includes a semiconductor substrate, a stacked body, a transistor, first and second silicon oxides, and a first silicon nitride film. The semiconductor substrate includes a cell region. The stacked body is provided in the cell region and included in a memory cell array. The transistor is disposed on the semiconductor substrate between the stacked body and an edge portion of the semiconductor substrate. The first silicon oxide film surrounds the stacked body and is disposed between the stacked body and the transistor. The second silicon oxide film surrounds the first silicon oxide film, is separated from the first silicon oxide film, and is disposed between the edge portion and the first silicon oxide film. The first silicon nitride film includes a portion provided on the substrate in a first region. The portion surrounds the stacked body.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit.

Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials.

Abstract: The present invention provides an array substrate and a manufacturing method thereof. The array substrate includes: a base substrate; a TFT on the base substrate, a data line electrically connected with a source of the TFT, a transparent conductive layer between the data line and the pixel electrode, a pixel electrode electrically connected with a drain of the TFT, wherein the data line and the pixel electrode are set on different layers, and the data line, the transparent conductive layer, and the pixel electrode are laminated and insulating to each other. It reduces electric field interference generated by the data line to the pixel electrode by the array substrate of the present invention.

Abstract: A pixel unit includes a thin film transistor, a first insulating layer, a pixel electrode, a second insulating layer, a meltable conductive component, and a common electrode. The thin film transistor includes a drain electrode. The first insulating layer is arranged over the drain electrode. The pixel electrode is arranged over the first insulating layer and electrically coupled to the drain electrode. The second insulating layer is arranged over the pixel electrode. The meltable conductive component is arranged over the second insulating layer. The common electrode is arranged over the meltable conductive component and electrically coupled to the meltable conductive component.

Abstract: A gate driver circuit and a display device using the same are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node.

Abstract: An array substrate and a display device are disclosed. The array substrate includes: a base substrate; and a first electrically conductive layer and a second electrically conductive layer on the base substrate; wherein the base substrate is provided with at least one TFT, each of the at least one TFT includes a gate electrode disposed in the first electrically conductive layer, and a source electrode and a drain electrode disposed in the second electrically conductive layer; and wherein, at least one of the drain electrode and the source electrode includes an electrode body and an extending portion, the electrode body overlapping with the gate electrode, and the extending portion overlapping with a portion of the first electrically conductive layer other than the gate electrode.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

Abstract: The disclosure discloses an improving method of bending display abnormality of a flexible display, including the following steps: detecting a characteristic parameter of a driving thin film transistor of each of pixels in the flexible panel during display bending; calculating a bending position of the flexible panel according to the characteristic parameter of the driving thin film transistor of each of pixels; performing image visual correction on an image displayed by the pixels located at the bending position of the flexible panel. The disclosure also discloses an improving device of display bending abnormality of a flexible display and a flexible display. In the disclosure, when the flexible display is displayed in a bent state, the pixels located at the bending position are corrected to improve the display abnormality, thereby enhancing the display quality.

Abstract: An array substrate and a display device are provided in the embodiments of the disclosure. The array substrate includes: a substrate; thin film transistors formed on the substrate, each of the thin film transistors comprising a gate electrode, a gate insulation layer, an active layer; and a source electrode and a drain electrode; a protective layer formed on the thin film transistors, having through-holes formed therein; and lead-out electrodes; and at least one support is provided below the through-holes, each of the through-holes being configured to form an electrical connection between the drain electrode in each of the thin film transistors and a corresponding one of the lead-out electrodes, an orthogonal projection of each of the through-holes on the substrate falling within an orthogonal projection of the at least one support on the substrate.

Abstract: A flexible display device includes a substrate and a border unit. The substrate has a display area and a border area that surrounds the display area. The border unit is located in the border area and includes a first metal layer on the substrate, an insulation layer covering the first metal layer and the substrate, a second metal layer on the insulation layer, a protection layer covering the second metal layer and the insulation layer, a semiconductor layer between the insulation layer and the protection layer, a planarization layer covering the protection layer, and a third metal layer on the planarization layer. The third metal layer has a first part, a second part, and a third part that is between and physically connected to the first and second parts. A notch is defined by the first, second, and third parts.

Abstract: The present application provides an array substrate and a method of manufacturing the same. The array substrate includes a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer.

Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.

Abstract: The invention provides a forming method of a via hole, including: sequentially stacking a patterned first conductive layer, a first insulating layer, a patterned second conductive layer, and a second insulating layer on a substrate. The second conductive layer and the first conductive layer overlap in a normal direction of the substrate, such that the second insulating layer has a protrusion portion protruding away from the substrate. A photosensitive material layer covers the second insulating layer. The photosensitive material layer is exposed, wherein a depth of exposure is equal to a vertical distance from a top surface of the protrusion portion to a surface of the photosensitive material layer. The exposed photosensitive material layer is removed by development to form a first via hole exposing the second insulating layer. The exposed second insulating layer is etched to form a second via hole to expose the second conductive layer, and then the photosensitive material layer is removed.

Abstract: The present disclosure provides a multispectral imaging device, comprising the following layers and components arranged in sequence following a direction of incident light: a color filter layer, comprising a plurality of color filters transparent for specific wavebands; a first transparent electrode layer continuously formed in imaging area; a first conversion layer continuously formed in imaging area to convert visible light to electric signals; a first flat topography comprising plurality of pixel electrodes and with surface roughness less than 5 nm; a second conversion layer to convert NIR light to electric signals; and circuit components to process the electric signals. Benefit from the first continuous conversion layer formed on the flat topography, high light utilization, low spectral cross-talk, low dark current are achieved in the multispectral imaging device.

Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.

Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided.

Abstract: A semiconductor device includes: a photodiode formed in a substrate; and at least one transistor having a gate feature that comprises a first portion and a second portion coupled to an end of the first portion, the first portion disposed above and extending along a major surface of the substrate and the second portion extending from the major surface of the substrate into the substrate, wherein the photodiode and the at least one transistor at least partially form a pixel.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically connected to the substrate and the sensor chip, a transparent layer facing the sensor chip, a support disposed on the substrate, and a packaging compound disposed on the substrate and covering side edges of the support and the transparent layer. A part of each wire is embedded in the support. A height from the upper surface of the substrate to the top of the support is larger than a height from the upper surface of the substrate to the top of any of the wires. The bottom surface of the transparent layer has a central region facing the sensor chip and a ring-shaped supporting region surrounded by the central region. The support is arranged outside the sensor chip and abuts against the supporting region.

Abstract: A method for forming an image sensor includes: providing a first device including a visible light receiving portion and an infrared receiving portion; coating a first infrared cutoff filter on the first device; patterning plural photoresists on the first infrared cutoff filter located in the visible light receiving portion to form a second device; etching the second device until a first filter of the first device is exposed to form an infrared cutoff filter and an infrared cutoff filter grid located in the visible light receiving portion, in which the infrared cutoff filter grid is located on the infrared cutoff filter; filling a color filter in the infrared cutoff filter grid and forming a second filter on the first filter; and disposing a spacer layer and a micro-lens layer on the color filter and the second filter sequentially.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Abstract: Embodiments relate to a stacked photo sensor assembly where two substrates that are stacked vertically. The two substrates are connected via interconnects at a pixel level to provide a signal from a photodiode at a first substrate to circuitry on a second substrate. The circuitry on the second substrate performs operations that were conventionally performed on first substrate. By stacking the first and second substrates, the photo sensor assembly can be made more compact while increasing or at least retaining the photodiode fill factor of the photo sensor assembly.

Abstract: A semiconductor device disclosed includes a semiconductor substrate, an electrode layer arranged over the semiconductor substrate, and a conductive member provided in an opening and electrically connected to the electrode layer, and the opening penetrates the semiconductor substrate and reaches the electrode layer. The conductive member includes a metal portion and a barrier metal portion provided between a side surface of the opening and the metal portion, the barrier metal portion includes a first layer and a second layer provided between the first layer and the metal portion, and the second layer is denser than the first layer.

Abstract: A semiconductor device of the present disclosure includes: a semiconductor element disposed on a first surface side of a semiconductor substrate; a through-electrode that is provided through the semiconductor substrate in a thickness direction of the semiconductor substrate and introduces charge obtained in the semiconductor element to a second surface side of the semiconductor substrate; and an amplifier transistor that outputs an electrical signal based on the charge introduced by the through-electrode, the amplifier transistor using the through-electrode as a gate electrode and including a source region and a drain region around the through-electrode.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.

Abstract: An imaging device comprises a first pixel disposed in a substrate. The first pixel may include a first material disposed in the substrate, and a second material disposed in the substrate. A first region of the first material, a second region of the first material, and a third region of the second material form at least one junction. A first lateral cross section of the substrate intersects the at least one junction, and a second lateral cross section of the substrate intersects at least one fourth region of the first material.

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Abstract: The present disclosure relates to an X ray flat panel detector and a fabrication method thereof. The X ray flat panel detector comprises: a substrate; a thin film transistor disposed on the substrate and configured to output a sensed signal; an insulating layer covering the thin film transistor; a photosensitive device disposed on the insulating layer to have a vertical shift with respect to the thin film transistor, and configured to absorb visible light through a quantum dot film and convert the visible light into a sensed signal; and a scintillating layer disposed on the photosensitive device and configured to convert X rays into the visible light.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.

Abstract: A light emitter device includes a submount with a top surface and a bottom surface, electrically conductive traces on the top surface of the submount, light emitting diodes (LEDs) arranged on the top surface of the submount in light emitter zones, with the LEDs being electrically connected to respective traces of the traces, a retention material disposed over the top surface of the submount in a form of walls which physically separate the light emitter zones, and encapsulants that are dispensed in respective light emitter zones of the light emitter zones. A least a portion of the plurality of walls of the retention material can comprise a translucent material, a reflective material, and/or a light-absorbing material. The LEDs are individually addressable to independently control an output of light from each of the LEDs to produce a specified light output.

Abstract: An electrically-powered device, structure and/or component is provided that includes an attached electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. The energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase an electrical power output.

Abstract: An integrated circuit is provided that comprises a resistor, a first superconducting structure coupled to a first end of the resistor, and a second superconducting structure coupled to a second end of the resistor. A thermally conductive heat sink structure is coupled to the second end of the resistor for moving hot electrons from the resistor prior to the electrons generating phonons.

Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.

Abstract: The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.

Abstract: A semiconductor device includes a semiconductor layer, first gate electrode, second gate electrode, first conductive layer and second conductive layer. The semiconductor layer includes a first side surface, a second side surface, a first end portion, and a second end portion. The first side surface and the second side surface face each other. The first end portion and the second end portion face each other. A first gate insulating layer is provided between the first gate electrode and the first side surface. A second gate insulating layer is provided between the second gate electrode and the second side surface. A first metal oxide layer is provided between the first conductive layer and the first end portion. A second metal oxide layer is provided between the second conductive layer and the second end portion.

Abstract: A method of manufacturing an integrated circuit system, includes, in part, providing a planar surface on an insulator, forming first and second bottom electrodes over the insulator substrate, forming a first electrolyte over the first and second bottom electrodes, forming a first top electrode over the first electrolyte, forming and depositing a second bottom electrode over the insulator substrate, patterning and removing the first top electrode and the first electrolyte from regions above the second bottom electrode, forming a second electrolyte above the second bottom electrode and the first tope electrode, forming a second top electrode above the second electrolyte, and patterning and removing the second top electrode and the second electrolyte from regions above the first bottom electrode.

Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.

Abstract: A photosensitive laminate (121) includes an optically clear polymer film (123) comprising a thermoplastic polymer, and further having a first surface (124) and a second surface (125) opposite the first surface. An organic image sensor layer (126) disposed on at least a portion of the first surface (124) of the optically clear polymer film. A glass layer (122) is laminated directly onto the organic image sensor layer (126) and the first surface (124) of the optically clear polymer film, wherein no adhesive is disposed between the first surface of the optically clear polymer film (124) and the glass layer (122). A method of manufacturing the photosensitive laminate and image sensor devices are also described.

Abstract: An OLED display panel includes a cover and a backplane, a plurality of color filter (CF) units are arranged in an array on the cover; auxiliary cathodes are filled into gaps among the CF units; the auxiliary cathodes include a black matrix, a buffer layer and a metal layer; a planarization layer is disposed on the auxiliary cathodes and the CF units; a plurality of openings are disposed in the planarization layer at locations corresponding to the auxiliary cathodes; a plurality of spacers are disposed on the planarization layer at locations corresponding to the auxiliary cathodes; the spacers abut against and support the cover and the backplane; a transparent electrode layer is disposed on the planarization layer and the spacers and is communicated with the auxiliary cathodes via the openings; and the plurality of CF units of the cover and pixel regions of the backplane are oppositely arranged.

Abstract: The display panel includes a light emitting device, three quantum dot converters including quantum dot particles and converting light of a first color emitted from the light emitting device to light of a different color and emitting the light of the different color, a transmission part transmitting light of the first color emitted from the light emitting device, and a transparent substrate disposed on one side of the three quantum dot converters and the transmission part. One of the three quantum dot converters emits a white light to the transparent substrate.

Abstract: A display device includes an input sensing unit having a plurality of sensing electrodes, a plurality of signal lines each of which is connected to a corresponding one of the plurality of sensing electrodes, and a plurality of sensing pads each of which each is connected to a corresponding one of the plurality of signal lines. The sensing pads are arranged in a non-linear configuration, such as a plurality of rows when viewed in a plan view.

Abstract: An electroluminescent display device includes a substrate on which first and second pixel regions are defined, a passivation layer over the substrate, a first electrode in each of the first and second pixel regions on the passivation layer, a bank layer exposing the first electrode, a light emitting layer on the first electrode exposed by the bank layer, and a second electrode on the light emitting layer, further the bank layer includes first and second openings exposing the first electrodes corresponding to the first and second pixel regions, respectively, and also a depth of the second opening is larger than a depth of the first opening, and a height of the bank layer of the second pixel region is larger than a height of the bank layer of the first pixel region.

Abstract: An organic light emitting display device, includes a plurality of pixels, each of the plurality of pixels including at least one red sub pixel, at least one green sub pixel, and at least one blue sub pixel, wherein red sub pixels and blue sub pixels of adjacent pixels are aligned in a first direction and are also aligned in a second direction, the second direction being a direction that intersects the first direction, wherein green pixels of adjacent pixels are aligned in the first direction and are also aligned in the second direction, wherein the at least one green sub pixel of each pixel is disposed between the at least one red sub pixel and the at least one blue sub pixel of the each pixel, and wherein the at least one green sub pixel is offset from the at least one red sub pixel and the at least one blue sub pixel in the first direction and the second direction in the each pixel.