Abstract: A pixel array, a method for fabricating the same, and an OLED array substrate are disclosed. The pixel array includes a plurality of pixels, wherein each pixel includes four sub-pixels, the four sub-pixels are of the same size and all in a shape of isosceles trapezoid, and the four sub-pixels are arranged into a form of half of a regular hexagon. A display panel having the above structure has a better rotational symmetry, as a result, a high resolution and homogeneity can be achieved for each direction of the display panel.

Abstract: The present application discloses an organic light emitting device. The organic light emitting device includes a first electrode; an organic layer an the first electrode, the organic layer having an organic light emitting layer; a second electrode on a side of the organic layer distal to the first electrode; an electrochromic layer between the first electrode and the organic layer; and a third electrode between the electrochromic layer and the organic layer.

Abstract: The present invention is related to a method of fabricating a film. The method may comprise filling ink droplets containing a solvent and material constituting the film into pixel units of an array substrate; freezing the ink droplets on the array substrate; and sublimating the solvent of the ink droplets on the array substrate. The pixel units of the array substrate may be separated by a pixel define layer and arranged in a matrix.

Abstract: A transparent display device including a substrate having a light emitting region and a light transmitting region, a light emitting element located in the light emitting region, a first wall structure having an undercut sidewall, a first top conductive pattern and a barrier multi-layer structure is provided. The first wall structure forms the boundary between the light emitting region and the light transmitting region and the light emitting element is located in the light emitting region surrounded by the first wall structure. The first top conductive pattern is disposed on the top surface of the first wall structure. The barrier multi-layer structure is disposed on the light emitting element. The barrier multi-layer structure includes a first barrier layer and a second barrier layer. An overlapping portion of the first barrier layer and the second barrier is located in the light emitting region surrounded by the first wall structure.

Abstract: Disclosed is an organic light-emitting display device, in which a compensation pattern is selectively provided between two dam patterns depending on the arrangement density of a lower structure thereof, thereby making the width of a seal pattern uniform for each area. As a result, the reliability of the device is greatly improved.

Abstract: An organic light emitting display device includes: an insulating layer; first electrodes on the insulating layer and spaced from each other by a gap; an organic light emitting layer on the first electrodes; and a second electrode on the organic light emitting layer, wherein the insulating layer includes a trench between the first electrodes, wherein the organic light emitting layer includes a first stack on the first electrodes, a charge generating layer on the first stack, and a second stack on the charge generating layer, wherein each of the first and second stacks includes a hole transporting layer, at least one emitting material layer and an electron transporting layer, and wherein the first stack has a discontinuous portion in the trench.

Abstract: The display device including a pixel circuit has a first line, a transistor, a light emitting element, and a second line. The transistor is located between the second line and an electrode of the light emitting element. Either the first line or the second line is wired in a region that overlaps a light emitting region of the light emitting element in a lamination direction of layers. The second line intersects the first line outside of the light emitting region and overlaps a non-light emitting region of the light emitting element.

Abstract: An organic light emitting diode (OLED) display panel and a method for manufacturing the OLED display panel are provided. The OLED display panel includes a first electrode layer, a second insulating layer, and an auxiliary electrode layer. The first electrode layer includes a plurality of first electrodes. The second electrode layer includes a plurality of second electrodes. The first electrodes and the second electrodes are aligned with each other. The auxiliary electrode layer includes rows of auxiliary electrode, each row of the auxiliary electrodes is corresponding to and electrically connected with a row of the second electrodes.

Abstract: The present disclosure relates to an OLED device and a method for preparing the same. The method includes: providing an OLED basic device; forming a hydrophobic layer selectively covering a light emitting side surface of the OLED basic device by an ink jet printing method; forming an optical coupling efficiency enhancing layer on an area of the light emitting side surface in a selective atom precipitation way, which may not be covered by the hydrophobic layer. The optical coupling efficiency enhancing layer is formed between adjacent hydrophobic layers to form a periodic distribution array, thereby improving the optical coupling efficiency of the OLED device.

Abstract: The present application provides an array substrate, which includes a base substrate, and a first electrode, a first protection layer, a semiconductor electrode, a second protection layer and a second electrode formed sequentially on the base substrate. The second electrode and the semiconductor electrode constitute a storage capacitor, and the first electrode is below the semiconductor electrode to make the semiconductor electrode conductive. In a direction perpendicular to the base substrate, the thickness of at least a portion of the first protection layer in the first electrode area is less than that of other portions of the first protection layer outside the first electrode area, the first electrode area being an area defined by the projection of the first electrode on the first protection layer.

Abstract: A display device includes: a substrate including a display area including pixels at which an image is displayed and a peripheral area at which the image is not displayed, the peripheral area disposed outside the display area. In the peripheral area, thin film transistors connected to the pixels and with which operation of the pixels is tested, the thin film transistors including gate electrodes arranged separated from each other on the substrate; and a bridge wiring electrically connecting adjacent gate electrodes of the plurality of thin film transistors to each other.

Abstract: A flexible display device may include a flexible display panel including a display area disposed a plurality of pixels, a signal line area disposed a plurality of signal lines for transmitting driving signals to the plurality of pixels, and a panel pad area disposed a plurality of panel pads for receiving an external driving signal, and a flexible film configured to transmit the driving signals inputted from an external to the flexible display panel and including a film pad area in which a plurality of film pads arranged so as to correspond to the plurality of panel pad, wherein the plurality of film pads has a first thickness configured to increase a contact surface with the flexible display panel.

Abstract: A gate driver circuit, a display device, and a method of driving the display device are disclosed. The gate driver circuit includes a first transistor supplying a start signal to a Q node in response to a clock, a second transistor adjusting a gate voltage of the first transistor in response to the clock, a third transistor adjusting a gate voltage of the second transistor in response to the start signal, a fourth transistor changing a voltage of a QB node, a fifth transistor switching a current path between the first transistor and the Q node in response to a first line control signal, a sixth transistor supplying a gate-off voltage to an output node, a seventh transistor supplying a gate-on voltage to the output node, and an eighth transistor supplying a second line control signal to the QB node.

Abstract: Provided is a display apparatus capable of reducing generation of defects during manufacturing of the display apparatus or while in use after being manufactured. The display apparatus includes a substrate including a bending area between a first area and a second area, the substrate being bent in the bending area about a bending axis; an inorganic insulating layer over the substrate and including a first feature that is either a first opening or a first groove, the first feature positioned to correspond to the bending area; and an organic material layer at least partially filling the first feature, and including a second feature that is a second opening or a second groove, the second feature extending along an edge of the substrate.

Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.

Abstract: A semiconductor device constituted of: a semiconductor layer; and a field layer patterned on said semiconductor layer, said field layer constituted of material having characteristics which block diffusion of mobile ions and maintain structural integrity at activation temperatures of up to 1200 degrees centigrade.

Abstract: A semiconductor device includes a substrate, a liner, and an isolation structure. The substrate has at least one first semiconductor fin and at least one second semiconductor fin. The liner is disposed on at least one sidewall of the second semiconductor fin. The isolation structure is disposed over the substrate, in which the isolation structure is in contact with the first semiconductor fin and the liner.

Abstract: An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.

Abstract: A semiconductor device includes active patterns protruding from a substrate and an insulation structure surrounding lower portions of the active patterns. The insulation structure includes an insulation layer conforming to a top surface of the substrate and to sidewalls of the active patterns and a buried insulation pattern on the insulation layer.

Abstract: A semiconductor device includes a substrate having a working surface, and a plurality of field effect transistor (FET) devices provided on the substrate in a common plane along the working surface. Each FET device includes an active nanochannel structure having opposing end surfaces and a sidewall surface extending between the opposing end surfaces, and an active gate structure surrounding an intermediate portion of the nanochannel structure in contact with the sidewall surface. First and second gate spacers each surrounding a respective end portion of the nanochannel structure in contact with the side wall surface, and first and second source/drain (S/D) structures are in contact with the opposing end surfaces of the nanochannel structure respectively. A single diffusion break provided between first and second FET devices, the single diffusion break including a dummy nanochannel structure connected to an S/D structure of the first FET device and an S/D structure of the second FET device.

Abstract: A power semiconductor device includes an emitter electrode disposed on a semiconductor substrate and through which a main current flows, a conductive layer that is disposed on the emitter electrode and is not a sintered compact, and a sintered metal layer that is disposed on the conductive layer and is a sintered compact. The sintered metal layer has a size to cover all the emitter electrode in plan view, and has higher heat conductivity than the conductive layer. The power semiconductor device can improve heat dissipation performance and adhesion.

Abstract: A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.

Abstract: Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.

Abstract: A first insulating layer is disposed on a second surface of a semiconductor substrate, and has an opening. A second insulating layer is disposed on the second surface and separated from the first insulating layer. A stack includes, in sequence on the second surface, a side n-type epitaxial layer and first and second p-type epitaxial layers that are made of a gallium-nitride-based material. The stack has an outer side wall having a portion formed of the second p-type epitaxial layer, an inner side wall extending from the second insulating layer, and a top surface. The n-type contact layer is disposed on the top surface. The source electrode portion is in contact with the n-type contact layer on the top surface, and is in contact with the second p-type epitaxial layer on the outer side wall. A gate insulating film is disposed on the inner side wall.

Abstract: A gallium nitride transistor can include a silicon substrate and a first oxide layer and a second oxide layer on the substrate. A first gallium nitride layer may reside on the silicon substrate and the first and second oxide layers. A polarization layer may reside on the first gallium nitride layer. A two dimensional electron gas may exist in the first gallium nitride layer proximate to the polarization layer. A second gallium nitride layer may reside on a first sidewall of the polarization layer and on the first oxide layer on the substrate. A first p-doped gallium nitride layer may reside on the second gallium nitride layer. A third gallium nitride layer may reside on a second sidewall of the polarization layer and on the second oxide layer on the substrate. A second p-doped gallium nitride layer may reside on the second gallium nitride layer.

Abstract: Techniques are disclosed for forming transistors including retracted raised source/drain (S/D) to reduce parasitic capacitance. In some cases, the techniques include forming ledges for S/D epitaxial regrowth on a high-quality crystal nucleation surface. The techniques may also include forming the raised sections of the S/D regions (e.g., the portions adjacent to spacer material between the S/D regions and the gate material) in a manner such that the S/D raised sections are retracted from the gate material. This can be achieved by forming a notch at the interface between a polarization charge inducing layer and an oxide layer using a wet etch process, such that a relatively high-quality surface of the polarization charge inducing layer material is exposed for S/D regrowth. Therefore, the benefits derived from growing the S/D material from a high-quality nucleation surface can be retained while reducing the parasitic overlap capacitance penalty that would otherwise be present.

Abstract: Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.

Abstract: Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.

Abstract: Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.

Abstract: Embodiments of the invention form a channel fin across from a major surface of a substrate, wherein a top surface of the channel fin extends substantially horizontally with respect to the major surface. A gate is formed across from the major surface and along a sidewall surface of the channel fin, wherein a first top surface of the gate is above the top surface of the channel fin and extends substantially horizontally with respect to the major surface. A second top surface of the gate is defined by a trench formed through an exposed sidewall portion of the gate in a direction that is substantially horizontal with respect to the major surface, wherein a gate length dimension of the initial gate is defined by a distance from a bottom surface of the gate to the second top surface of the gate.

Abstract: Embodiments of the invention form a channel fin across from a major surface of a substrate, wherein a top surface of the channel fin extends substantially horizontally with respect to the major surface. A gate is formed across from the major surface and along a sidewall surface of the channel fin, wherein a first top surface of the gate is above the top surface of the channel fin and extends substantially horizontally with respect to the major surface. A second top surface of the gate is defined by a trench formed through an exposed sidewall portion of the gate in a direction that is substantially horizontal with respect to the major surface, wherein a gate length dimension of the initial gate is defined by a distance from a bottom surface of the gate to the second top surface of the gate.

Abstract: An ohmic electrode that is used in, for example, a power semiconductor device including: a SiC substrate including an ohmic contact layer formed on a SiC semiconductor layer and formed of a material selected from the group consisting of nickel and nickel silicide, a barrier layer formed on the ohmic contact layer, and an electrode layer formed on the barrier layer and formed of a copper alloy containing at least one from among zinc, nickel, titanium, manganese, and calcium.

Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on?VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi?Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a sacrificial layer arranged vertically between the first and second nanosheet channel layers. The sacrificial layer is laterally recessed at a sidewall of the body feature to expose respective portions of the first and second nanosheet channel layers. A sacrificial spacer is formed by oxidizing a portion of the sacrificial layer at the sidewall of the body feature. Sections of a semiconductor material are epitaxially grown on the exposed portions of the first and second nanosheet channel layers to narrow a gap vertically separating the first and second nanosheet channel layers. The sacrificial spacer is removed to form a cavity between the sections of the semiconductor material and the sacrificial layer. A dielectric spacer is conformally deposited in the cavity.

Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.

Abstract: On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.

Abstract: A power semiconductor device includes a semiconductor body, a first load terminal structure arranged at a front side of the semiconductor body, and a second load terminal structure arranged at a back side of the semiconductor body, and configured for controlling a load current between the load terminal structures by means of at least one transistor cell. The at least one transistor cell is at least partially included in the semiconductor body and electrically connected to the first load terminal structure on one side and to a drift region on the other side, the drift region being of a first conductivity type. The semiconductor body further includes: a transistor short region of the first conductivity type, wherein a transition between the transistor short region and the first load terminal structure forms a Schottky contact; and a separation region of a second conductivity type separating the transistor short and drift regions.

Abstract: Embodiments relate to a stacked photo sensor assembly where two substrates are stacked vertically. The two substrates are connected via interconnects at a pixel level to provide a signal from a photodiode at a first substrate to circuitry on a second substrate. The circuitry on the second substrate performs operations that were conventionally performed on first substrate. More specifically, charge storage of the first substrate is replaced with capacitors on the second substrate. A voltage signal corresponding to the amount of charge in the first substrate is generated and processed in the second substrate. By stacking the first and second substrates, the photo sensor assembly can be made more compact while increasing or at least retaining the photodiode fill factor of the photo sensor assembly.

Abstract: A semiconductor device may include a semiconductor substrate and first and second spaced apart shallow trench isolation (STI) regions therein, and a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first semiconductor stringer including a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and a gate above the superlattice.

Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of the element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.

Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of this element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region, and in contact with the gate insulation layer on a lower side of the body region. The bottom region includes a low concentration region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench; and a high concentration region in contact with the gate insulation layer in a second range of the bottom surface adjacent to the first range.

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing an array substrate and a display device. The array substrate includes a base substrate and a transistor disposed on the base substrate, and the transistor includes a gate electrode and an active layer. A light absorbing layer is formed on a side of the gate electrode facing the active layer, and the light absorbing layer is configured to absorb light irradiated thereto.

Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.

Abstract: A system and method for printing electrodes of a solar cell by automatically positioning are provided. The system includes: a transparent glass plate configured to support a solar cell, an electrode printing apparatus arranged above the transparent glass plate and configured to form electrodes on the solar cell by screen printing, a visual positioning module arranged right below the transparent glass plate and configured to acquire position information of the solar cell, and a main control module configured to adjust a position of the electrode printing apparatus according to the position information sent by the visual positioning module.