Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

Abstract: A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.

Abstract: Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the techniques may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.

Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.

Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

Abstract: Predicting data correlation using multivalued logical outputs in SRAM storage cells including generating a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points; writing, into storage cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each storage cell; and measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs.

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Abstract: Read reference levels are used to distinguish different data states for information stored in non-volatile memory. A storage system recalibrates its read reference levels, to maintain accuracy of the read process, by sensing samples of data for different test read reference levels and using those samples to determine an improved set of read reference levels. At least a subset of the test read reference levels used for the samples are dynamically and adaptively chosen based on indications of error for previous samples.

Abstract: Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive memory array. A VVDP reduction can be determined from the sum of the selected one or more of the plurality of bit lines.

Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

Abstract: An RRAM storage subarray structure, and reading and writing methods therefore. The RRAM subarray structure comprises a main array and a reference array. Any one column in the reference array comprises a first bit line, a second bit line and a source line, and comprises n/2 memory cells connected in parallel between the first bit line and the source line and n/2 memory cells connected in parallel between the second bit line and the source line, wherein k columns of memory cells in the reference array share the source line, and any one column in the reference array can be used as a reference cell. By providing an adaptive read reference current, the RRAM subarray structure increases the read margin and improves the read speed and success rate.

Abstract: In one embodiment, a device includes a memory cell for storing “0” or “1” as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is “0” and the current when the data is “1” take values in C1/C3, and second processing of reading out the stored data such that the current when the data is “0” or the current when the data is “1” takes a value in C2/C4 or C5.

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Abstract: According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Abstract: Disclosed is a semiconductor memory device. The semiconductor memory device includes: a first memory block; and a second memory block sharing a block word line with the first memory block, in which the block word line includes a first block word line disposed so as to overlap the first memory block and a second block word line disposed so as to overlap the second memory block. According to the present disclosure, it is less likely to have an operation failure.

Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Abstract: A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. Each memory cell includes a charge retention film between the semiconductor channel and a respective word line in the plurality of word lines. A controller is connected to the semiconductor channel and the word lines and configured to apply a program voltage during a program operation to a memory cell at a potential that increases in voltage steps, and a voltage increment between the voltage steps decreases during the program operation. The increment voltage is changed by the controller depending on a position of the memory cell along the semiconductor channel in the first direction.

Abstract: A memory device comprises a plurality of stacks of word lines, the word lines in the stacks having first vertical sides and second vertical sides opposite the first vertical sides, and a first plurality of strings and a second plurality of strings disposed respectively on the first vertical sides and the second vertical sides of the word lines in a particular stack in the plurality of stacks. The second plurality of strings is offset from the first plurality of strings in a direction along which the word lines in the particular stack extend. A first program operation includes applying a shielding voltage to a first string in the first plurality of strings and a fourth string in the second plurality of strings, and applying a program voltage to a second string in the second plurality of strings and a third string in the first plurality of strings.

Abstract: A memory device and a programming method for a memory cell array are provided. The memory device includes a memory cell array, a selection switch, a row decoder, a voltage generator, and a memory controller. The memory controller controls the row decoder according to input data to adjust a control path sequence of address control signals, and the memory controller simultaneously controls the voltage generator to adjust a data path sequence of input data signals, so as to perform a programming operation on memory cells of the memory cell array.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a memory device including a plurality of memory blocks, the memory device configured to perform a read operation on a selected memory block among the plurality of memory blocks; and a memory controller for controlling the memory device to perform the read operation, wherein an Initial turn-on period of the read operation is controlled based on information on an erase number of source line sharing blocks of the selected memory block.

Abstract: A semiconductor memory device includes a first circuit configured to process data received from and transmitted to an external controller, a second circuit configured to execute calibration on the first circuit, and a control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller. In response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit. In response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met.

Abstract: A NAND flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.

Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.

Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.

Abstract: Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.

Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier. The sense amplifier is connected to the bit line, receives a first control signal, and detects and amplifies a bit line signal of the bit line. The sense amplifier includes a precharge device that is turned on or turned off based on a read control signal, and a transistor output unit that outputs an output voltage based on the bit line signal when the precharge device is turned off.

Abstract: A memory system and an operating method thereof include: at least a CPU configured to generate a special command; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; and a plurality of memory devices connected with the PCIe switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.

Abstract: The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. The controller is configured to determine a previous power loss of a memory to be an asynchronous power loss, and identify a portion of the memory last subject to programming operations during the determined asynchronous power loss. The controller is further configured to perform a threshold voltage (Vt) margin analysis on the portion of the memory responsive to the determined asynchronous power loss.

Abstract: Apparatuses and methods related to column repair in memory are described. The sensing circuitry of an apparatus can include a first sensing component, a second sensing component, and a third sensing component. The second sensing component can include a defective sense amplifier that is column repaired. The apparatus can include a controller configured to use the sensing circuitry to shift data from the first sensing component to the third sensing component by transferring the data through the second sensing component. The second sensing component can be physically located between the first sensing component and the third sensing component.

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

Abstract: System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.

Abstract: Herein is reported a method for selecting or deselecting an antibody comprising a) determining for each Asp and Asn residue in an antibody Fv region the conformational flexibility of the C?-atom using a homology model ensemble, b) determining for each Asp and Asn residue in an antibody Fv region the size of the amino acid residue C-terminal to the Asp or Asn residue, and c) selecting an antibody in which the C?-atom is conformationally inflexible and/or the Asp or Asn has a big C-terminal amino acid residue, or deselecting an antibody in which the C?-atom has a moderate to high conformational flexibility and/or the Asp or Asn has a small C-terminal amino acid residue.

Abstract: A method of formulating a skin-lightening composition by identifying actives with a data architecture and incorporating the actives into a skin care composition. The data architecture can be used to identify connections between perturbagens and genes associated with skin tone. A gene expression profile for a control human cell is compared to the gene expression profile a cell exposed to perturbagen to identify the genes which are differentially expressed. The differentially expressed genes are analyzed and arranged into an ordered list of identifiers, which along with other instances create a data architecture.

Abstract: Disclosed are systems and methods for polynucleotide sequencing where detection and correction of base calling errors can be achieved without reliance on a reference sequence. In certain embodiments, redundant information can be introduced during measurement so as to allow such detection of errors. Such redundant information and measurements can be facilitated by encoding of nucleotide sequence being measured. Various examples of such encoding, redundancy introduction, and decoding are provided.

Abstract: The present invention relates to a virtual drug screening method with high prediction accuracy based on various biological activities extracted from multiple drug screening data, without using structures or structural attribute information of target proteins or compounds; an intensive screening library constructing method; and a system therefor.

Abstract: A device agent including an information accessor for accessing association information obtained via an information reader. The association information includes medical device information for uniquely identifying the medical device, and device agent information for facilitating in an association between the medical device and the information reader. The device agent also includes an associator for associating the medical device and the information reader based on the association information.

Abstract: A device and system for providing identification and medical information are disclosed. The device includes a readable code that contains medical biographical information of the subject, a programmable reporter element that is programmed to electronically store at least one particular event relating to the subject, and a signal producing element functionally related to the programmable reporter element. The system includes collecting and storing medical biographical information of a subject, embedding the medical biographical information in a readable code of the device, and scanning the readable code of the device worn by or in the possession of the subject using an appliance to retrieve the medical biographical information of the subject. The medical biographical information allows medical professionals to obtain the subject's medical information in order to provide medical care. Also disclosed is an integrated system for alerting subjects to upcoming events related to their continued care.

Abstract: A method for connecting a mobile operator terminal to a device to be operated includes outputting a code using an output element associated with the device. The code is transmitted to the mobile operator terminal. At least one piece of information related to the device is determined by decoding the transmitted code using software installed on the mobile operator terminal. A connection from the mobile operator terminal to a control unit associated with the device is then established with the aid of the piece of information related to the device and a piece of information related to the mobile operator terminal is transmitted from the mobile operator terminal to the control unit associated with the device over the established connection. A mobile operator terminal, a device for medical diagnosis or therapy and a system including a mobile operator terminal and a device, are also provided.

Abstract: A system and method is disclosed for monitoring the containment of an epidemic in relation to a location-based restriction using an anonymized database of spending records. The system measures the effectiveness of a restriction by analyzing the spending records of individuals in the population and identifies transaction trends that relate to the restriction and correlates them to the effectiveness of the restriction. Based on the identified transaction trends, the system calculates the effectiveness and analyzes the restrictions according to expected trends and models of epidemic spread by geography. The system utilizes the measured effectiveness and predictive analysis to generate notifications if the effectiveness does not meet prescribed requirements and to recommend corrective action.

Abstract: The present invention provides a top nozzle for use with PWR nuclear reactors and power plants, and in particular, VVER nuclear reactors. The top nozzle includes a plate portion having a peripheral portion; a hub portion spaced from the plate portion; a plurality of support portions extending from the plate portion to the hub portion; and at least one deflector portion extending inwardly from the peripheral portion at an acute angle with respect to the plate portion.

Abstract: A bottom nozzle includes a skirt, support blocks, transverse blades and longitudinal blades. The skirt is a hollow structure and a bottom thereof is provided with corner legs which are protruded downwards, a cavity is defined in the hollow structure, the transverse blades are configured in the cavity, the longitudinal blades are configured in the cavity, the transverse blades and longitudinal blades are firmly connected with the skirt, projections of the transverse blades and the longitudinal blades in a level plane are intersectant to form interleaved grids, and the support blocks run through and are fixed on the transverse blades and the longitudinal blades. In such a way, the bottom nozzle forms a three-dimensional gridded water passage, thereby improving the filter capacity and generating small water pressure drop.

Abstract: The present invention provides a system and method for reclaiming energy from the heat emanating from spent nuclear fuel contained within a canister-based dry storage system. The inventive system and method provides continuous passive cooling of the loaded canisters by utilizing the chimney-effect and reclaims the energy from the air that is heated by the canisters. The inventive system and method, in one embodiment, is particularly suited to store the canisters below-grade, thereby utilizing the natural radiation shielding properties of the sub-grade while still facilitating passive air cooling of the canisters. In another embodiment, the invention focuses on a special arrangement of the spent nuclear fuel within the canisters so that spent nuclear fuel that is hotter than that which is typically allowed to be withdrawn from the spent fuel pools can be used in a dry-storage environment, thereby increasing the amount energy that can be reclaimed.