Abstract: Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg1, wherein the gates formed alongside the second fin(s) have a second gate length Lg2, and wherein Lg1<Lg2; forming top spacers over the gates; and forming top source/drains over the top spacers. A VFET is also provided.

Abstract: A method performed by a semiconductor manufacturing apparatus includes calculating, by a processor of the semiconductor manufacturing apparatus, 3 standard deviations of process condition measurements obtained at a predetermined interval from log information of processing of substrates that have been correctly processed, calculating at least one of an upper limit and a lower limit for anomaly detection based on the calculated 3 standard deviations, and detecting an anomaly in the processing of the substrates based on the at least one of the upper limit and the lower limit.

Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.

Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.

Abstract: A subject matter of this invention is that a manufacturing yield of a semiconductor device is improved. A resistance value between a pogo pin and a test pin is measured by bringing a plurality of pogo pins of a socket mounted over a test board included in an inspection device of a semiconductor device into contact with a plurality of solder balls, respectively, and bringing the test pin provided in the socket into contact with a first solder ball of a plurality of solder balls at a position different from a position where the pogo pin is brought into contact with the first solder ball. Thereby, a coupling failure between the pogo pin and the first solder ball is detected, so that a conductive state is inspected.

Abstract: A substrate processing apparatus includes: a reaction tube configured to accommodate a substrate holder holding a plurality of substrates and process a substrate held on the substrate holder; a heating unit installed outside the reaction tube and configured to heat an inside of the reaction tube; a protection tube installed to extend in a vertical direction in contact with an outer wall of the reaction tube; an insulating tube disposed inside the protection tube and having through-holes extending in a vertical direction; a thermocouple having a thermocouple junction provided at an upper end thereof, and thermocouple wires joined at the thermocouple junction and inserted into the through-holes of the insulating tube; a gas supply unit configured to supply a gas, for processing a substrate accommodated in the reaction tube, into the reaction tube; and an exhaust unit configured to exhaust a gas from the reaction tube.

Abstract: A described example includes: a die with an active surface; a cap mounted over a portion of the active surface of the die; and mold compound covering the cap and covering portions of the die, the cap excluding the mold compound from contact with the portion of the active surface of the die.

Abstract: A power module includes an insulated circuit board, a semiconductor element, a first buffer plate, and first and second joining materials. The semiconductor element is disposed on a side of one main surface of the insulated circuit board. The first buffer plate is disposed between the insulated circuit board and the semiconductor element. The first joining material is divided into a plurality of portions in a plan view. The first buffer plate is higher in coefficient of linear expansion than the semiconductor element and lower in coefficient of linear expansion than the insulated circuit board. The first buffer plate is lower in Young's modulus than the semiconductor element.

Abstract: A semiconductor chip package and a semiconductor chip packaging method are provided. The package includes: a semiconductor chip having a functional region, a protective substrate located on one side of the semiconductor chip and covering the functional region, and a support unit located between the protective substrate and the semiconductor chip and enclosing the functional region. The support unit includes an outer support member and an inner support member located inside the outer support member. A receiving cavity is formed between the inner support member, the semiconductor chip and the protective substrate. A hollow cavity is formed between the inner support member, the outer support member, the semiconductor chip and the protective substrate. The inner support member is provided with at least one first ventilating structure, through which the receiving cavity is in communication with the hollow cavity.

Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.

Abstract: A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant.

Abstract: A semiconductor device includes a first die including a first pad and a first passivation layer, a second die including a second pad and a second passivation layer, and an encapsulant surrounding the first die and the second die. Surfaces of the first die are not coplanar with corresponding surfaces of the second die. A dielectric layer covers at least portions of the first passivation layer and the second passivation layer, and further covers the encapsulant between the first die and the second die. The encapsulant has a first surface. The dielectric layer has a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant, and further has a third surface opposite the second surface. The semiconductor device further includes a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer.

Abstract: The present invention relates to a substrate structure in which organic-inorganic hybrid thin films are laminated and a method for preparing the same and more specifically to a substrate structure in which organic-inorganic hybrid thin films are laminated that can be used for light emitters, display devices and solar cell devices wherein the organic-inorganic hybrid thin film including a stable new functional group, an inorganic precursor and an organic precursor are alternately used to afford stability in air and a method for preparing the same.

Abstract: A first metal layer is provided on a main surface side of a substrate. A second metal layer is formed on the first metal layer. A solder layer is provided on the second metal layer. An insulating member is structured so that an end of the first metal layer is partially connected to an end of the second metal layer.

Abstract: Provided are a heat dissipation substrate capable of improving heat dissipation properties of an electronic component, and an electric power steering device. In the heat dissipation substrate, a plurality of thermal vias are disposed at least in an electronic component projection region in which a region of a bottom surface portion of the electronic component is projected to a mounting surface in a direction perpendicular to the mounting surface, and a surface density of the thermal vias which occupy the mounting surface per unit area is at least partially different. The plurality of thermal vias are disposed so that the surface density of the thermal vias becomes the greatest in a dense region on an inner side of an edge portion of the electronic component projection region.

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.

Abstract: Ion implantation can be used to define a thermal dissipation path that allows for better thermal isolation between devices in close proximity on a microelectronics chip, thus providing a means for higher device density combined with better performance.

Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a heat dissipation sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The heat dissipation sheet includes a first adhesive layer disposed over the base film, a second adhesive layer disposed over the first adhesive layer, and a graphite layer disposed between the first adhesive layer and the second adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer is a double-sided adhesive with carrier, which comprises two adhesives and a carrier disposed between the two adhesives.

Abstract: A thermal interface for positioning between an electronics packaging and a target object includes a pad having a first side facing one of the electronics packaging and the target object and a second side. Carbon fibers having varying lengths extend from the second side towards the other of the electronics packaging and the target object.

Abstract: A metallic island is disposed between a first metallic bus and a second metallic bus. The first metallic strip is isolated from the metallic island by a first dielectric barrier. At least a parallel portion of the first metallic strip is generally parallel to the first metallic bus, the second metallic strip isolated from the second metallic bus by a second dielectric barrier. Each first semiconductor terminals that are coupled to the first metallic bus and to the metallic island. Each second semiconductor has terminals coupled to the metallic island and to the second metallic bus.

Abstract: A system includes a heat sink, a semiconductor device, a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device, and a fastener system that couples the semiconductor device, the layer of TIM, and the heat sink together. The TIM may facilitate dissipation of heat generated by the semiconductor device via the heat sink during operation of the semiconductor device. The fastener system includes a first Belleville-type washer configured to cooperate with the TIM, which flows when heated beyond a threshold temperature, to maintain a substantially constant coupling force between the semiconductor device and the heat sink during operation of the semiconductor device.

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.

Abstract: A BGA package substrate includes a substrate, a resist formed over the substrate and includes an opening, a land formed over the substrate in the opening, and a solder ball fused to the land, wherein the resist includes a notch at an edge of the opening through which the land is exposed, the notch having a bottom at a position lower than a surface of the land.

Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

Abstract: An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip.

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer, and an external connection pad tapered from a top surface to a bottom surface. The second patterned conductive layer includes a pad and a trace adjacent to the pad. The external connection pad is disposed on the pad of the second patterned conductive layer. A bottom width of the external connection pad is greater than or equal to a width of the pad of the second patterned conductive layer.

Abstract: A semiconductor device includes: a first semiconductor chip that includes through electrodes; a second semiconductor chip; and an interposer that has a recessed portion formed in a front surface thereof and includes a first wiring provided under a bottom surface of the recessed portion, in which the first semiconductor chip is fitted in the recessed portion with a chip top surface thereof flipped down to be electrically connected to the first wiring, the second semiconductor chip is connected on the front surface, of the interposer, around the recessed portion, and at the same time, is stacked on the first semiconductor chip in a manner to partially overlap the first semiconductor chip, and is electrically connected to the first semiconductor chip via the through electrodes.

Abstract: A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a first recess portion and a first stopper layer disposed on a bottom surface of the first recess portion; a semiconductor chip disposed in the first recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the first stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the first recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other.

Abstract: An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.

Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.

Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.

Abstract: An improvement is achieved in the performance of a semiconductor-device. The semiconductor device includes MISFETs formed in the upper surface of a substrate, a plurality of wiring layers stacked over the upper surface of the substrate, and a plurality of plugs each coupling two of the wiring layers to each other. The wiring layers located under the uppermost wiring layer include wires. The uppermost wiring layer includes a pad, an insulating film formed over the pad, and an opening extending through the insulating film and reaching the pad. The MISFETs and the wires overlap the opening in plan view. None of the plurality of plugs overlaps the opening in plan view.

Abstract: Method of manufacturing electronic devices using a maskless lithographic exposure system using a maskless pattern writer. The method comprises generating beamlet control data for controlling the maskless pattern writer to expose a wafer for creation of the electronic devices, wherein the beamlet control data is generated based on a feature data set defining features selectable for individualizing the electronic devices, wherein exposure of the wafer according to the beamlet control data results in exposing a pattern having a different selection of the features from the feature data set for different subsets of the electronic devices.

Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.

Abstract: An object of the present invention is to improve the operating characteristics of a semiconductor device. A semiconductor device has a contact plug that is formed over a semiconductor substrate, a metal wiring that is coupled to the upper surface of the contact plug, and a slit that is formed in the metal wiring. Further, the contact plug is formed at an end of the metal wiring, and the slit is formed at a position apart from the contact plug in an X direction in a planar view. A distance between an edge of the upper surface at the end of the metal wiring and the upper surface of the slit in the X direction is equal to or larger than and twice or smaller than a first plug diameter of the upper surface of the contact plug in the X direction.

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Abstract: Semiconductor devices may include a substrate and a semiconductor die on the substrate. The semiconductor die may include an active surface and a lateral edge at a periphery of the active surface. An electrically insulating material may be located on the active surface proximate the lateral edge. The electrically insulating material may be distinct from any other material located on the active surface. A wire bond may extend from the active surface, over the electrically insulating material, to the substrate. Methods of making semiconductor devices may involve positioning an electrically insulating material on an active surface of a semiconductor die proximate a lateral edge at a periphery of an active surface. After positioning the electrically insulating material on the active surface, a wire bond extending from the active surface, over the electrically insulating material, to the substrate may be formed.

Abstract: An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.

Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.

Abstract: Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes an IC and a shielding sidewall disposed adjacent to the IC. In certain aspects, the IC comprises a first layer coupled to the shielding sidewall, a second layer comprising a first signal path, and a third layer disposed below the first layer and coupled to the shielding sidewall, wherein the second layer is disposed between the first layer and the third layer. In some cases, the IC also includes a plurality of vias configured to couple the first layer to the third layer, wherein at least a portion of the first signal path is disposed in an inner shielding region that spans from the first layer to the third layer and spans from the shielding sidewall to the plurality of vias.

Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

Abstract: To protect the insulating film so that crack is not produced in the insulating film even when stress is applied to the semiconductor device. A manufacturing method of a semiconductor device is provided, including: forming an insulating film above a semiconductor substrate; forming, in the insulating film, one or more openings that expose the semiconductor substrate; forming a tungsten portion deposited in the openings and above the insulating film; thinning the tungsten portion on condition that the tungsten portion remains in at least part of a region above the insulating film; and forming an upper electrode above the tungsten portion.

Abstract: The present disclosure discloses an inductor structure mounted on a PCB board and a voltage regulator module having the same. The inductor structure includes inductor cores and inductor windings. The PCB board is provided with at least one hollow part, and the hollow part comprises a plurality of through holes spaced apart. The legs of the inductor cores are correspondingly inserted into the through holes at the corresponding positions of the hollow part, wherein any two adjacent through holes of the plurality of through holes have a spacer therebetween for use as the inductor winding of the inductor structure, and the thickness of the spacer is less than the thickness of the PCB board.