Abstract: Amorphous silicon devices, systems, and related methods are described herein. An example method for fabricating a thin film with light-emitting or light-detecting capability can include depositing a thin film of amorphous silicon on a wafer such that crystalline defects are distributed throughout the thin film. Additionally, an example photonic device can include a p-doped region and an n-doped region formed on a wafer, and a resonator structure formed on the wafer. The resonator structure can be formed from amorphous silicon and can be arranged between the p-doped and n-doped regions to form a PIN junction. Optionally, the photonic device can be incorporated into a monolithic integrated optical system.

Abstract: Provided is an epitaxial substrate for semiconductor elements which suppresses an occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN being doped with Zn; a buffer layer being adjacent to the free-standing substrate; a channel layer being adjacent to the buffer layer; and a barrier layer being provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer formed of Al-doped GaN and suppresses diffusion of Zn from the free-standing substrate into the channel layer.

Abstract: A nitride semiconductor structure includes a substrate, a nitride semiconductor layer, and a buffer stack layer between the substrate and the nitride semiconductor layer. The buffer stack layer includes a plurality of metal nitride multilayers repeatedly stacked, wherein each of the metal nitride multilayers consists of a first, a second, and a third metal nitride thin films in sequence, or consists of the first, the third, the second, and the third metal nitride thin films in sequence. The aluminum concentration of the first metal nitride thin film is higher than that of the third metal nitride thin film, and the aluminum concentration of the third metal nitride thin film is higher than that of the second metal nitride thin film.

Abstract: A nitride semiconductor template includes a substrate, and a chlorine-containing nitride semiconductor layer. The chlorine-containing nitride semiconductor layer contains an iron concentration of not higher than 1×1017 cm?3.

Abstract: A substrate treatment method of treating a substrate using a block copolymer containing a hydrophilic polymer and a hydrophobic polymer, includes: a resist pattern formation step of forming a predetermined resist pattern by a resist film on the substrate; a thin film formation step of forming a thin film for suppressing deformation of the resist pattern on a surface of the resist pattern; a block copolymer coating step of applying a block copolymer to the substrate after the formation of the thin film; and a polymer separation step of phase-separating the block copolymer into the hydrophilic polymer and the hydrophobic polymer.

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of boron-carbon films on a substrate. In one implementation, a method of processing a substrate is provided. The method comprises flowing a hydrocarbon-containing gas mixture into a processing volume of a processing chamber having a substrate positioned therein, wherein the substrate is heated to a substrate temperature from about 400 degrees Celsius to about 700 degrees Celsius, flowing a boron-containing gas mixture into the processing volume and generating an RF plasma in the processing volume to deposit a boron-carbon film on the heated substrate, wherein the boron-carbon film has an elastic modulus of from about 200 to about 400 GPa and a stress from about ?100 MPa to about 100 MPa.

Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.

Abstract: A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.

Abstract: Methods and apparatus to selectively deposit metal films (e.g., titanium films) are described. One of the precursors is energized to form ions and radicals of the precursor. The precursors flow through separate channels of a dual channel gas distribution assembly to react in a processing region above a substrate.

Abstract: Polishing compositions comprising ceria coated silica particles offer minimal topography, reduced oxide and nitride losses, while providing high oxide polish rates. These formulations are especially useful for polishing large structures typically used in 3D NAND device manufacturing.

Abstract: Disclosed is a method of chemically-mechanically polishing a substrate. The method comprises, consists of, or consists essentially of (a) contacting a substrate containing at least one Group III-V material, with a polishing pad and a chemical-mechanical polishing composition comprising water, abrasive particles having a negative surface charge, and an oxidizing agent for oxidizing the Group III-V material in an amount of from about 0.01 wt. % to about 5 wt. %, wherein the polishing composition has a pH of from about 2 to about 5; (b) moving the polishing pad and the chemical-mechanical polishing composition relative to the substrate; and (c) abrading at least a portion of the substrate to polish the substrate. In some embodiments, the Group III-V material is a semiconductor that includes at least one element from Group III of the Periodic Table and at least one element from Group V of the Periodic Table.

Abstract: An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.

Abstract: An etching method using a remote plasma source (RPS) and a method of fabricating a semiconductor device, the etching method including generating a plasma by supplying a process gas to at least one RPS and applying power to the at least one RPS; and etching a first material film including SiNx by supplying the plasma and at least one control gas selected from HBr, HCl, HI, NH3, SiH4, CHF3, and CH2F2 to a process chamber.

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).

Abstract: A method of making nanostructures including: locating a photoresist mask layer on a substrate, the thickness of the photoresist mask layer is H; forming a patterned mask layer includes a plurality of stripe masks, a spacing distance between adjacent stripe masks equals L; depositing a first thin film layer along a first direction, the thickness of the first thin film layer is D, a first angle between the first direction and a direction along the thickness of stripe masks is ?1, ?1<tan?1(L/H); depositing a second thin film layer along a second direction, a second angle between the second direction and the direction along the thickness of stripe masks is ?2, ?2<tan?1[L/(H+D)], 0<L?H tan ?1?(H+D)tan?2<10 nm, the first thin film layer partly overlaps with the second thin film layer to form an overlapping structure; etching the first thin film layer and the second thin film layer to obtain a nanoscale microstructure.

Abstract: In an etching method of etching a tungsten film, the method is provided to execute a generating a surface reaction layer on a tungsten film that is formed on a surface of a base material by supplying a reactive species including fluorine which is generated in plasma onto the base material for a first predetermined time in a state where the base material of which the tungsten film is formed on at least a portion of the surface is cooled to a melting point temperature or lower of a tungsten fluoride, and a removing the surface reaction layer that is generated on the tungsten film by heating the base material of which the surface reaction layer is generated on the tungsten film to a boiling point temperature or higher of the tungsten fluoride for a second predetermined time.

Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.

Abstract: A method for producing a glass substrate according to the present invention includes the steps of: (I) forming a through hole (11) in a glass sheet (10); (II) forming a resin layer (20) on a first principal surface of the glass sheet (10) using a resin composition sensitive to light having a predetermined wavelength ?1; (III) photoexposing an area of the resin layer (20) that covers the through hole (11) by irradiating the area with light U having the wavelength ?1 and applied from the direction of a second principal surface of the glass sheet (10); and (IV) forming a through-resin hole (21) by removing the area photoexposed in the step (III). The glass sheet (10) protects the resin layer (20) from the light U so as to prevent the resin layer (20) from being photoexposed by beams of the light U that are incident on the second principal surface of the glass sheet (10) in the step (III).

Abstract: The present disclosure relates to a substrate with a plating configuration and a process for making the same. The disclosed substrate includes a substrate base with a substrate body, and a plating configuration with a plating seed layer and a plating barrier layer. Herein, the substrate body is formed of metal-diamond composites. The plating seed layer is formed of copper, silver, or gold, and the plating barrier layer includes nickel material. The plating seed layer directly covers at least sidewalls of the substrate body, and the plating barrier layer is directly formed over the plating seed layer and encloses the substrate base.

Abstract: A temperature of only a part in a surface of a mounting table can be set to be higher than or lower than a set temperature of an entire surface of the mounting table. A main flow path 320 formed within the mounting table 200 to be arranged over the entire surface thereof; an auxiliary flow path 330 formed within the mounting table to be arranged in a part of the surface thereof; and a temperature control medium circulating unit that supplies and circulates a temperature control medium adjusted to have a set temperature into and through the main flow path, allows the temperature control medium to be branched, and supplies and circulates the branched temperature control medium into and through the auxiliary flow path after adjusting a temperature of the branched temperature control medium to be a temperature higher than or lower than the set temperature are provided.

Abstract: A tape film lamination apparatus may include a housing, a substrate holder disposed in the housing and positioned to receive a substrate, a film holder disposed on the housing and positioned to support a tape film, and an air removal unit connected to a portion of the housing below the film holder to remove and/or exhaust air from the housing resulting to attach the tape film to the substrate.

Abstract: A system for fan out chip encapsulation processing is provided, wherein a plurality of microchips are encapsulated in molding compound, the system comprising: an atmospheric loading camber, configured to load substrates onto carriers in atmospheric environment; an entry loadlock arrangement configured to introduce the carriers into vacuum environment of the system; a degas chamber positioned downstream of the loadlock arrangement within the vacuum environment, the degas chamber comprising a heating element and a pumping arrangement to remove gases emitted from the molding compound; an etch chamber positioned downstream of the degas chamber and within the vacuum environment, the etch chamber comprising an ion beam generator and an ion neutralizer; a metal sputtering chamber positioned downstream of the etch chamber and inside the vacuum environment; and, an exit loadlock arrangement configured to remove carriers from the vacuum environment.

Abstract: A workpiece handling module including a first housing member and a second housing member pivotally movable relative to the first member forming a housing having an access side and a second side opposite the access side and side walls, a first portion of the side walls is carried by the first member and a second portion of the side walls is carried by the second member, and at least one of the first and second housing members includes at least one sealable opening for allowing ingress and egress of workpieces to and from an interior chamber formed by the first and second housing members in a closed configuration, and the second portion of the side walls adjacent the access side and carried by the second member is greater than the first portion of the side walls adjacent the access side and carried by the first member.

Abstract: An apparatus for conveying a substrate includes a base along which the substrate is conveyed, a first upward gas ejecting section, a second upward gas ejecting section and a third upward gas ejecting section disposed over the base, the third upward gas ejecting section being disposed between the first and second upward gas ejecting sections, and a first downward gas ejecting section and a second downward gas ejecting section disposed above and facing respective portions of the third upward gas ejecting section. Gas ejected upward from the first, second and third upward gas ejecting sections floats the substrate. The substrate is subjected to pressure by gas ejected downward from the first and second downward gas ejecting sections. The first and second downward gas ejecting sections are spaced to provide a working area therebetween and through which the substrate is irradiated with a laser beam.

Abstract: Proposed is an overhead transportation system for transporting FOUPs in the environment of semiconductor production. The system includes a pair of rails and a hoist travelling along the rails on two pairs of independently controlled wheels. The wheels are driven from in-wheel drive motors and are provided with lateral guide rollers that prevent the wheels from contact with the side walls of the rails. The FOUP gripper mechanism for grasping FOUPs is suspended from the hoist on multifunctional electrically conductive straps, which raise a gripper-grasped FOUP by pulling it up together with the lower pulleys of the strap-guiding unit. The gripper mechanism is attached to a swinging member rotationally installed on a slider, which is laterally moveable from the hoist toward a work station. The in-wheel motors receive power from batteries on the hoist. Other drives are fed from an external source switched in to the hoist on work stations.

Abstract: The present invention is directed to an assembling device used for semiconductor equipment. The assembling device includes a chamber lid, a ceiling, a suspension part, a driving part and receptacles. The ceiling is disposed below the chamber lid. The suspension part is inserted through the chamber lid, and to be hooked to the ceiling. The driving part is disposed above the chamber lid and connected to the suspension part, and configured to drive the suspension part to join or separate the ceiling and the chamber lid. The receptacles are disposed in the ceiling and configured to be correspondingly attached to the suspension part, each of the receptacles defines a rotating groove that is open at top and closed at bottom.

Abstract: A sample holder includes a substrate composed of ceramics, having a sample holding surface on one main surface thereof; and a heat-generating resistor provided on an other main surface of the substrate, containing a glass component. The substrate contains the glass component in a vicinity region of the heat-generating resistor.

Abstract: An electrostatic chuck according to an embodiment is an electrostatic chuck for adsorbing an object. The electrostatic chuck includes a base body having a first surface that includes a bottom surface and a protruding surface part protruding from the bottom surface. The protruding surface part has a first top surface and a step surface disposed between the first top surface and the bottom surface.

Abstract: A method of processing a semiconductor wafer, in which a mask is formed: by cutting, with CO2 laser, a portion corresponding to a street, out of a temporary-adhesive of a surface protective tape to protect on a patterned face; carrying out dicing with SF6 plasma; and carrying out ashing, by removing a layer of the temporary-adhesive, with O2 plasma; a semiconductor chip; and a surface protective tape.

Abstract: A vacuum tweezer includes: a tweezer body including a suction distal end portion that performs vacuum suction of an object to be suctioned; and a light source causing a beam to be condensed at a position on an extension of the suction distal end portion on which a vacuum suction force acts.

Abstract: A tray for storing minimum contact area (MCA) components of a substrate processing system includes a first compartment including at least one of a first lift pin tray and a first plurality of holes. The first lift pin tray includes a plurality of slots configured to retain lift pins of the substrate processing system. The first plurality of holes is configured to receive MCA pins of the substrate processing system. A first cup is arranged adjacent to the first compartment. The first cup includes a wall at least partially surrounding the first cup, the wall separates the first cup from the first compartment, and an upper edge of the wall extends above a bottom surface of the first compartment.

Abstract: A wafer edge lift pin of an apparatus for manufacturing a semiconductor device is described. The wafer edge lift pin includes an offset top section containing a notch portion to support and laterally confine the wafer. The notch portion horizontally sweeps away from the wafer along a radius so that rotation adjusts lateral confinement of the wafer. A base section below the top section has a diameter greater than a diameter of the top section across the notch portion to help strengthen the pin and to allow perpendicular mounting. A bottom section has a diameter that is smaller than the diameter of the base section and provides a boss feature to mount the lift pin. The apparatus includes a process chamber where the wafer is processed, a chuck assembly on which the wafer is loaded. At least three wafer edge lift pins move the wafer up and down.

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.

Abstract: Methods of increasing the optical path length and bandwidth of a Ge-based photodiode while reducing the diode area and capacitance without compromising the optical responsivity and the resulting devices are provided. Embodiments include providing a Si substrate having a BOX layer over the Si substrate and a Si layer over the BOX layer; forming an oxide layer over the Si layer; forming a trench in the oxide layer, the trench having a center strip and a plurality of opposing fins; epitaxially growing Ge in the trench and above the oxide layer; and removing the oxide layer, a Ge center strip and a plurality of opposing fins remaining.

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

Abstract: A control method for differentiated etching depth is provided. The method includes: providing a first etching stop pattern layer in a panel having stacked structure; adopting a first etchant to perform a first etching process to the panel such that a location of the panel provided with the first etching stop pattern layer forms a first etching depth, and forms a second etching depth at a location of the panel without providing the first etching stop pattern layer; through controlling an etching time, the second etching depth is deeper than a bottom of the first etching stop pattern layer; and adopting a second etchant to perform a second etching process to the panel in order to etch and remove the first etching stop pattern layer. In a same mask process, through changing the etchant, different depths are etched and formed to reduce the time consuming and decrease the production cost.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.

Abstract: An object is to provide a technique for preventing an oxide film from being partly thin. A third oxide film is formed onto a nitride film in a first area; in addition, a fourth oxide film is formed onto a main surface in a second area. The third oxide film, the nitride film, and a first oxide film are removed from the first area using a mask. After the third oxide film, the nitride film, and the first oxide film are removed, a fifth oxide film is formed onto the main surface in the first area. The fifth oxide film is removed from the first area using a mask. After the fifth oxide film is removed, a sixth oxide film is formed onto the main surface in the first area.

Abstract: A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.

Abstract: A method for manufacturing a semiconductor device having a shallow trench isolation structure includes providing a semiconductor substrate having first and second regions, multiple fins disposed on the first and second regions, and a hardmask layer on an upper surface of the fins, forming a first dielectric layer on the semiconductor substrate covering the fins, forming a first mask layer including an opening exposing a portion of the first dielectric layer between the first and second regions, implanting dopant ions into the exposed portion of the first dielectric layer, removing the first mask layer, and performing an etching process on the first dielectric layer to form a first isolation region between the first and second regions and a second isolation region between the fins. The doped portion has a reduced etch rate so that the thickness of the first isolation region is thicker than the second isolation region.

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.

Abstract: Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.

Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a substrate, including a first region and a second region; forming a first doped region in the first region of the substrate, the first doped region having first doping ions; forming a second doped region in the second region of the substrate, the second doped region having second dopant ions with a conductivity type opposite to the first doping ions; forming a first metallide on a surface of the first doped region having the first doping ions; and forming a second metallide on a surface of the second doped region having the second doping ions, the second metallide and the first metallide being made of different materials.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, multiple trenches extending through the interlayer dielectric layer to the semiconductor substrate and having a first trench of a PMOS device and a second trench of an NMOS device, and a high-k dielectric layer on sidewalls and a bottom of the trenches. The method also includes forming a semiconductor layer filling the trenches, removing the semiconductor layer in the first trench, forming a PMOS work function adjustment layer in the first trench and a metal electrode layer on the PMOS work function adjustment layer in the first trench, removing the semiconductor layer in the second trench, and forming an NMOS work function adjustment layer in the second trench and a metal electrode layer on the NMOS work function adjustment layer in the second trench.