Abstract: An embodiment system includes: a first motion sensor configured to generate first sensor data indicative of a first type of movement of an electronic device; a first feature detection circuit configured to determine at least one orientation-independent feature based on the first sensor data; and a classifying circuit configured to determine whether or not the electronic device is located on a stationary surface based on the at least one orientation-independent feature.

Abstract: Methods, devices, and systems for forming atomically precise structures are provided. In some embodiments, the methods, devices, and systems of the present disclosure utilize a scanning tunneling microscope (STM) system to receive a sample having a surface to be patterned. The system positions a conductive tip over a pixel region of the surface. While the conductive tip remains laterally fixed relative to the surface, the system applies a bias voltage between the conductive tip and the surface such that a current between the conductive tip and the surface removes at least one atom from the pixel region. The system stops applying the voltage and current when it senses the removal of the at least one atom. The system then verifies that the at least one atom has been removed from the pixel region.

Abstract: An anechoic chamber includes a closed chamber and a metal container. The closed chamber includes wave-absorbing inner walls located therein, and the wave-absorbing inner walls collectively define a first accommodation space. Each of the wave-absorbing inner walls includes wave absorbers arranged thereon. The metal container is removably received in the first accommodation space, and has wave-reflecting inner walls located therein. The wave-reflecting inner walls collectively define a second accommodation space which is used to receive a device under test (DUT).

Abstract: A wafer test system includes a cabinet housing multiple instruments, a test head having multiple pin modules, and cable connecting at least some of the instruments to the pin modules. The cabinet has at least one front door, left and right side panels, a rear door, a ceiling unit, and a bottom unit. Each of the instruments has a front surface, left and right side surfaces, and a rear surface. At least some of the instruments each include at least one first connection terminal. The cabinet further includes a first space defined between the at least one front door and the front surface of each of the instruments, and a second space defined between the rear door and the front surface of each of the instruments. The first space and the second space are separated in the cabinet to separate intake air and exhaust air of the instruments.

Abstract: A signal transfer structure including a tapered input line extending in a first direction and having an input terminal and a contact terminal, a width of the input line increasing from the input terminal to the contact terminal in the first direction and a signal being input to the input terminal; a diverging line in contact with the contact terminal of the input line and extending in a second direction different from the first direction; an output line connected to the diverging line and from which the signal is output; and an interconnector, the interconnector including a vertical via between the diverging line and the output line and a via line connected to the vertical via and having a same characteristic impedance as the output line.

Abstract: An oscilloscope probe includes: a connector pod; a probe identification module disposed in the connector pod, the probe identification module having a cross-sectional area; and a resistor disposed in the connector pod, and in-line with the probe identification module and having a substantially identical cross-sectional area as the probe identification module.

Abstract: A testing device with enhanced accessibility for repair and replacement purposes includes a base, an upper seat, a test board and a needle seat. The upper seat is mounted on the base. The test board is sandwiched between the base and the upper seat. A receiving groove is defined on the upper seat. The receiving groove extends through the upper seat to partially expose the test board. The needle seat is detachably fixed to the upper seat. A lower part of the needle seat is received in the receiving groove and abuts against the test board. An upper portion of the needle seat protrudes from the upper seat and is configure for connecting connection terminals of a product to be tested.

Abstract: A probe pin alignment apparatus includes a beam-splitting element, an image-sensing device and a light-reflecting element. The beam-splitting element has a first illuminating surface facing a probe element, a second illuminating surface facing an object, and a light incident surface. The beam-splitting element has a semi-reflective surface for reflecting a light beam from the light incident surface to the probe element. The image-sensing device is disposed externally to the light incident surface of the beam-splitting element. The light-reflecting element, disposed oppositely to the light incident surface, allows a light beam to pass through the semi-reflective surface to be reflected back to the semi-reflective surface to be further projected onto the object. The beam-splitting element outputs a probe image and an object image from the first and second illuminating surfaces through the light incident surface.

Abstract: A combination current sensing device comprising a plurality of current measuring sensors, at least one ambience measuring sensor, a voltage measuring device and a computing device; at least a magnetic field concentrator, and a controlled module assembly constraining the magnetic field concentrator and the bar conductor, in a defined position with respect to one another; the combination current sensing device may have a plurality of incoming connections and a plurality of outgoing connections; and the computing device outputs a validated measure of primary current and an auxiliary information according to a plurality of range and a safe value of the primary current, ensuring functional safety. The voltage measuring device determines a voltage, configured functions and health of an electric source in combination with other sensors and the computing device. One or more of the devices may be optional and or external to the combination current sensing device.

Abstract: A power supply in a test and measurement device includes a stimulus having an output coupled to an amplifier in which an output signal from the stimulus controls an output level of the amplifier. The stimulus may include a Digital to Analog Converter. A measurement circuit detects the output level of the amplifier. The power supply includes an overpulse generator that can be structured to accept a desired amplifier output level, overdrive the stimulus at a first level for a first time period, and drive the stimulus at a second level for a second time period. The measurement circuit determines when the overpulse generator switches from driving the stimulus at the first level to driving the stimulus at the second level. The time period for driving the stimulus at the second level starts as the actual amplifier output level approaches the desired amplifier output level.

Abstract: An apparatus and a method for using a signal analyzer are disclosed. The apparatus includes an input port having a first plurality of input channels. The input port generates a digital data stream from each of the first plurality of input channels. The apparatus also includes a trigger bank having a second plurality of trigger processors, each trigger processor receiving a digital data stream chosen from the digital data streams and generating a trigger output having one of a plurality of possible values from the digital data stream. A trigger combiner that receives each of the trigger outputs and generates a trigger signal if the combined trigger outputs satisfy a predetermined criterion. A controller copies the digital data streams to a memory and copies the trigger processor outputs to the memory in response to the trigger combiner generating the trigger signal.

Abstract: A circuit for sensing a current comprises a substrate having a first and a second major surface, the second major surface being opposite to the first major surface. At least one magnetic field sensing element is arranged on the first major surface of the substrate and is suitable for sensing a magnetic field caused by a current flow in a current conductor coupled to the second major surface. The substrate also comprises at least one insulation layer, substantially buried between the first major surface and the second major surface of the substrate.

Abstract: A shrinkable cable joint includes a joint insulating layer that surrounds a connection region configured to house two connected cable ends. A joint semiconductive layer surrounds the joint insulating layer. A joint screen layer surrounds the joint semiconductive layer. A joint sheath surrounds the joint screen layer. A capacitive voltage sensor is arranged between the joint screen layer and the joint semiconductive layer. The capacitive voltage sensor includes a sensor insulating layer having a first side and an opposite second side; a sensor electrode and a guard electrode arranged on the second side and directly contacting the joint semiconductive layer; and a sensor conductive layer arranged on the first side. The sensor conductive layer includes a first conductive layer portion in direct contact with the joint screen layer and electrically coupled to the guard electrode and a second conductive layer portion electrically coupled to the sensor electrode.

Abstract: A coil wire includes a core wire and a winding wire. The winding wire is wound around a circumference of the core wire so as to form a plurality of spirals. The coil wire satisfies one of: (i) an outer surface of the core wire is exposed, and a distance between the outer surface of the core wire and an inner circumferential surface of part of the winding wire is smaller than a thickness of a first insulating film coated on the winding wire; or (ii) the outer surface of the core wire is coated by a second insulating film, and a distance between an outer surface of the second insulating film and the inner circumferential surface of part of the winding wire is smaller than a thickness of a thicker one of the first insulating film and the second insulating film.

Abstract: A test and measurement probe system (100,104), including an input (106) to receive an input signal, the input signal including a low frequency (LF) and/or direct current (DC) component and an alternating current (AC) component, an extractor circuit (110), such as an AC coupling circuit or a LF and/or DC rejection circuit, configured to receive the input signal and to separate the AC component and the LF and/or DC component from the input signal, a first output (118) to output the alternating current component to the test and measurement instrument, and a second output to output the direct current component to the test and measurement instrument. In some embodiments, the LF and/or DC component is digitized prior to being output by the second output.

Abstract: A current detection structure comprises, a bus bar to be measured through which a current to be measured flows; an element that detects a magnetic field; and a first proximity bus bar and a second proximity bus bar, wherein arrangements of the first proximity bus bar and the second proximity bus bar relative to the element and the directions and magnitude of currents flowing through the first proximity bus bar and the second proximity bus bar are set such that the magnitude of magnetic fields at the position of the element generated by the first proximity bus bar and the second proximity bus bar are the same and directions thereof are reversed.

Abstract: A voltage indicator and a method for its use in detecting and indicating the presence of single-phase AC voltage in an electrical power cord. The voltage indicator includes an electronic display, capacitor plate elements connected electrically to the electronic display so as to couple the voltage indicator capacitively to the electrical power cord when alternating current voltage is present, and diodes that act as a rectifier, between one of the capacitor plate elements and the electronic display device. Capacitive coupling develops electrical current through the voltage indicator and energizes the display device when alternating line current voltage is present in the power cord. The voltage indicator is electrically insulated from the power cord it monitors by the usual insulation on the power cord or cable.

Abstract: A detection circuit and a detection method for an on-the-go device, and a terminal are disclosed. The detection circuit includes a detection unit, a detection end, and a detection chip. The detection unit includes a voltage source and a first resistor that are connected in series, the voltage source is configured to generate a first voltage, and the first resistor is configured to divide the first voltage, to obtain a second voltage. The detection end is connected to an external device and the detection unit, and is configured to provide a connection interface between the detection circuit and the external device. The detection chip is connected to the first resistor, and is configured to determine, when the second voltage is less than a specified voltage, that the external device is an OTG device.

Abstract: A system characterizes and identifies one of a plurality of different operating modes of a number of electric loads. The system includes a processor; a voltage sensor providing a voltage signal for one of the electric loads to the processor; a current sensor providing a current signal for the one electric load to the processor; and a routine executed by the processor and structured to characterize the different operating modes using steady state and voltage-current trajectory features determined from the voltage and current signals, and to identify a particular one of the different operating modes based on a plurality of operating mode membership functions of the steady state and voltage-current trajectory features.

Abstract: A current sensor includes a sensor element configured to output a value of physical quantity depending on current supplied to a load; and a sensor controller configured to output a current value based on the output value of the sensor element. The sensor controller is configured to: acquire the output value and a temperature of the sensor element while current is not supplied to the load; determine a correlation between the output value and the temperature based on a plurality of sets of the acquired output value and the acquired temperature; calculate an offset of the output value at a temperature while current is supplied based on the correlation for the temperature of the sensor element; calculate the current value from a value obtained by subtracting the offset from the output value of the sensor element while current is supplied; and output the calculated current value.

Abstract: A system for verifying an energy generation source, includes a key forming device that forms a key in a DC voltage signal generated by the energy generation source, and a verifying device that verifies the energy generation source based on the key in the DC voltage signal.

Abstract: Measuring data are provided for monitoring a current-supply network, based on one or a plurality of measured electrical quantities of the current-supply network. A time signal is assigned to the measuring data. The measuring data are inspected for the occurrence of one a plurality of predetermined events. Based on determining the occurrence of predetermined event or events, corresponding event data based on the measuring data are generated. A time stamp is conferred to the event data, where the time stamp is based on a link of a synchronized clock time provided by a clock and the time signal assigned to the measuring data. User data are generated from the event data comprising the time stamp, and transmitted via a communication network.

Abstract: Various embodiments relate to detecting theft of electrical energy. A method of detecting theft of electrical energy may include measuring, for each time sample of a number of time samples, a neutral current of an electrical energy metering system. The method may further include summing, for each time sample of the number of time samples, a number of measured phase current values of the electrical energy metering system to determine an imputed neutral current. Further, the method may include determining, for each time sample of the number of time samples, a squared difference between the measured neutral current and the imputed neutral current. Moreover, the method may include integrating, for each time sample of the number of time samples, the squared difference to determine an accumulator value. In addition, the method may include detecting, based on the accumulator value, theft of electrical energy from the electrical energy metering system.

Abstract: A charge calculation apparatus, system and method allow for a controller to administer an electric power charging operation to one or more client devices, such as an electric vehicle. The vehicle provides its ID to the controller, which in turn calculates a tax according to the vehicle making the request, and other factors such as taxing jurisdiction, amount of electricity used, timing, etc. By controlling the charging operation in this way, the taxing authorities are able to collect tax revenue for use in maintaining roads from the users of those roads by monitoring which vehicles are using electricity to operate the vehicles on the roads. By keeping track of the vehicle's movement within different tax jurisdictions, the tax may be apportioned amongst the different taxing authorities.

Abstract: An oscilloscope includes a time domain input, a logic domain input, and a frequency domain input. The time domain input provides a time domain input signal in a time domain as a first input signal. The logic domain input provides logic level input as a second input signal. The logic level input includes logic levels over time. The frequency domain input provides a third input signal through frequency downconversion.

Abstract: A spectrum analyzer includes: a support substrate; and a plurality of resonators that have center frequencies different from each other, one end of each of the plurality of resonators being fixed to the support substrate. The plurality of resonators are arranged so that an interval between resonators having adjacent center frequencies is secured by a certain value or greater, thus reducing coupling and increasing analysis accuracy.

Abstract: A frequency detection circuit may include a pulse generator configured to generate a pulse signal having a pulse width proportional to a cycle of a periodic wave to be measured; a low pass filter configured to selectively allow the pulse signal to pass therethrough; and a determination circuit configured to generate a frequency detection signal based on the pulse signal having passed through the low pass filter.

Abstract: A battery monitor control system has a load plate, two or more lead wires connected to two or more busbars in a string of batteries, and a digital signal processor. The load plate has one or more primary switches connected to two or more terminals of the batteries in the string of batteries. The load plate also has a load resistor and a current sensor. The primary switches are turned on and off to produce a ripple current in the string of batteries. The digital signal processor determines the real portion of the complex impedance of at least one of the batteries by analyzing the voltage and current waveform of the ripple current. The primary switches may be turned on and off with a sin wave modulation.

Abstract: In at least one embodiment, an apparatus for monitoring isolation resistance in a vehicle is provided. The apparatus includes at least one controller that is configured to at least one of activate and deactivate any number of the plurality of switches and to perform a plurality of measurements on a high voltage system. The at least one controller is further configured to determine an isolation resistance between the high voltage system and the low voltage system based on the plurality of measurements and to determine a first resistance between the positive branch and a ground of the low voltage system based at least on the isolation resistance. The at least one controller is further configured to determine whether the isolation resistance of the high voltage system is exhibiting a symmetric failure, or an asymmetric failure based at least on the first resistance.

Abstract: Monitoring seating of a cable connector within a socket is provided by associating a seating monitor with the socket. The seating monitor includes an actuator and a detector. The actuator is partially exposed within the socket, and is engaged by the connector and moved from a cable unplugged position to a cable plugged position with seating of the connector within the socket. The detector monitors seating of the connector within the socket based on position of the actuator. The detector includes a fixed member fixedly positioned within the detector, and a slidable member slidable relative to the fixed member. The slidable member is coupled to the actuator to slide with movement of the actuator. The detector circuit generates a signal representative of position of the slidable member relative to the fixed member, and thus, representative of position of the cable connector within the socket.

Abstract: Embodiments of the present disclosure may enable an electrical component within an electrical distribution equipment cabinet to be audibly monitored via an electrical fault detection device mounted on the housing of the cabinet. The electrical fault detection device may comprise a sensor to detect a signal emitted from an electrical fault within the cabinet, a transducer to convert the detected signal into an electrical audio signal, and an output socket adapted for an external device that may generate an audible sound based on the detected signal. The detected sensor may be an ultrasound sensor and the detected signal may be an ultrasound emitted from the electrical fault.

Abstract: Systems are provided to determine a location of an electrical fault in an electrical system of a vehicle. A test apparatus can include a control unit and a plurality of scan circuits. The control unit is configured to electrically couple the plurality of scan circuits to the electrical system and trigger the plurality of scan circuits to pass electrical signals to the electrical system. Each scan circuit is configured to detect a presence of an electrical fault in the electrical system based on an electrical signal passed. Each scan circuit provides information indicative of a location of the electrical fault in the electrical system, when detected, to the control unit.

Abstract: An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

Abstract: According to the present invention, there is provided a group III nitride semiconductor substrate (free-standing substrate 30) that is formed of group III nitride semiconductor crystals. Both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes. A variation coefficient of an emission wavelength of each of the first and second main surfaces, which is calculated by dividing a standard deviation of an emission wavelength by an average value of the emission wavelength, is 0.05% or less in photoluminescence (PL) measurement in which mapping is performed in units of an area of 1 mm2 by emitting helium-cadmium (He—Cd) laser, which has a wavelength of 325 nm and an output of 10 mW or more and 40 mW or less, at room temperature. In a case where devices are manufactured over the free-standing substrate 30, variations in quality among the devices are suppressed.

Abstract: Techniques regarding autonomous identification of aged circuits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an identification component, operatively coupled to the processor, that can identify an aged circuit by analyzing a current-voltage characteristic curve for a distortion in a sub-threshold quiescent current signature of the aged circuit.

Abstract: A chip includes at least one oscillator circuitry and a controller circuitry. The at least one oscillator circuitry is disposed at different locations of the chip, and respectively generates a plurality of oscillating signals. The controller circuitry transmits the oscillating signals to an external system, in order to determine a performance of the chip based on the oscillating signals. Each of the at least one oscillator circuitry includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit senses a variation of a semiconductor device in the chip, in order to generate a first oscillating signal of the oscillating signals. The second oscillator circuit senses a variation of a parasitic component in the chip, in order to generate a second oscillating signal of the oscillating signals.

Abstract: A device for testing a semiconductor device includes a blade, a socket, and a test board. The blade includes one or more outer blade conductors disposed on one or more side surfaces of the blade. The socket includes one or more outer socket conductors disposed on one or more side surfaces of the socket. The one or more outer socket conductors are disposed at a location such that they are in contact with or are isolated from the one or more outer blade conductors depending on a position of the blade. The test board transfers a test signal to the one or more outer socket conductors.

Abstract: A method for identifying the noise figure of a device under test is described. A signal generator that outputs the modulated signal, a device under test and an analyzer are provided. The signal generator is connected with the analyzer directly wherein at least two error vector magnitude measurements are performed. The signal generator is connected with the device under test and the device under test is connected with the analyzer wherein at least two error vector magnitude measurements are performed. The noise contribution of the device under test is determined from the error vector magnitude measurements performed. A gain measurement is performed on the device under test. The noise figure of the device under test is calculated based on the noise contribution of the device under test obtained and the gain of the device under test obtained. Further, a measurement system is described.

Abstract: Provided are methods and systems for testing time parameters of an adaptor and systems. The method includes the following. After a testing system is coupled with an adaptor, a clock signal is received from the adaptor, where the clock signal is indicative of the transmission time of the instruction. A first valid interrupt of the clock signal, a square wave corresponding to the first valid interrupt, and a next valid interrupt of the first valid interrupt are acquired. A first falling edge and a first rising edge of the first valid interrupt, a second falling edge of the square wave, and a third falling edge of the next valid interrupt are acquired. A test result time parameters of the adaptor is generated according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.

Abstract: Disclosed is a guide plate for a probe card guiding a probe pin of the probe card and a manufacturing method thereof, and the probe card having the same. Particularly, the guide plate and a manufacturing method thereof, and the probe card securing reliability of the probe card are intended to be provided, wherein probe pins are easily inserted into the guide plate, and pin insertion holes into which the probe pins are inserted are precisely formed in a small size.

Abstract: The present disclosure provides methods for testing and evaluating electrical parameters of electronic circuits. An exemplary method includes providing a device-under-test electrically coupled to a testing apparatus; and determining an optimum value of a first electrical parameter and an optimum value of a second parameter by testing the device-under-test according to a set of first electrical parameter values and a set of second electrical parameter values. The optimum value of the first electrical parameter and the optimum value of the second parameter are determined based on an electrical noise response of the device-under-test.

Abstract: An apparatus for testing a wiring circuit includes: a circuit substrate having wirings in the circuit substrate and pads on an upper surface of the circuit substrate and connected to the wirings; an electrode below a lower surface of the circuit substrate; an optical sensor above the upper surface of the circuit substrate and configured to detect a signal emitted from the upper surface of the circuit substrate; and an optical unit above the optical sensor and configured to irradiate light, wherein the optical sensor includes: an optical substrate whose optical characteristics are changed by the signal emitted from the upper surface of the circuit substrate; and a patterned reflective layer on a surface of the optical substrate facing the circuit substrate, the patterned reflective layer having a first region reflecting light incident on the optical substrate and a second region transmitting the light incident on the optical substrate.

Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.

Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Abstract: Embodiments are described for securing access to a debug port of an FPGA (Field Programmable Gate Array) card installed within an IHS (Information Handling System). A remote access controller determines the status of the FPGA card debug port via a query to a management controller of the FPGA card. The remote access controller generates a passcode for the debug port and disables the debug port via a message to the management controller. The management controller detects a request, that includes a requestor password, for access to the debug port. The remote access controller authorizes the requestor's access to the debug port if the requestor password matches the generated passcode. The remote access controller disables the debug port upon each power cycle of the FPGA card or upon detecting removal of a device from the debug port.

Abstract: Systems, methods, and circuitries are disclosed to test an inter-domain device that is positioned in a signal path between a first output wrapper device in a first module and a first input wrapper device in a second module. In one example, a testing system includes an output scan chain that includes the first output wrapper device and an input scan chain that includes the first input wrapper device. A controller is configured to: provide an output scan enable signal to the output scan chain to cause test data to be stored in the first output wrapper device; capture, with the first input wrapper device, inter-domain device data output; provide an input scan enable signal to the input scan chain to cause the inter-domain device data to be output by an output scan chain serial output; and determine whether the inter-domain device data indicates that the inter-domain device is defective.

Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).

Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers , and provides the second timing information corresponding to the timing differences to the transceivers.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.