Abstract: Voice activity detection (VAD) is an enabling technology for a variety of speech based applications. Herein disclosed is a robust VAD algorithm that is also language independent. Rather than classifying short segments of the audio as either “speech” or “silence”, the VAD as disclosed herein employees a soft-decision mechanism. The VAD outputs a speech-presence probability, which is based on a variety of characteristics.

Abstract: A head shell enabling easy and accurate regulation of overhang is provided. A head shell is attachable to and detachable from a connector of a tone arm of a record player, and holds a pickup cartridge. The head shell includes a cylinder attachable to and detachable from the connector, a head shell main body held to the cylinder, and a fixing screw capable of fixing the head shell main body to the cylinder. The cylinder includes a cylindrical cylinder external circumferential surface and a groove disposed on the cylinder external circumferential surface along an axial direction of the cylinder. A space is defined between the fixing screw and the groove in a circumferential direction of the cylinder.

Abstract: An apparatus according to one embodiment includes a controller configured to control writing operations to a magnetic recording tape. The apparatus further includes logic integrated with and/or executable by the controller for causing the controller to write user data to the magnetic recording tape in a user data area of the magnetic recording tape. Furthermore, the logic is integrated with and/or executable by the controller for causing the controller to create a housekeeping data set (HKDS) that includes location information for the user data written in the user data area, and write several copies of the HKDS in a non-user data area of the magnetic recording tape.

Abstract: An apparatus, according to one approach, includes two arrays of data transducers on a module, the two arrays being aligned along a common axis extending between distal ends of the module. Outer servo readers are positioned toward outer ends of the two arrays. An inner servo reader is positioned between the two arrays. The servo readers are positioned to each reside above a unique servo track on a magnetic recording tape. A method according to one approach includes passing a magnetic recording tape having a plurality of data bands over a module as described above. Data is simultaneously transduced on the two data bands using the data transducers. Advantageously, the number of simultaneously-usable channels on the module is dramatically increased, thereby also dramatically increasing the data rate per unit of tape speed, while backward compatibility may be preserved.

Abstract: A junction shield (JS) structure and method of forming the same are disclosed for providing longitudinal bias to a free layer (FL) having a width (FLW) and magnetization in a cross-track direction between sidewalls in a sensor. The sensor is formed between bottom and top shields and has sidewalls extending from a front side at an air bearing surface (ABS) to a backside at a stripe height (SH) from the ABS. The JS structure has a lower layer (JS1) with magnetization parallel to that of the FL, and a tapered top surface such that JS1 has decreasing thickness with increasing height from the ABS. As aspect ratio or AR (SH/FLW) increases above 1, longitudinal bias increases proportionally to slow an increase in asymmetry as AR increases, and without decreasing amplitude for a reader with low AR. The JS1 layer may be antiferromagnetically coupled to an upper JS layer for stabilization.

Abstract: According to one embodiment, a disk device includes a first actuator assembly and a second actuator assembly which are respectively supported by a first bearing unit and a second bearing unit to be rotatable about a support shaft. The first bearing unit includes a first sleeve and a ball bearing. The second bearing unit includes a second sleeve and a ball bearing. The first sleeve includes a first end surface opposed to the second sleeve and an annular first step projecting from the first end surface, and the second sleeve includes a second end surface opposed to the first step with a gap and an annular second step projecting from the second end surface. The second step is opposed to the first step and the first end surface with a gap.

Abstract: Provided is an Fe—Pt based magnetic material sintered compact, comprising BN and SiO2 as non-magnetic materials, wherein Si and O are present in a region where B or N is present at a cut surface of the sintered compact. A high density sputtering target is provided which enables production of a magnetic thin film for heat-assisted magnetic recording media, and also reduces the amount of particles generated during sputtering.

Abstract: A tape-type magnetic recording medium, includes a substrate; and a magnetic layer provided on the substrate. The magnetic recording medium is configured such that (1) (wmax?wmin)/wmin?400 [ppm] where wmax and wmin are respectively maximum and minimum of average values of width of the magnetic recording medium measured under four environments whose temperature and relative humidity are (10° C., 10%), (10° C., 80%), (29° C., 80%), and (45° C., 10%), respectively, and the magnetic layer has a squareness ratio of 65% or more in the vertical direction, and (2) 4.4?TB/(TA?TB) where TA is an average thickness of the magnetic recording medium and TB is an average thickness of the substrate.

Abstract: Disclosed herein are magnetic storage media with embedded disconnected circuits, and magnetic storage systems comprising such media. A magnetic storage media comprises a recording layer comprising a storage location, and an embedded disconnected circuit (EDC) configured to assist in at least one of writing to or reading from the storage location in response to a wireless activation signal. A magnetic storage system comprises a signal generator configured to generate a wireless activation signal, a magnetic storage media with a plurality of storage locations, and a write transducer and/or a read receiver. The magnetic storage media has at least one EDC configured to assist in writing to and/or reading from at least one of the plurality of storage locations in response to the wireless activation signal.

Abstract: A magnetic recording medium includes a substrate, an underlayer formed on the substrate, and a magnetic layer formed on the underlayer. The magnetic layer includes an alloy having a L10 structure. The underlayer includes a first underlayer and a second underlayer. The first underlayer includes Mo and Ru, the content of Ru in the first underlayer is in a range of 5 atom % to 30 atom %, and the second underlayer includes a material having a body-centered cubic (BCC) structure. The second underlayer is formed between the first underlayer and the substrate.

Abstract: A magnetic recording medium, includes a substrate; a magnetic layer; an underlayer between the substrate and the magnetic layer, the underlayer including a non-magnetic powder and a binding agent; and a back layer. In a case where wmax and wmin are respectively maximum and minimum of average values of width of the magnetic recording medium measured under four environments whose temperature and relative humidity are (10° C., 10%), (10° C., 80%), (29° C., 80%), and (45° C., 10%), respectively, wmax and wmin satisfy a relation of (wmax?wmin)/wmin?400 [ppm]. The substrate includes polyester. A squareness ratio in a vertical direction of the magnetic medium is 65% or more, and an average thickness of the magnetic recording medium is 5.6 ?m or less.

Abstract: Provided is a sputtering target, comprising: from 0.001 mol % to 0.5 mol % of Bi; from 45 mol % or less of Cr; 45 mol % or less of Pt; 60 mol % or less of Ru; and a total of 1 mol % to 35 mol % of at least one metal oxide, the balance being Co and inevitable impurities.

Abstract: An image capture device for recording HDR (high dynamic range) image data obtained through image capture performs control so as to, when encoding HDR image data obtained by capturing an image with an image sensor, divide part of the HDR image data corresponding to a coding area to be encoded into a plurality of divided HDR image data, encode each of the plurality of divided HDR image data by using encoding means, and record the plurality of divided HDR image data that are encoded on a recording medium in a predetermined recording format.

Abstract: The disc device comprises disc selector spindle that hold discs in a stacked state, separate lowermost disc from other discs, and supply separated lowermost disc to drive unit. The disc selector spindle includes first, second, and third support claws that move to storage position at which each support claw is stored inside center hole of disc and protrusion position at which each support claw protrudes in a region located in the vicinity of inner diameter of disc in plan view. First support claw moves to storage position and protrusion position independently of the movements of second support claw and third support claw. Second support claw is disposed so as to be shifted from third support claw in a stacking direction of disc by a thickness of one disc, and to move from storage position to protrusion position at a timing different from a timing of third support claw.

Abstract: A tape cartridge for retaining a magnetic tape, the tape cartridge being configured to be selectively positioned substantially within a tape drive, includes a cartridge body and a cartridge hub. The cartridge body includes a cartridge length from a front to a rear of the cartridge body, and a cartridge width from a first side to a second side of the cartridge body. The cartridge hub is positioned within the cartridge body. The cartridge hub is configured so that the magnetic tape is wound around the cartridge hub within the cartridge body. The cartridge hub includes a hub diameter. The cartridge length and the cartridge width provide boundaries for a maximum wound tape diameter as the magnetic tape is wound around the cartridge hub within the cartridge body. A ratio of the maximum wound tape diameter to the hub diameter is at least approximately 3.50:1.

Abstract: A computer-implemented method performed in connection with a video comprising a plurality of video frames, the computer-implemented method being performed in a computerized system comprising a processing unit and a memory, the computer-implemented method involving: using the processing unit to detect a plurality of content components within at least one of the plurality of video frames; based on a video modification instruction received from a user, modifying at least one of the plurality of the detected content components; storing an information on the modified at least one of the plurality of the detected content components in the memory; using the central processing unit to overlay the modified at least one of the plurality of the detected content components over the video; and causing the video with the overlaid modified content component to be displayed to the user.

Abstract: An approach for defining, capturing, assembling, and displaying customized video content is provided. In an embodiment, a method comprises: receiving, by a server computer, a video frame sequence that includes one or more video frames; applying, by the server computer, one or more filters to the one or more video frames to generate a video data file that captures geometry of a customizable object depicted in the one or more video frames; generating, by the server computer, customization instructions for customizing appearance of the customizable object; transmitting, from the server computer to a client computer, the video data file and the customization instructions to cause the client computer to execute the customization instructions with respect to the video data file to render a customized object, and to overlay the customized object over the customizable object in the video frame sequence.

Abstract: The present disclosure relates to systems and methods video recording and video replaying. The method may include obtaining video data from a video recording device. The method may also include generating an index item corresponding to the video data if the video data includes a key frame, wherein the index item includes an index position of the video recording device corresponding to the key frame, and an offset address used to determine an address where the key frame is stored. The method may further include storing an index table including at least the index item in a video.

Abstract: A semiconductor device includes a power gating control block and a power gating circuit. The power gating control block activates a data power control signal during a period that is set by a target code, the period being from a point in time in which the semiconductor device enters a read mode or a write mode. In addition, the power gating control block deactivates an operation power control signal in a power-down mode. The power gating circuit inhibits a data power signal from being supplied to a data input/output block based on the data power control signal. Moreover, the power gating control block inhibits an operation power signal from being supplied to an internal operation control block based on the operation power control signal.

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract: A memory system includes a memory and a controller for providing the memory with a data strobe signal; and data synchronized with an internal data strobe signal, wherein the controller includes a signal generator for generating the data strobe signal, an inverter for selectively outputting one between a non-inverted data strobe signal having the same phase as the data strobe signal and an inverted data strobe signal having an inverted phase to the phase of the data strobe signal based on an inversion signal, a delayer for delaying the inverted data strobe signal or the non-inverted data strobe signal based on a delay signal and outputting the internal data strobe signal, and a trainer for performing a verification operation on the synchronized data and generating the inversion signal and the delay signal based on the verification operation result.

Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

Abstract: Spin transfer torque memory (STTM) devices incorporating an Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are disclosed. The Insulator-Metal-Transition (IMT) device or at least one layer of Insulator-Metal-Transition (IMT) material are utilized for providing a spike current when the voltage across it exceeds the threshold voltage to reduce a critical current required for transfer torque induced magnetization switching.

Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.

Abstract: A data reading circuit and a storage unit are provided. The data reading circuit includes a being read unit, a reference current generation unit, a current adjustment unit, a reference unit, a comparison unit, and a voltage stabilization unit corresponding to the reference unit. The being read unit is connected to the current adjustment unit and the comparison unit. The reference current generation unit is connected to the current adjustment unit. The current adjustment unit is connected to the reference current generation unit, the being read unit, and the comparison unit. The reference unit is connected to the voltage stabilization unit. The comparison unit is connected to the voltage stabilization unit, the being read unit, and the current adjustment unit. The voltage stabilization unit is connected to the reference unit and the comparison unit.

Abstract: The present disclosure provides a data reading circuit and a storage unit. The data reading circuit includes a being read unit connected to a voltage stabilizing unit and configured to store data. The voltage stabilizing unit is configured to stabilize and output a current from the being read unit to a first amplifying unit. The first amplifying unit is configured to amplify and output the current from the being read unit to a comparing unit. A reference unit is connected to a second amplifying unit, to output a reference current to the second amplifying unit. The second amplifying unit is configured to amplify and output the reference current to the comparing unit. The comparing unit is configured to compare a comparing point voltage, that is based on the amplified current of the being read unit and the amplified reference current, with a reference voltage and to output comparison results.

Abstract: One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

Abstract: In various embodiments, a memory cell arrangement is provided including a memory cell driver and one or more memory cells, wherein one or more control nodes of each of the one or more memory cells are electrically conductively connected to one or more output nodes of the memory cell driver. The memory cell driver may include: a first supply node to receive a first supply voltage and a second supply node to receive a second supply voltage, a plurality of input nodes to receive a plurality of input voltages, one or more output nodes, and a logic circuit connected to the first supply node, the second supply node, the plurality of input nodes, and the one or more output nodes, wherein the logic circuit includes one or more logic gates and is configured to connect via the one or more logic gates either the first supply node or the second supply node to the one or more output nodes in response to the plurality of input voltages.

Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.

Abstract: A refresh processing method, apparatus, and system, and memory controllers are provided, to improve memory access efficiency. The refresh processing apparatus includes a plurality of memory controllers that are in one-to-one correspondence with a plurality of memory spaces. Any first memory controller in the plurality of memory controllers is configured to: receive N first indication signals and N second indication signals that are output by N memory controllers other than the first memory controller, where N is greater than or equal to 1; and determine a refresh policy of a first memory space based on at least one of the following information: the N first indication signals, the N second indication signals, and refresh indication information of the first memory space.

Abstract: A semiconductor device may include a main circuit component and a spare circuit component including a plurality of spare elements and selected to change a function of the main circuit component, wherein each of the plurality of spare elements is configured to block a source voltage supply.

Abstract: A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a given row of a memory cell array and sequential bits of one or more elements of a second matrix. The partial products can be calculated first sequentially across the set of rows and second sequentially across the bit positions of the elements of the second matrix. Alternatively, the partial products can be calculated first sequentially across the bit positions of the elements of the second matrix first and second sequentially across the set of rows. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array, and a peripheral circuit region including second metal pads, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted. The peripheral circuit region is vertically connected to the memory cell region by the metal pads directly.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Abstract: A high bandwidth register file circuit that significantly reduces the shared local read bitline RC delay to enable ultra-high performance PRFs with high port counts. In one example, the register file circuit includes read stack nfets in a multiplexer circuit instead of the memory cell causing the local read bitline RC to be independent of the number of read and write ports of the memory cell.

Abstract: A circuit includes a bit line, a pass gate coupled between the bit line and a power node having a first power voltage level, and a driver coupled between the bit line and a reference node having a reference voltage level. The pass gate couples the bit line to the power node when the first signal has the reference voltage level and decouples the bit line from the power node when the first signal has the first power voltage level. The driver receives a second signal based on a control signal, couples the bit line to the reference node when the second signal has a second power voltage level below the first power voltage level, and decouples the bit line from the reference node when the second signal has the reference voltage level. An input circuit generates the first signal independent of the control signal.

Abstract: The present technology provides an electronic device, a memory device, and a method of operating a memory device. The memory device includes a memory cell array including a variable resistance memory cell coupled to a first conductive line and a second conductive line, and a peripheral circuit configured to provide a write pulse or a read pulse to the variable resistance memory cell through the first conductive line. The write pulse is controlled to have one of a first polarity and a second polarity that are opposite to each other. The read pulse is controlled to have a polarity corresponding to a greater value of first and second amorphization start current values of the variable resistance memory cell, the first amorphization start current value being determined by a first pulse having the first polarity, the second amorphization start current value being determined by a second pulse having the second polarity.

Abstract: A device includes a first signal line, a second signal line, and a controller. The first signal line is coupled to a first storage area. The second signal line is coupled to a second storage area. The controller outputs a signal to the first signal line or the second signal line to select the first storage area or the second storage area. The first storage area may be a removable data storage card, and the second storage area may be an embedded storage area in the device. The signal is a reset signal for the selected one of the first storage area and the second storage area.

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Abstract: The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Abstract: According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the vo

Abstract: In various aspects, a voltage supply circuit may include a first controlled voltage converter circuit including a first voltage converter and a first control circuit, wherein the first control circuit is configured to receive an input voltage and control the first voltage converter to output a first output voltage having a predefined relationship to the received input voltage; and a second controlled voltage converter circuit including a second voltage converter and a second control circuit, wherein the second control circuit is configured to receive the first output voltage and control the second voltage converter to output a second output voltage having a predefined relationship to the received first output voltage.

Abstract: An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

Abstract: Methods, systems and apparatus including computer-readable mediums for partially erasing blocks in a memory system to increase reliability are provided. In one aspect, a memory system includes a memory having a plurality of blocks and a memory controller coupled to the memory. The memory controller is configured to: execute a first erase operation on a particular block in the memory, the particular block including multiple sub-blocks each having respective memory cells, one or more memory cells in the particular block being in one or more programmed states before the first erase operation, then execute a second erase operation on a first sub-block of the particular block such that first respective memory cells of the first sub-block are in an erased state after the second erase operation. The memory controller can be configured to not execute the second erase operation on the one or more other sub-blocks of the particular block.

Abstract: A memory device including at least one dummy word line over a substrate; a plurality of word lines over the dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate and classified into channel holes and dummy holes, each of the channel holes being connected to a bit line. The method including performing an erase operation on dummy cells formed as the dummy word line and the dummy holes; verifying the erase operation; and performing a program operation on at least one of the dummy cells such that the at least one dummy cell has a higher threshold voltage than main cells formed as the dummy word line and the channel holes.

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Abstract: A storage device configured to provide an improved data recovery rate includes a memory device including a plurality of memory cells and a memory controller. The memory controller includes a read operation controller for controlling the memory device to perform a read operation by applying a default read voltage or optimal read voltage to a selected word line coupled to selected memory cells among the plurality of memory cells; and an optimal read voltage operating component for determining the optimal read voltage when the read operation using the default read voltage fails, based on an average threshold voltage and cell number information which are information on a memory cell number for each of first and second distributions which are adjacent threshold voltage distributions among threshold voltage distributions that the threshold voltages of the selected memory cells form.

Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.