Abstract: A method for controlling the filling of an ion trap with a predetermined quantity of ions. The method comprises generating an ion current by transmitting ions along an ion path to an ion trap, such that ions are accumulated in the ion trap over a transmission time period, wherein the magnitude of the ion current varies in time. The method further comprises detecting at an ion detector at least some ions from the source of ions during a plurality of distinct sampling time intervals interspersed within the transmission time period, and setting the duration of the transmission time period based on the detection of ions at the ion detector. The time difference between the start of a sampling time interval and the start of an immediately subsequent sampling time interval is less than a timescale for variation of the magnitude of the ion current. A controller for controlling the filling of an ion trap with a predetermined quantity of ions and a mass spectrometer comprising the controller is also described.

Abstract: A microwave discharge lamp includes a discharge bulb which is discharged by a microwave and emits a light, a cylindrical resonant cavity which has at least a portion formed of a conductive mesh of net structure and is disposed to cover the discharge bulb, a main antenna which has one end supplied with microwave power through a bottom surface of the resonant cavity and the other end electrically contacting a side surface of the resonant cavity to be grounded, and a dummy antenna which has one end electrically grounded to the bottom surface of the resonant cavity and the other end electrically grounded to the side surface of the resonant cavity and is disposed opposite to the main antenna to be symmetrical to the main antenna about a central axis of the resonant cavity.

Abstract: A method of forming an electronic device is disclosed. The method comprises forming a barrier layer on a silicon layer, and depositing a silicon oxide layer on the barrier layer. The formation of the barrier layer on the silicon layer minimizes parasitic oxidation of the underlying silicon layer and minimizes defects in the silicon layer.

Abstract: A treatment liquid feeding system, provided with: a treatment liquid feeding device 10 having carrier-housing parts 12 for housing a carrier 70, bottle-housing parts 13 for housing a treatment liquid bottle 80 removed from a carrier 70, liquid feed parts 14 for delivering a treatment liquid to substrate treatment devices 90 from a treatment liquid bottle 80, and a transportation unit 15; and a control device configured to control the transportation unit 15 so as to remove a treatment liquid bottle 80 from the carrier 70 of a carrier-housing part 12 and transport the treatment liquid bottle 80 to a bottle-housing 13, control the transportation unit 15 so as to transport a treatment liquid bottle 80 to a liquid feed part 14, and control the transportation unit 15 so as to house a treatment liquid bottle 80 in the carrier 70 of a carrier-housing part 12.

Abstract: Methods of depositing material on a surface of a substrate are disclosed. The methods include exposing a surface of the substrate to a precursor within a reaction chamber to form adsorbed species on the surface and removing at least a portion of the adsorbed species prior to introducing a reactant to the reaction chamber.

Abstract: The disclosure provides an ultra-low K dielectric layer and a manufacturing method thereof, the manufacturing method comprising: forming an ultra-low K dielectric layer on a substrate; forming a thin oxygen layer on the upper surface of the ultra-low K dielectric layer; performing plasma purge on the ultra-low K dielectric layer after forming the thin oxygen layer using oxygen; and the plasma purge lasts for more than 2 seconds. The ultra-low K dielectric layer manufactured according to the manufacturing method provided by the disclosure has a smooth surface, overcomes the original bump defects of the ultra-low K dielectric layer, and improves the performance of the ultra-low K dielectric layer. The manufacturing method of the ultra-low K dielectric layer provided by the disclosure has a simple process, is compatible with the manufacturing process of the existing ultra-low K dielectric layer, and has operability.

Abstract: A pattern-forming method includes: forming a pattern on an upper face side of a substrate; applying a first composition to a sidewall of the pattern; forming a resin layer by applying a second composition to an inner face side of the sidewall of the pattern coated with the first composition; allowing the resin layer to separate into a plurality of phases; and removing at least one of the plurality of phases. The first composition contains a first polymer. The second composition contains a second polymer. The second polymer includes a first block having a first structural unit and a second block having a second structural unit. The polarity of the second structural unit is higher than the polarity of the first structural unit. Immediately before forming of the resin layer, a static contact angle ? (°) of water on the sidewall of the pattern satisfies inequality (1).

Abstract: A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

Abstract: There is a method for forming an oxide or chalcogenide 2D semiconductor. The method includes a step of growing on a substrate, by a deposition method, a precursor epitaxy oxide or chalcogenide film; and a step of sulfurizing the precursor epitaxy oxide or chalcogenide film, by replacing the oxygen atoms with sulfur atoms, to obtain the oxide or chalcogenide 2D semiconductor. The oxide or chalcogenide 2D semiconductor has an epitaxy structure inherent from the precursor epitaxy oxide or chalcogenide film.

Abstract: Method for gap fill includes performing in order the following: (a) performing, consecutively, a first plurality of cycles of an atomic layer deposition process on a substrate; (b) purging process gases from the atomic layer deposition process; (c) performing a first plasma treatment on the substrate by introducing a fluorine plasma in the process chamber; (d) purging process gases from the plasma treatment; (e) repeating, in order, operations (a) through (d) until a predefined plurality of cycles has been performed; (f) performing, consecutively, a second plurality of cycles of the atomic layer deposition process on the substrate; (g) purging process gases from the atomic layer deposition process; (h) performing a second plasma treatment on the substrate by introducing a fluorine plasma in the process chamber; (i) purging process gases from the plasma treatment; (j) repeating, in order, operations (f) through (i) until a predefined plurality of cycles has been performed.

Abstract: A wafer composite includes a handle substrate, an auxiliary layer formed on a first main surface of the handle substrate, and a silicon carbide structure formed over the auxiliary layer. The handle substrate is subjected to laser radiation that modifies crystalline material along a focal plane in the handle substrate. The focal plane is parallel to the first main surface. The auxiliary layer is configured to stop propagation of microcracks that the laser radiation may generate in the handle substrate.

Abstract: A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, the Six1Ge1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Six2Ge1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Six2Ge1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Six1Ge1-x1 film, the Six2Ge1-x2 film, and the silicon film.

Abstract: Disclosed are methods for reducing transfer pattern defects in a semiconductor device. In some embodiments, a method includes providing a semiconductor device including a plurality of photoresist lines on a stack of layers, wherein the plurality of photoresist lines includes a bridge defect extending between two or more photoresist lines of the plurality of photoresist lines. The method may further include forming a plurality of mask lines by etching a set of trenches in a first layer of the stack of layers, and removing the bridge defect by etching the bridge defect at a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the stack of layers.

Abstract: Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.

Abstract: An upper layer (4,5) made of non-doped III-V compound semiconductor is formed on a lower layer (3) made of non-doped III-V compound semiconductor. Impurity source gas is fed through vapor phase diffusion using an organometallic vapor-phase epitaxy device to add an impurity to the upper layer (4,5). The vapor phase diffusion is continued with the feed of the impurity source gas stopped or with a feed amount of the impurity source gas lowered.

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support.

Abstract: Included are forming, on a semiconductor substrate, an insulation film having an opening section where an opening is formed, forming a first resist on the insulation film while avoiding the opening section and the semiconductor substrate exposed via the opening section, forming a first metal on the opening section, the semiconductor substrate exposed via the opening section, and the first resist by a vapor deposition method or a sputtering method, removing, by a lift-off method, the first resist and the first metal on the first resist, forming, on the insulation film, a second resist allowing the first metal to be exposed, causing the first metal to grow a second metal by an electroless plating method, and removing the second resist, where these processings are included in the listed order.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, an inhibitor residue over gate structure and between the gate spacers, and source/drain structures on opposite sides of the gate structure. The inhibitor residue lines a sidewall of one of the gate spacers.

Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.

Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.

Abstract: A substrate drying apparatus, a substrate drying method and a storage medium are capable of sublimating a sublimable substance filled in recesses of a pattern formed on a substrate while preventing pattern collapse. A first unit includes a solution supplier which supplies a sublimable substance solution containing a sublimable substance and a solvent to a processing surface, and a first liquid remover which forms a solid film of the sublimable substance on the processing surface by removing the solvent and a processing liquid from the processing surface. A second unit includes a second liquid remover which vaporize the solvent and the processing liquid remaining in the solid film by heating the substrate, and maintaining the substrate at a temperature within a first temperature range, and a solid film remover which remove the solid film from the processing surface by heating the substrate at a temperature within a second temperature range.

Abstract: The invention has been made in view of the above problems, and provides a plasma processing method capable of preventing etching shape abnormality in a plasma processing method for forming a mask layer of a polysilicon film. The invention relates to a plasma processing method for plasma-etching a polysilicon film, the plasma processing method comprising plasma-etching the polysilicon film using a mixed gas including a halogen gas, a fluorocarbon gas, an oxygen gas, and a carbonyl sulfide gas.

Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly, and the support assembly includes a plurality of pin. The method includes securing an etching mask to a backside of the wafer, and the etching mask has an extending portion which covers a peripheral portion of the wafer. The etching mask has a plurality of circular bores extended along a vertical direction, and the etching mask is secured to the support assembly by connecting the circular bores and the pins. The method also includes performing a wet etching process on the backside of the wafer to foil a thinned wafer, wherein the thinned wafer has a peripheral portion with a first thickness and a central portion having a second thickness smaller than the first thickness.

Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.

Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.

Abstract: The disclosure provides a plane polishing method and a processing method of the silicon wafer. The plane polishing method includes steps of: depositing a hard mask on a silicon substrate to form a silicon wafer base material; forming an opening on the hard mask by photolithography or etching; carrying out an oxidation reaction on a portion of the silicon substrate exposed by the opening, forming an oxide layer having a bottom embedded in the silicon substrate and a top protruding and exposed outside the hard mask by oxidizing the silicon substrate; and polishing the oxide layer by chemical mechanical planarization. In the present disclosure, the surface formed by the oxide layer and the hard mask flat is flat, without a recess even in the case of large structures, thereby precisely controlling a shape and a depth of the cavity in accordance with an oxidation rate on a silicon substrate.

Abstract: The present invention provides a method for treating a substrate, which can remove transition metal-containing substances on a substrate with high efficiency while inhibiting cerium from remaining on the surface of the treated substrate. Furthermore, the present invention provides a method for manufacturing a semiconductor device including the method for treating a substrate, and a kit for treating a substrate that is applicable to the method for treating a substrate.

Abstract: An etching apparatus includes: a placement table serving as a lower electrode and configured to place a workpiece to be subjected to an etching processing thereon; a DC power supply configured to generate a negative DC voltage applied to the placement table; and a controller configured to: periodically apply a negative DC voltage to the placement table from the DC power supply when the etching processing on the workpiece placed on the placement table is initiated, and decrease a frequency of the negative DC voltage applied to the placement table with an elapse of processing time of the etching processing.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: The present invention relates to a method of producing a ceramic substrate, the method including: joining a metal layer to each of opposite surfaces of a ceramic base material; forming, on the metal layers, a first electrode layer and a second electrode layer having a larger volume than the first electrode layer; calculating the volumes of the first and second electrode layers; and controlling a thickness of the second electrode layer, thereby controlling warpage which may occur due to a difference between the volumes of the first and second electrode layers. The present invention can reduce the defect rate of a ceramic substrate by controlling warpage that may occur due to the difference in volume taken up by the metal layers on the opposite surfaces of the base material.

Abstract: Disclosed are an underfill method and apparatus for a semiconductor package, the underfill method includes loading a substrate; charging a filler to be filled in between the substrate and a device; applying the filler to the substrate; and subjecting the applied filler to an electric field.

Abstract: A tank includes a container part having an upper wall, a sidewall and a bottom wall to store a processing liquid therein, a liquid discharge passage installed at a position higher than a liquid surface of the processing liquid stored in the container part to discharge the processing liquid into the container part, and a gas discharge passage installed at a position higher than the liquid surface to discharge a gas into the container part. The liquid discharge passage discharges the processing liquid from the liquid discharge port so that the processing liquid is brought into contact with a portion above the liquid surface of an inner surface of the sidewall. The gas discharge passage discharges the gas from the gas discharge port so that the gas is brought into contact with a portion above the liquid surface of an inner surface of the container part.

Abstract: An apparatus for treating a substrate includes a chamber having a treating space formed therein, a substrate support unit that supports the substrate in the treating space, a plate that is located to face the substrate support unit in the treating space and that has a plurality of holes formed therein, a gas supply unit that supplies gas into the treating space through the holes, and a gas exhaust unit that exhausts the gas in the treating space through the holes.

Abstract: A method of fabricating a semiconductor device includes providing a system that includes a susceptor configured to retain a semiconductor substrate, a heating element, and a reflector integrated with the heating element, where the reflector includes a surface defined by a plurality of circumferential ridges having a separation distance that varies from a top portion of the reflector to a bottom portion of the reflector. The method further includes heating the semiconductor substrate and forming an epitaxial layer on the heated semiconductor substrate, where the heating includes emitting thermal energy from the heating element and reflecting the thermal energy from the surface of the reflector onto the semiconductor substrate, where an amount of the thermal energy received by an edge of the semiconductor substrate is more than an amount of the thermal energy received by a center of the semiconductor substrate.

Abstract: The present invention is related to a heating device for heating an object material using a laser beam, the heating device comprising a stage on which the object material is placed; a laser module for generating and outputting a laser beam; an optical module for controlling a path of the laser beam; a polygon mirror rotating around an axis of rotation and having a plurality of reflecting surfaces which reflect the laser beam; and a beam guide module for controlling an incidence range within which the laser beam reflected by the polygon mirror is incident on the object material, and an indirect heating method using a laser beam in a heating device.

Abstract: A photoresist is developed on a semiconductor wafer. The wafer is introduced into a controlled cold temperature environment and is maintained there until inelastic thermal contraction of the developed photoresist material results in reducing the critical dimension (CD) of the photoresist by not less than 10% from its value before exposure to the controlled cold temperature environment. Then the semiconductor wafer is removed from the controlled cold temperature environment.

Abstract: A substrate processing apparatus includes: a processing unit including a holder that holds a substrate and rotates the substrate, a nozzle that ejects a processing liquid, and a conductive piping unit that supplies the processing liquid to the nozzle; a controller that causes the processing unit to execute a liquid processing in which the substrate is processed by supplying the processing liquid from the nozzle to the substrate that is held and rotated by the holder, and a measuring unit that measures a flowing current generated by the processing liquid flowing through the piping unit. The controller monitors the liquid processing based on a measurement result by the measuring unit.

Abstract: Embodiments of the present disclosure relate to a method and an apparatus for monitoring plasma behavior inside a plasma processing chamber. In one example, a method for monitoring plasma behavior includes acquiring at least one image of a plasma, and determining a plasma parameter based on the at least one image.

Abstract: Embodiments include systems, devices, and methods for monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, a processing tool includes a processing chamber having a liner wall around a chamber volume, and a monitoring device having a sensor exposed to the chamber volume through a hole in the liner wall. The sensor is capable of measuring, in real-time, material deposition and removal rates occurring within the chamber volume during the wafer fabrication process. The monitoring device can be moved relative to the hole in the liner wall to selectively expose either the sensor or a blank area to the chamber volume through the hole. Accordingly, the wafer fabrication process being performed in the chamber volume may be monitored by the sensor, and the sensor may be sealed off from the chamber volume during an in-situ chamber cleaning process. Other embodiments are also described and claimed.

Abstract: A system and method include receiving, by a processing device of a manufacturing execution system (MES), a target profile associated with products, wherein the target profile comprises an identifier of a block of steps in a process to make the products and a target work-in-progress (WIP) value representing a target number of parts waiting to be processed by a group of machines used in the block of steps to make the products, identifying a move list or an assignment list that, when issued, causes the group of machines to operate to maintain a number of parts waiting for processing to match the target WIP value of the target profile.

Abstract: Systems and methods for substrate support in a millisecond anneal system are provided. In one example implementation, a millisecond anneal system includes a processing chamber having a wafer support plate. A plurality of support pins can extend from the wafer support plate. The support pins can be configured to support a substrate. At least one of the support pins can have a spherical surface profile to accommodate a varying angle of a substrate surface normal at the point of contact with the substrate. Other example aspects of the present disclosure are directed to methods for estimating, for instance, local contact stress at the point of contact with the support pin.

Abstract: A method and apparatus for detecting and correcting incoming substrate deformation is disclosed. Substrates are positioned in a first process chamber, where the presence and type of substrate bow is detected. Based upon the detection of substrate bow, and a determination of whether the substrate has a compressive bow or a tensile bow, a substrate processing program is selected for execution. The substrate processing program can be executed in the first process chamber or in a second process chamber to correct or alleviate the bow prior to or during further processing of the substrate.

Abstract: A reticle compartment defining an enclosed interior adapted to store at least two reticles in a resticle storage portion, including an inlet port, through which a purge gas can enter the enclosed enterior, and an outlet port, through which the purge gas can exit the enclosed interior, wherein the reticle compartment further includes a first diffusor plate arranged in the enclosed interior between the inlet port and the reticle storage portion, wherein the first diffusor plate is provided with openings, through which the purge gas can flow, the openings in a central section of the first diffusor plate being provided with a larger individual opening area and/or providing a large total opening area per unit area than openings in a peripheral section of the first diffusor plate.

Abstract: A robot hand is provided. The robot hand includes a transfer plate that has a loading region; an electrostatic chuck configured to adsorb a wafer disposed on the loading region of the transfer plate; and a heating element configured to heat the loading region of the transfer plate.

Abstract: Methods and apparatus for dechucking a wafer from a surface of an electrostatic chuck (ESC). In some embodiments, a method comprises reducing a pressure of a gas applied to a backside of the wafer to approximately zero psi; reducing a downward pressure in a cylinder bore of a lifting actuator to approximately atmospheric pressure while a processing volume of the processing chamber is in a vacuum state to create a constant upward force on the wafer, the constant upward force less than a breaking force of the wafer; and sweeping a voltage applied to the ESC to dechuck the wafer; and monitoring a sensor on the lifting actuator that is interposed between a chucking position of the lifting actuator and a transfer position of the lifting actuator to detect when the wafer is dechucked.

Abstract: An electrostatic chuck with a top surface adapted for Johnsen-Rahbek clamping in the temperature range of 500 C to 750 C. The top surface may be sapphire. The top surface is attached to the lower portion of the electrostatic chuck using a braze layer able to withstand corrosive processing chemistries.