Abstract: A radio frequency switch is disclosed. The RF switch uses a combination of transistor technology and a topology to create an RF switch that has a high isolation and a high voltage breakdown at frequencies including those above a gigahertz.

Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.

Abstract: A circuit assembly includes a first signal branch connecting a signal connection to an electrical load via a semiconductor switch and a second signal branch connecting the signal connection to the electrical load via a relay. When a sensor detects a polarity change in an electrical signal within a test time interval, a controller may close the semiconductor switch at a first signal time such that electrical energy is supplied to the electrical load, actuate the relay at a second signal time after the semiconductor switch has been closed, and open the semiconductor switch after the relay has been closed such that electrical energy is supplied to the electrical load solely via the second signal branch.

Abstract: A frequency converter (1) for generating an output signal (5a) from an input signal (5), the output signal (5a) having different frequency than the input signal (5), the frequency converter (1) including: an input (7) for receiving an input signal (5); a transmission line (3) formed of a non-linear medium (3a), the medium (3a) arranged such that when the input signal (5) propagates along the line (3), one or more harmonics (5a,5b) of the input signal (5) are generated; a plurality of dispersion control elements (13), the dispersion control elements (13) arranged to control the dispersion relationship of the medium (3a), to phase match the input signal (5) and the one or more harmonics (5a,5b), such that energy is transferred from the input signal (5) to the one or more harmonics (5a,5b); and an output (9) for providing the one or more harmonics (5a, 5b) as an output signal.

Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Abstract: A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.

Abstract: A circuit that includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

Abstract: Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.

Abstract: A method for preparing photoactive perovskite materials. The method comprises the step of preparing a germanium halide precursor ink. Preparing a germanium halide precursor ink comprises the steps of: introducing a germanium halide into a vessel, introducing a first solvent to the vessel, and contacting the germanium halide with the first solvent to dissolve the germanium halide. The method further comprises depositing the germanium halide precursor ink onto a substrate, drying the germanium halide precursor ink to form a thin film, annealing the thin film, and rinsing the thin film with a second solvent and a salt.

Abstract: A touch panel is manufactured by a method that decreases undesirable reflections of external light while improving the visibility of emitted light. The touch panel includes a base layer including an active region responsive to an external touch to generate an electronic signal and a peripheral region adjacent to the active region, and a first conductive pattern disposed on the active region and a second conductive pattern disposed on the peripheral region, each of the first conductive pattern and the second conductive pattern including a conductive layer having an external light reflectivity and a darkening layer disposed over the conductive layer. External light reflectivity of each of the first and second conductive patterns is lower than that of the conductive layer.

Abstract: An electro-permanent magnet (EPM) key assembly of an information handling system may comprise a pair of scissor plates operably connected to a base contact assembly including an EPM such that each of the pair of scissor plates may rotate away from one another in the presence of downward force on a key cap situated atop the pair of scissor plates for actuation of the EPM key assembly; the EPM comprising a low-coercivity magnet and a high-coercivity magnet; wherein an application of a first current pulse applied to an electrically conductive wire coiled around the low-coercivity magnet places the EPM in a first on state to assert a first magnetic field on a ferromagnetic flange operatively coupled to rotate with at least one scissor plate about a hinge; and wherein an application of a second current pulse applied to the electrically conductive wire places the EPM in a second on state to increase the magnetic field on the ferromagnetic flange.

Abstract: An electropermanent magnet key assembly of an information handling system comprising an electropermanent magnet (EPM) having a low-coercivity magnet and a high-coercivity magnet, wherein the EPM is capable of an on state generating a magnetic field and an off state disabling the magnetic field, a key cap, situated atop a pair of scissor plates, capable of downward movement, via action of the scissor plates, from a raised, neutral position in which a surface of the key cap is moved to a depressed position below the neutral position, wherein the downward movement of the key assembly may record a keystroke, a flange operably connected a first scissor plate of the pair of scissor plates and extending opposite of a hinge of the first scissor plate, such that the flange is attracted toward the magnetic field of the EPM situated beneath the pair of scissor plates to urge the first scissor plate to push the key cap to the neutral position in an on state, and a spring exerting a biasing force to rotate a rocker arm to

Abstract: A method for assembling an electro-permanent magnet (EPM) key assembly of an information handling system may comprise disposing a pair of scissor plate mounts framed onto a base contact assembly upward through a cap support plate opening within a cap support plate comprising a printed circuit board with pressure sensors to record keystrokes for mounting the EPM key assembly, operably connecting the base contact assembly to the cap support plate, disposing a ferromagnetic flange operably coupled to rotate with at least one scissor plate about a hinge downward through the cap support plate opening, operably connecting the pair of scissor plates to the base contact assembly such that each of the pair of scissor plates may rotate away from one another in the presence of downward force on a key cap, and situating the key cap atop the pair of scissor plates.

Abstract: In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

Abstract: [Problem] Provided is an electronic circuit that is able to avoid the influence on the output level of the driver for low-speed communication due to a decrease in the voltage of the driver for high-speed communication in an interface for interconnection of devices in the electronic apparatus. [Solution] An electronic circuit includes a plurality of first drivers coupled in parallel, the first drivers each including transistors coupled in series and transmitting data at a predetermined communication speed; and a second driver including transistors coupled in series and transmitting data at a communication speed lower than the communication speed of the first driver. The number of first drivers operating in parallel is sufficient for output impedance of the first drivers to meet a predetermined standard through application of an electrical potential to bodies of the transistors of the first drivers. The electrical potential causes an output level of the second driver to meet a predetermined standard.

Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

Abstract: A family of resonators and other devices which employ virtual electrodes using pixel based projection across a gap onto a material. In many embodiments, the pixels are projected onto a piezoelectric material, such as quartz crystal, by an integrated circuit die placed opposite a face of the crystal. The die projects individual pixels of electromagnetic energy onto the crystal, which vibrates and produces its own electromagnetic energy which is received by the pixels. Pixel projection onto other materials, including non-resonant materials, is also disclosed. The pixel based projected electrodes may be used in combination with, or in lieu of, conventional metal electrodes. Individual pixels may be turned on and off, and gain- and phase-controlled, in order to achieve specific desired resonator response characteristics. Many types of devices using pixel based electrode projection are disclosed—including resonators having one or more electrodes, oscillators, filters, delay lines, antennas and others.

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

Abstract: A C-element circuit for use in an oscillator or the like includes a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and an output latch for providing an output signal based on a relationship between the two input signals. A stack of input transistors is included with an outer pair of input transistors with gates connected to the first input terminal and an inner pair of input transistors with gates connected to a second input terminal. A balancing circuit operates to equalize a first delay of a change in the first input signal affecting the output signal with a second delay of a change in the second input signal affecting the output signal. Bypass control techniques are provided for using the C-element circuit with a single input.

Abstract: A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

Abstract: A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.

Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input

Abstract: There is provided a successive-approximation type AD converter and a pipeline type AD converter without delay due to sample hold. A successive-approximation type AD converter 1 includes: receiving circuits configured to output the analog input signal according to the received analog input signal; subtractors configured to calculate subtraction signals between the analog input signal in each of n successive conversions and comparison signals obtained by DA-converting the control values by DA converters; comparators configured to determine a high-low relationship between the voltages of the subtraction signals and the reference voltage; a control circuit configured to update the control values so that the comparison signals approach the analog input signal based on the comparison results; and an output register configured to output the digital output signal based on the comparison results of the comparators.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: In an embodiment, a method includes: receiving an audio frame; decomposing the received audio frame into M sub-band pulse-code modulation (PCM) audio frames, where M is a positive integer number; predicting a PCM sample of one sub-band PCM audio frame of the M sub-band PCM audio frames; comparing the predicted PCM sample with a corresponding received PCM sample to generate a prediction error sample; comparing an instantaneous absolute value of the prediction error sample with a threshold; and replacing the corresponding received PCM sample with a value based on the predicted PCM sample when the instantaneous absolute value of the prediction error sample is greater than the threshold.

Abstract: A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

Abstract: Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 17280 bits is interleaved in units of 360-bit bit groups 0 to 47. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

Abstract: A method for improving decoding and error correction in non-volatile memory, e.g., solid state drives. A map is generated for each data type that has a structure, e.g., text files. The map can be based on the underlying characteristics of this type of the data file and the mutual information between Lout to a soft decoder. The map transforms the data prior to encoding to condition the data to improve decoding and error correction.

Abstract: A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order.

Abstract: Described herein are systems configured for carrier aggregation. Systems include a multiplexing circuit having a filter assembly, switching circuit with a switching path, and a switchable impedance. The filters can be designed so that when operated simultaneously (e.g., during multi-band operation) the same inductance can be used allowing the switching network to switch in a particular inductance into the path. The described systems can include an inductance that is coupled to an output port so that when operating in single-band mode, the different paths share the same inductance. Relative to other solutions, the described systems can improve performance (e.g., reduce insertion loss), reduce the number of components in the associated module, reduce manufacturing costs, and the like.

Abstract: A radio frequency receiver is provided that comprises an antenna, an RF amplifier, at least one down conversion mixer stage and a variable notch filter. The at least one down-conversion mixer stage is arranged to act on signals provided by the RF amplifier and is tuned to a tuned frequency ft which is selected from a plurality of possible tuned frequencies corresponding to a frequency of the RF signal to be received at the antenna. The variable notch filter is arranged to act on signals passing from the antenna to the RF amplifier and has a resonance frequency fr which is selected from a plurality of possible resonance frequencies such that fr=ft in where n is a whole number between 2 and 10. The variable notch filter thereby acts to attenuate signals from the antenna at said resonance frequency.

Abstract: A high-frequency signal stimulator system has at least two mutually independent data producers, signal processing and a signal generator. The at least two mutually independent data producers are each configured to produce at least one data packet describing a high-frequency signal to be produced. The signal processing is configured to extract a signal of the data packet produced by the first of the at least two mutually independent data producers and contents of the data packet produced by the second of the at least two mutually independent data producers. The signal generator is configured to produce a high-frequency signal based on the extracted contents.

Abstract: An apparatus of user equipment (UE) includes a radio integrated circuit (IC), an adjustable external low noise amplifier (eLNA) external to the radio IC, and processing circuitry. The radio IC includes a receive signal circuit path including an adjustable gain internal low noise amplifier (iLNA), and a transmit signal circuit path including a digital-to-analog converter (DAC) circuit configured to convert digital signals to analog baseband signals for transmitting. The processing circuitry is configured to provide digital values of the digital signals to the DAC circuit and initiate adjusting gain of one or both of the iLNA and the eLNA according to the digital values.

Abstract: Embodiments of this disclosure relate to multiplexers that include acoustic wave filters for filtering radio frequency signals. In certain embodiments, a multiplexer includes a first acoustic wave filter including bulk acoustic wave resonators and a second acoustic wave filter including multilayer piezoelectric substrate surface acoustic wave resonators. The second acoustic wave filter can have a second pass band that is above a first pass band of the first acoustic wave filter. Related acoustic filter assemblies, packaged radio frequency modules, wireless communication devices, and methods are disclosed.

Abstract: A transmitter device includes a transmitter including a first oscillator circuitry, a signal processing circuitry, and a calibration circuitry, and a second oscillator circuitry. The first oscillator circuitry is configured to output a first oscillating signal. The signal processing circuitry is configured to mix calibration signals according to the first oscillating signal, in order to emit a first output signal. The calibration circuitry is configured to detect a power of the first output signal to generate coefficients, and generate the calibration signals according to the coefficients, an in-phase data signal, and a quadrature data signal. The second oscillator circuitry is disposed adjacent to the transmitter, and is configured to output a second oscillating signal. The calibration signals are configured to reduce a pulling generated by both of the first output signal and the second oscillating signal to the first oscillator circuitry.

Abstract: A method of operating a communications system includes receiving a signal at a digital predistorter (DPD), introducing predistortion to the signal using the DPD, and converting the predistorted signal to an analog signal using a digital-to-analog converter having a first bandwidth. The method also includes amplifying the analog signal, sampling the amplified signal using an analog-to-digital converter having a second bandwidth less than the first bandwidth, and extracting coefficients of the DPD from the sampled signal.

Abstract: Methods and devices for radio frequency (RF) loopback for transceivers are described. A transceiver for communicating RF signals with a target device may transmit signals at a transmit frequency and receive signals at a (different) receive frequency. The transceiver may include a waveguide diplexer for separating and combining signals based on frequency. The transceiver may be configured to couple a loopback signal from a common port of the waveguide diplexer; the loopback signal may be based on a transmit signal. The transceiver may include a loopback translator to translate the loopback signal from the transmit frequency to the receive frequency and provide the translated loopback signal to a receiver used for receiving signals from the target device. The receiver may compare the translated loopback signal with a representation of the transmit signal to generate a compensation signal. A transmitter may use the compensation signal to adjust subsequent transmit signals.

Abstract: Disclosed herein is an improved electronic device enclosure and methods for manufacturing the same. One embodiment includes a front panel; a back panel with a patterned intrusion region to improve passive audio amplification; an electrically conductive front plate; an electrically conductive back plate with an open region configured to permit transmission of radiofrequency signals; wherein the front plate couples with the front panel, the back plate couples with the back panel, the front panel hingedly couples with the back panel, and the front plate and back plate are configured to enclose an electronic device; and the front plate is sized and dimensioned to block radiofrequency radiation from exiting the front panel of the electronic device enclosure.

Abstract: Suggested is a cover for a portable terminal which is driven by receiving wireless power from a portable terminal and performs communication with an IoT device by using the portable terminal having no IoT communication module embedded therein by performing communication with the IoT device via IoT communication. The suggested cover for a portable terminal comprises: a first antenna module for generating driving power through energy harvesting with a portable terminal; and a second antenna module and a third antenna module driven by the driving power, wherein one of the first antenna module and the second antenna module collects IoT data from the portable terminal, and wherein the third antenna module transmits the IoT data, collected by one of the first antenna module and the second antenna module, to an external IoT device.

Abstract: Systems and methods for generating a microwave signal using two millimeter-wave frequencies. A first millimeter-wave up-conversion frequency, which is generated from a lower frequency source, is used to up-convert a baseband and/or intermediate signal into a first millimeter-wave signal, which is then down-converted into a microwave signal using a second millimeter-wave down-conversion frequency generated from the same lower frequency source. Each of the first and second millimeter-wave frequencies is associated with a phase noise that is higher than a phase noise associated with the lower frequency source, however, the frequency differential between the first millimeter-wave frequency and the second millimeter-wave frequency is free of the higher phase noise, as a result of the two millimeter-wave signal being generated from the single lower frequency source, thereby causing the resultant microwave signal to be free of the higher phase noise as well.

Abstract: An electronic lock can enter a lockdown mode in response to a lockdown command comprising a mechanical command, e.g. a button or door handle being pressed on the lock in a predefined time-series sequence, or touching the lock in a time-series sequence). Alternatively, an audio or visual command can be issued, e.g. saying certain words or making a hand gesture. The lock may require additional authentication before executing the lockdown command, e.g. recognizing an authorized electronic key. Other embodiments are also provided.

Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.

Abstract: A communications apparatus, including a phase correction unit, a first radio frequency channel, a first analog bridge, a second radio frequency channel, and a second analog bridge. A first signal is sent to a first input end by using the first radio frequency channel, and is divided into at least two channels of first sub-signals by using the first analog bridge, and the at least two channels of first sub-signals are respectively output from at least two first output ends to at least two first antenna arrays. Similarly, a second signal is divided into at least two channels of second sub-signals by using the second analog bridge, and the at least two channels of second sub-signals are output to at least two second antenna arrays. A first channel of first sub-signal and a first channel of second sub-signal are coupled to the phase correction unit by using a coupler.

Abstract: Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Such UWB systems through their receivers may operate in the presence of interfering signals and should provide for robust communications. Accordingly, an accurate and sharp filter that operates at low power is required and beneficially one that does not require a highly accurate power heavy clock. Further, many UWB applications require location and/or range finding of other elements and it would therefore be beneficial to provide a UWB based range finding and/or location capability removing the requirement to add additional device complexity and, typically significant, power consumption.

Abstract: A transmitter stores mappings of distinct values of an information signal to corresponding ones of distinct combinations of K chirps taken from M chirps that are different from each other, such that each of the distinct values is mapped to a corresponding one of the distinct combinations of K chirps. The transmitter receives a distinct value among the distinct values of the information signal. The transmitter selects, based on the mappings, a distinct combination of K chirps among the distinct combinations of K chirps that is mapped to the distinct value. The transmitter sums the K chirps of the distinct combination of K chirps to produce a symbol that represents the distinct value. The transmitter modulates the symbol to produce a modulated symbol, and transmits the modulated symbol. A receiver receives a modulated symbol that conveys a distinct value, and recovers the distinct value using stored mappings.

Abstract: A small cell base station antenna includes a first backplane, a first linear array of radiating elements extending forwardly from the first backplane, a second backplane that is opposite the first backplane and a second linear array of radiating elements extending forwardly from the second backplane. The first backplane is inclined at a first oblique angle with respect to a vertical axis and the second backplane is inclined at a second oblique angle with respect to the vertical axis.