Abstract: An integrated circuit includes a drift region in a substrate, a drain in the substrate which includes a doped drain well, the doped drain well including a first zone, having a first concentration of a first dopant, and a second zone, having a second concentration of the first dopant, where the first concentration is smaller than the second concentration, and a gate electrode over the drift region and being separated from the doped drain well in a direction parallel to a top surface of the substrate by a distance greater than 0.

Abstract: A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode intersecting the active fin and extending in a second direction, source/drain regions disposed on the active fin on both sides of the gate electrode, and a contact plug disposed on the source/drain regions. The contact plug has at least one side extending in the second direction which has a step portion having a step shape.

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).

Abstract: The present disclosure provides a thin film transistor and a fabrication method thereof, an array substrate and a fabrication method thereof, and a display panel. The method for fabricating a thin film transistor includes: forming an active layer including a first region, a second region and a third region on a substrate; forming a gate insulating layer on a side of the active layer away from the substrate; forming a gate electrode on a side of the gate insulating layer away from the active layer; and ion-implanting the active layer from a side of the gate electrode away from the active layer, so that the first region is formed into a heavily doped region, the second region is formed into a lightly doped region, and the third region is formed into an active region.

Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.

Abstract: A thin film transistor includes an active layer, a gate electrode spaced apart from and partially overlapped with the active layer, and a gate insulating film between the active layer and the gate electrode, wherein the active layer includes a channel portion overlapped with the gate electrode, a conductorization portion which is not overlapped with the gate electrode, and a gradient portion between the channel portion and the conductorization portion and not overlapped with the gate electrode, the conductorization portion and the gradient portion of the active layer are doped with a dopant, the gate insulating film covers an upper surface of the active layer facing the gate electrode during doping of the active layer, and in the gradient portion, a concentration of the dopant increases along a direction from the channel portion toward the conductorization portion. A display device may also include the thin film transistor.

Abstract: A charge trapping non-volatile organic memory device according to the present invention has a structure in which an organic matter-based blocking layer, a trapping layer, and a tunneling layer are sequentially positioned between a gate and an organic semiconductor layer positioned on an insulating substrate, the trapping layer including a metal oxide and a polymer, and has an organic-inorganic composite film in which the metal oxide is dispersed in a polymer matrix in units of atoms.

Abstract: A semiconductor device includes: a p-type region including a super-lattice pseudo mixed crystal region in which a first layer and a second layer are alternately stacked. The first layer includes a gallium oxide based semiconductor. The second layer includes a p type semiconductor made of a material different from the first layer.

Abstract: A tunnel oxide passivated contact solar cell includes a semiconductor substrate, an emitter film layer, an anti-reflective layer, a first electrode, a tunnel oxide layer, a semiconductor film layer and a second electrode. The semiconductor substrate is a first type doped semiconductor, and the first surface of the semiconductor substrate includes a zigzag structure. The emitter film layer is a second type doped semiconductor film. The anti-reflective layer is provided with a first opening. A part of the first electrode is in the first opening and electrically connected to the emitter film layer. The tunnel oxide layer has a thickness ranging from 1.3 nm to 1.6 nm, the thickness difference measured is less than 4%, and the tunnel oxide layer is made by an atomic layer deposition process. The semiconductor film layer is a first type doped semiconductor. The second electrode is electrically connected to the semiconductor film layer.

Abstract: Structures for a photodetector and methods of fabricating a structure for a photodetector. A photodetector includes a photodetector pad coupled to a waveguide core and a light-absorbing layer coupled to the photodetector pad. The light-absorbing layer has a body, a first taper that projects laterally from the body toward the waveguide core, and a second taper that projects laterally from the body toward the waveguide core. The photodetector pad includes a tapered section that is laterally positioned between the first taper and the second taper of the light-absorbing layer.

Abstract: The present disclosure relates to an all-back-contact photovoltaic device that includes, in order, a substrate, a first electrode having a first surface, an insulator, a second electrode having a second surface, and an active material, where the insulator and the second electrode form a cavity, the active material substantially fills the cavity and is in physical contact with the first surface and the second surface, the insulator includes a first layer and a second layer with the second layer positioned between the first layer and the second contact, and the first layer is constructed of a first material that is different than a second material used to construct the second layer.

Abstract: Disclosed herein are lattice-anchored materials that combine cesium lead halide perovskites with lead chalcogenide colloidal quantum dots (CQDs) that surprisingly exhibit stability exceeding that of the constituent materials. The CQDs keep the perovskite in its desired cubic phase, suppressing the transition to the undesired, lattice-mismatched, phases. These composite materials exhibit an order of magnitude enhancement in air stability for the perovskite, showing greater than six months' stability in room ambient as well as being stable for more than five hours at 200° C. in air. The perovskite prevents oxidation of the CQD surfaces and reduces the nanoparticles' agglomeration under 100° C. by a factor of five compared to CQD controls. The matrix-protected CQDs exhibit 30% photoluminescence quantum efficiency for a CQD solid emitting at infrared wavelengths.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

Abstract: A photoelectric conversion device includes: a fluorescent light guide plate that has a plate-shaped structure in which fluorescent substances that absorb sunlight and emit fluorescent light are dispersed and which is formed of a material having a refractive index different from a refractive index of an outside, the fluorescent light emitted from the fluorescent substances being concentrated onto an edge surface to be emitted when the sunlight is incident; a first photoelectric cell configured to generate power by being irradiated with the sunlight; a lens layer configured such that light incident from an outer surface is concentrated onto the first photoelectric cell; a second photoelectric cell configured to generate power by being irradiated with the fluorescent light emitted from the edge surface of the fluorescent light guide plate; and power output units configured to extract power obtained in the photoelectric cells.

Abstract: A photovoltaic module comprises one or more spectrum splitting devices disposed adjacent a first side of the photovoltaic module; and a plurality of photovoltaic cells disposed adjacent a second side of the photovoltaic module opposite the first side and such that the photovoltaic cells are spaced from the one or more spectrum splitting devices, wherein at least one of the photovoltaic cells comprise a bifacial photovoltaic cell, wherein the one or more spectrum splitting devices are configured to selectively direct incident energy to one or more of the photovoltaic cells, and wherein a spatial configuration of the one or more spectrum splitting devices and the plurality of photovoltaic cells are configured based on an optimization parameter.

Abstract: A diode device may be provided, including a semiconductor substrate including a well region arranged therein, a first doped region and a second doped region arranged within the well region, a first contact region arranged within the first doped region, and an isolation structure arranged within the first doped region, where an oxide layer may line a surface of the isolation structure. The first doped region and the first contact region may have a first conductivity type, and the well region and the second doped region may have a second conductivity type different from the first conductivity type. A doping concentration of the first contact region may be higher than a doping concentration of the first doped region, and a part of the first doped region may be arranged between the first contact region and the well region.

Abstract: A method for preparing a P-type crystalline silicon rear electrode, comprising: printing an all-aluminum paste on a P-type crystalline silicon rear passivation layer, then printing a linear interlayer-glass paste on the all-aluminum paste, and finally overprinting rear silver electrodes on the linear middle layer-glass paste. In a solar cell prepared using the method, good contact with silver and aluminum is kept without causing damage to the passivation layer and compromising the conductivity. In the present invention, a complete all-aluminum back surface field can be formed, leading to an improved field passivation property of an electrode region and reduced carrier recombination.

Abstract: Disclosed herein are an apparatus for detecting radiation and a method of making it. The method may comprise forming a recess into a semiconductor substrate, wherein a portion of the semiconductor substrate extends into the recess and is surrounded by the recess; forming a semiconductor single crystal in the recess, the semiconductor single crystal having a different composition from the semiconductor substrate; forming a first doped semiconductor region in the semiconductor substrate; forming a second doped semiconductor region in the semiconductor substrate; wherein the first doped semiconductor region and the second doped semiconductor region form a p-n junction that separates the portion from the rest of the semiconductor substrate.

Abstract: A display panel, a light-emitting device, and a driving method thereof are provided. The light-emitting device includes a substrate, and a first electrode, a first light-emitting unit, a connecting layer, a second light-emitting unit, and a second electrode stacked up sequentially on the substrate. Polarities of the first electrode and the second electrode are opposite and reverse periodically in order that the first light-emitting unit and the second light-emitting unit illuminate alternately.

Abstract: A device for transferring micro light-emitting diodes includes a collection tube and an elastic port. The collection tube has a first end and a second end arranged oppositely, and a caliber of the collection tube is greater than a diameter of the micro light-emitting diodes. The elastic port is disposed at the first end, and a caliber of the elastic port is less than the diameter of the micro light-emitting diodes. The micro light-emitting diodes are pressed into the collection tube from the elastic port. The collection tube can store the micro light-emitting diodes. The device can effectively improve transfer speed.

Abstract: A method of manufacturing a chip scale light-emitting diode package is provided. The method of manufacturing chip scale light-emitting diode package includes: manufacturing a lens molding sheet including intaglios on one surface thereof; forming a lens layer having lens portions on one surface thereof and a flat surface on a surface opposite thereto by applying a light-transmitting resin to the intaglios; forming an adhesive layer on the flat surface of the lens layer; arranging light-emitting diode chips, each having a first surface and a second surface opposite to the first surface, on the adhesive layer in such a way that the light-emitting diode chips correspond to the lens portions and the second surface is attached to the adhesive layer, wherein a first electrode pad and a second electrode pad are formed on the first surface; and manufacturing a chip array sheet by forming a molding part on the adhesive layer to cover outer surfaces of the light-emitting diode chips.

Abstract: An optoelectronic semiconductor component may include an emitter unit and a reflector. The emitter unit may include a semiconductor layer sequence having two opposing main sides, multiple lateral surfaces, and an active zone for generating radiation. The emitter unit may include electrical contact surfaces located on the main sides. The reflector may cover the main sides and all lateral surfaces apart from up to at least 90% of a single lateral surface designed for radiation emission.

Abstract: In an embodiment a light emitting diode includes an n-type n-layer, a p-type p-layer and an intermediate active zone configured to generate ultraviolet radiation, a p-type semiconductor contact layer having a varying thickness and a plurality of thickness maxima directly located on the p-layer and an ohmic-conductive electrode layer directly located on the semiconductor contact layer, wherein the n-layer and the active zone are each of AlGaN and the p-layer is of AlGaN or InGaN, wherein the semiconductor contact layer is a highly doped GaN layer, and wherein the thickness maxima have an area concentration of at least 104 cm?2.

Abstract: An InGaN-based LED epitaxial wafer and a fabrication method thereof are disclosed, wherein the InGaN-based LED epitaxial wafer includes: a substrate; an InGaN layer, formed on a surface of the substrate, having an In content between 40% and 90%, so as to ensure that the LED epitaxial wafer is capable of emitting long-wavelength light or near-infrared rays; a p-type metal oxide layer, formed on a surface of the InGaN layer facing away from the substrate, acting as a hole injection layer for the InGaN layer.

Abstract: Disclosed are a light-emitting device, a template of the light-emitting device and preparation methods thereof. The template of the light-emitting device comprises a substrate; a GaN-based semiconductor layer and a mask layer provided on the substrate, where the mask layer comprises a plurality of mask openings provided at intervals, and the plurality of mask openings are filled with the GaN-based semiconductor layer; and a sacrificial layer provided on a surface of the GaN-based semiconductor layer away from the substrate and located in the plurality of mask openings provided at intervals.

Abstract: An embodiment of the present disclosure provides a light emitting diode chip, including: a light emitting functional layer including a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, and a second semiconductor layer including a plurality of second semiconductor patterns which are arranged at intervals; a first electrode layer including a first electrode pattern electrically coupled to the first semiconductor layer; a second electrode layer disposed on a side, away from the light emitting layer, of the second semiconductor layer and including a plurality of second electrode patterns in one-to-one correspondence with the second semiconductor patterns, and the second electrode patterns are electrically coupled to the second semiconductor patterns correspondingly. Embodiments of the present disclosure further provide a method for manufacturing a light emitting diode chip and a display device.

Abstract: A light-emitting diode includes a light-transmissive substrate, a light-emitting unit disposed on the light-transmissive substrate, an insulating layer, a first electrode and a second electrode. The insulating layer includes a first insulating portion and a second insulating portion which respectively cover an upward surface and a lateral surface of the light-emitting unit. The first and second electrodes are separately disposed on the insulating layer. At least one of the first and second electrodes extends on the first insulating portion and over a juncture between the first insulating portion and the second insulating portion.

Abstract: A display device includes pixel electrodes disposed on a substrate, light-emitting diode elements disposed on the pixel electrodes, an insulating film disposed on at least a side of each of the pixel electrodes and disposed on at least a side of each of the light-emitting diode elements, partition walls disposed on the insulating film, and a common electrode disposed on the partition walls and the light-emitting diode elements.

Abstract: An ink includes a solvent, light-emitting elements included in the solvent, and polymer resins included in the solvent. Each of the light-emitting elements includes semiconductor layers, and an insulating film at least partially surrounding outer surfaces of the semiconductor layers.

Abstract: A particle layer is positioned over a light output surface of a light emitting diode. A transparent protection layer positioned between and in contact with the light output surface and the particle layer. The particle layer comprises a multitude of optically scattering or luminescent particles and a thin coating layer of transparent material coating particles of the multitude. The particles are characterized by a D50 greater than about 1.0 ?m and less than about 30. ?m; the coating layer has a thickness less than about 0.20 ?m. The protection layer is less than about 0.05 ?m thick and includes one or more materials different from material of the coating layer. The protection and coating layers can each include one or more metal or semiconductor oxides. Oxide precursor reactivities, with respect to the corresponding light output surface, are less for protection layer material than for coating layer material.

Abstract: A display device includes: a substrate; a plurality of pixels on the substrate, and each of the pixels including first to third sub-pixels each including at least one light emitting diode configured to emit light; and a color conversion layer including first to third color conversion patterns respectively corresponding to the first to third sub-pixels, each of the first to third color conversion patterns configured to transmit the light or convert the light into light of a different color. The light emitting diode of each of the first to third sub-pixels is coupled to a first electrode and a second electrode. At least one of the first to third color conversion patterns includes a perovskite compound.

Abstract: A display apparatus including a substrate, a first sub-pixel, a second sub-pixel, and a third sub-pixel disposed on the substrate and configured to emit red light, green light, and blue light, respectively, partition walls disposed between the first sub-pixel, the second sub-pixel, and the third sub-pixel, and configured to not transmit light, in which the first sub-pixel, the second sub-pixel, and the third sub-pixel include a first light emitting cell, a second light emitting cell, and a third light emitting cell, respectively, and a height of each of the first, second, and third light emitting cells is lower than a height of the partition walls, and a difference between the height of the partition walls and the height of each of the first, second, and third light emitting cells is less than 100 ?m.

Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.

Abstract: Provided is a silica glass member for hermetic sealing of an ultraviolet SMD LED element to be suitably used for hermetic sealing of, and as a transmission window material for, a surface mount-type package (SMD) having an ultraviolet LED mounted thereon and configured to emit ultraviolet light in a wavelength range of from 200 nm to 350 nm.

Abstract: A vertical light-emitting diode structure with a metal layer capable of testing and protecting sidewalls comprises a light-emitting diode element, a sidewall passivation layer, a welding electrode and a metal protective layer, which mainly allows the metal protective layer to be electrically connected to the welding electrode, and the metal protective layer covers and protects a chip side edge and a carrier board side edge of the light-emitting diode element with the sidewall passivation layer in between. Accordingly, through coating and protection of the metal protective layer, the problem of potential failure of the sidewall passivation layer of the light-emitting diode element during electroplating, electroless plating process or other environmentally rigorous processes can be solved, and the metal protective layer can provide test contacts, a quality of the sidewall passivation layer is evaluated by detecting forward bias (Vf) and reverse leakage current (Ir) of the light-emitting diode element.

Abstract: The present application discloses a drive backplane and a preparation method thereof, a display panel, and a display device. The drive backplane includes a flexible substrate provided with a first via hole; a first passivation layer located on a side of the flexible substrate and provided with a second via hole, an orthographic projection of the second via hole being at least partially overlapped with an orthographic projection of the first via hole; a thin film transistor located on a side, facing away from the flexible substrate, of the first passivation layer; and an electrical connecting structure, including a signal trace and a connecting terminal.

Abstract: A display panel, a manufacturing method thereof and a display device. The display panel includes a first region and a second region. The second region includes a driving circuitry layer and a first light-emitting unit located on a base substrate, the first region includes a plurality of second light-emitting units located on the base substrate, the second light-emitting unit is electrically coupled to the driving circuitry layer through a transparent conductive layer, the transparent conductive layer includes at least two conductive sub-layers laminated one on another and insulated from each other, each conductive sub-layer includes at least one transparent conductive line, and each transparent conductive line is coupled to a corresponding second light-emitting unit.

Abstract: A method of fabricating a two dimensional thermoelectric device includes forming dissimilar atomic layers having quantum electron transport properties, and forming a well-defined interface between the dissimilar atomic layers for effecting a thermoelectric transport by exploiting a gradient in the material parameters between the layers. The resulting device defines an inclusion matrix of the dissimilar atomic layers such that the inclusion layer is confined within a matrix formed by the other atomic layer.

Abstract: A thermoelectric generator includes: a heat-receiving plate (2) having a heat-receiving surface (2A) configured to receive radiant heat; a thermoelectric generation module provided to a surface of the heat-receiving plate (2) opposite from the heat-receiving surface (2A) and having an area smaller than an area of the heat-receiving plate (2); a cooling plate provided to a surface of the thermoelectric generation module opposite from a surface where the heat-receiving plate (2) is provided; and a temperature equalizer (22) provided to the heat-receiving plate (2) and configured to equalize a temperature of the heat-receiving surface (2A).

Abstract: A terahertz detector and a method of manufacturing a terahertz detector, wherein the terahertz detector including a substrate (2) and at least one detection unit. Each detection unit includes: a channel material (1) arranged on the substrate, two electrodes (3, 4) respectively in ohmic contact with both ends of the channel material (1) in a longitudinal direction, and a three-dimensional grapheme (5) in direct or indirect thermal contact with the channel material (1).

Abstract: A superconducting circuit includes a first port and a plurality of second ports; a plurality of filter poles, each filter pole comprising an inductor and a capacitor connected in parallel, between the first port and a second port in the plurality of second ports; an admittance inverter comprising at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter linking two successive filter poles together. The plurality of filter poles and associated admittance inverters define a plurality of current branches so that, when operating as a demultiplexer, an input electrical current input though the first port is routed to a selected one of the plurality of the plurality of second ports by an application of a first set of magnetic flux biases.

Abstract: A subelement (1) for an Nb3Sn-containing superconductor wire includes an Sn-containing core (2), an inner matrix (5) which includes Cu and surrounds the Sn-containing core (2), a region (7) of mutually abutting Nb-containing rod elements (8, 30), which surrounds the inner matrix (5), where the Nb-containing rod elements (8, 30) are each configured with an Nb-containing core filament (9; 31) and a Cu-containing filament casing (10), an outer matrix (6) which includes Cu and surrounds the region (7) of Nb-containing rod elements (8, 30). The Sn-containing core (2) has a core tube (3) into which an Sn-containing powder (4) has been introduced, the Sn-containing powder (4) being in a compacted state. This provides a subelement for an Nb3Sn-containing superconductor wire which cost-effectively yields an improved superconducting current carrying capacity.

Abstract: Provided is a piezoelectric film capable of realizing an electroacoustic conversion film with an excellent heat dissipation property, in which a sufficient sound pressure with respect to an input operating voltage is obtained. The piezoelectric film is a piezoelectric film including a polymer-based piezoelectric composite material which contains piezoelectric particles in a matrix containing a polymer material, electrode layers which are laminated on both surfaces of the polymer-based piezoelectric composite material, and a protective layer laminated on a surface of at least one electrode layer, in which in a case where a cross section of the piezoelectric film is observed with a scanning electron microscope, at least one electrode layer has a plurality of projections directed toward the protective layer, and the number of projections is in a range of 2 to 40 per visual field of 85 ?m in the cross section.

Abstract: The present invention provides a polymer-based piezoelectric composite material from which a piezoelectric film capable of outputting a higher sound pressure is obtained in a case of using a piezoelectric speaker, a piezoelectric film formed of the polymer-based piezoelectric composite material, and a piezoelectric speaker and a flexible display which are formed of the piezoelectric film. The polymer-based piezoelectric composite material of the present invention is a polymer-based piezoelectric composite material including a polymer matrix which contains a polymer having a unit represented by Formula (1), and at least one unit selected from the group consisting of, a unit represented by Formula (2-1), a unit represented by Formula (2-2), and a unit represented by Formula (2-3), and piezoelectric particles.

Abstract: The present invention provides a polymer-based piezoelectric composite material from which a piezoelectric film capable of outputting a higher sound pressure is obtained in a case of using a piezoelectric speaker, a piezoelectric film formed of the polymer-based piezoelectric composite material, and a piezoelectric speaker and a flexible display which are formed of the piezoelectric film. The polymer-based piezoelectric composite material of the present invention is a polymer-based piezoelectric composite material including a polymer matrix which contains a polymer containing a group represented by Formula (1), and piezoelectric particles. *-L1-CR1R2—CN??Formula (1) In Formula (1), L1 represents a divalent linking group excluding a divalent aliphatic hydrocarbon group. R1 and R2 each independently represent a hydrogen atom, an alkyl group, or an aryl group.

Abstract: Provided are a polymer-based piezoelectric composite material and a piezoelectric film which have high productivity and are capable of suppressing degradation of piezoelectric conversion efficiency in an environment where the temperature and the humidity are severe. The polymer-based piezoelectric composite material is a polymer-based piezoelectric composite material including piezoelectric particles in a matrix containing a polymer material, in which the polymer-based piezoelectric composite material contains greater than 500 ppm and 10000 ppm or less of a substance on a mass basis which has an SP value of less than 12.5 (cal/cm3)1/2 and is in a liquid state at room temperature, voids are formed in the polymer-based piezoelectric composite material, and an area ratio of the voids in a cross section of the polymer-based piezoelectric composite material is 0.1% or greater and 20% or less.

Abstract: A semiconductor device includes a storage element on a substrate. The storage element has a tapered upper end structure. The tapered upper end structure includes a top electrode and a spacer surrounding the top electrode. A gap-fill dielectric layer is disposed around the spacer. A conductive cap layer covers the top electrode and the spacer. An inter-metal dielectric (IMD) layer is disposed on the conductive cap layer. A metal interconnection is disposed in the IMD layer and electrically connected to the top electrode through the conductive cap layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A current sensor package, comprises a current path and a sensing device. The sensing device is spaced from the current path, and the sensing device is configured for sensing a magnetic field generated by a current flowing through the current path. Further, the sensing device comprises a sensor element. The sensing device is electrically connected to a conductive trace. An encapsulant extends continuously between the current path and the sensing device.